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Chanhee Oh
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2000 – 2009
- 2006
- [j7]Haldun Haznedar, Martin Gall, Vladimir Zolotov, Pon Sung Ku, Chanhee Oh, Rajendran Panda:
Impact of stress-induced backflow on full-chip electromigration risk assessment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1038-1046 (2006) - 2005
- [c22]Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Amir Grinshpon, Ilan Algor, Rafi Levy, Chanhee Oh:
Pessimism reduction in crosstalk noise aware STA. ICCAD 2005: 954-961 - [c21]Mini Nanua, David T. Blaauw, Chanhee Oh:
Leakage Current Modeling in PD SOI Circuits. ISQED 2005: 113-117 - 2004
- [j6]Murat R. Becer, Ravi Vaidyanathan, Chanhee Oh, Rajendran Panda:
Crosstalk noise control in an SoC physical design flow. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4): 488-497 (2004) - [j5]Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj:
Postroute gate sizing for crosstalk noise reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12): 1670-1677 (2004) - [c20]Alexey Glebov, Sergey Gavrilov
, Vladimir Zolotov, Chanhee Oh, Rajendran Panda, Murat R. Becer:
False-Noise Analysis for Domino Circuits. DATE 2004: 784-789 - [c19]Alexey Glebov, Sergey Gavrilov
Delay noise pessimism reduction by logic correlations. ICCAD 2004: 160-167 - [c18]Chanhee Oh, Haldun Haznedar, Martin Gall, Amir Grinshpon, Vladimir Zolotov, Pon Sung Ku, Rajendran Panda:
A Methodology for Chip-Level Electromigration Risk Assessment and Product Qualification. ISQED 2004: 232-237 - 2003
- [j4]David T. Blaauw, Chanhee Oh, Vladimir Zolotov, Aurobindo Dasgupta:
Static electromigration analysis for on-chip signal interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(1): 39-48 (2003) - [j3]David T. Blaauw, Supamas Sirichotiyakul, Chanhee Oh:
Driver modeling and alignment for worst-case delay noise. IEEE Trans. Very Large Scale Integr. Syst. 11(2): 157-166 (2003) - [c17]Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj:
Post-route gate sizing for crosstalk noise reduction. DAC 2003: 954-957 - [c16]Murat R. Becer, Ravi Vaidyanathan, Chanhee Oh, Rajendran Panda:
Signal integrity management in an SoC physical design flow. ISPD 2003: 39-46 - [c15]Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj:
Post-Route Gate Sizing for Crosstalk Noise Reduction. ISQED 2003: 171-176 - [c14]Chanhee Oh, David T. Blaauw, Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Aurobindo Dasgupta:
Static Electromigration Analysis for Signal Interconnects. ISQED 2003: 377-382 - 2002
- [j2]Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Rajendran Panda, David T. Blaauw:
Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits. IEEE Trans. Very Large Scale Integr. Syst. 10(2): 79-90 (2002) - [c13]Vladimir Zolotov, David T. Blaauw, Supamas Sirichotiyakul, Murat R. Becer, Chanhee Oh, Rajendran Panda, Amir Grinshpon, Rafi Levy:
Noise propagation and failure criteria for VLSI designs. ICCAD 2002: 587-594 - [c12]Vladimir Zolotov, David T. Blaauw, Rajendran Panda, Chanhee Oh:
Noise Injection and Propagation in High Performance Designs. ISQED 2002: 425-430 - [c11]Alexey Glebov, Sergey Gavrilov
False-Noise Analysis Using Resolution Method. ISQED 2002: 437-442 - 2001
- [c10]Supamas Sirichotiyakul, David T. Blaauw, Chanhee Oh, Rafi Levy, Vladimir Zolotov, Jingyan Zuo:
Driver Modeling and Alignment for Worst-Case Delay Noise. DAC 2001: 720-725 - [c9]Alexey Glebov, Sergey Gavrilov
False-Noise Analysis using Logic Implications. ICCAD 2001: 515- - [c8]Murat R. Becer, David T. Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov, Jingyan Zuo, Rafi Levy, Ibrahim N. Hajj:
A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance. ISQED 2001: 158-163 - 2000
- [c7]Rafi Levy, David T. Blaauw, Gabi Braca, Aurobindo Dasgupta, Amir Grinshpon, Chanhee Oh, Boaz Orshav, Supamas Sirichotiyakul, Vladimir Zolotov:
ClariNet: a noise analysis tool for deep submicron design. DAC 2000: 233-238 - [c6]David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Chanhee Oh, Rajendran Panda:
Slope Propagation in Static Timing Analysis. ICCAD 2000: 338-343
1990 – 1999
- 1999
- [c5]Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David T. Blaauw:
Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing. DAC 1999: 436-441 - 1998
- [c4]David T. Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards:
Emerging power management tools for processor design. ISLPED 1998: 143-148 - 1996
- [j1]Chanhee Oh, M. Ray Mercer:
Efficient logic-level timing analysis using constraint-guided critical path search. IEEE Trans. Very Large Scale Integr. Syst. 4(3): 346-355 (1996) - 1995
- [c3]Jaehong Park, Chanhee Oh, M. Ray Mercer:
Improved sequential ATPG using functional observation information and new justification methods. ED&TC 1995: 262-266 - 1994
- [c2]Ronn B. Brashear, Noel Menezes, Chanhee Oh, Lawrence T. Pillage, M. Ray Mercer:
Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis. EDAC-ETC-EUROASIC 1994: 332-337
1980 – 1989
- 1989
- [c1]Chanhee Oh, Nagaraj Nandhakumar, Jake K. Aggarwal:
Integrated modelling of thermal and visual image generation. CVPR 1989: 356-362
Coauthor Index
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