Article

Post-route gate sizing for crosstalk noise reduction

Authors:

Ibrahim N. HajjAuthors Info & Claims

DAC '03: Proceedings of the 40th annual Design Automation Conference

Pages 954 - 957

https://doi.org/10.1145/775832.776071

Published: 02 June 2003 Publication History

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Abstract

Gate sizing is a practical and a feasible crosstalk noise repair technique in the post route design stage, especially for block level sea-of-gates designs. The difficulty in gate sizing for noise reduction is that by increasing a driver size, noise at the driver output is reduced, but noise injected by that driver on other nets is increased. This can create cyclical dependencies between nets in the circuit with noise violations. In this paper, we propose a fast and effective heuristic post-route gate sizing algorithm that uses a graph representation of the noise dependencies between nodes. Our method utilizes gate sizing in both directions and works in linear time as a function of the number of gates. The effectiveness of the algorithm is shown on several industrial high performance designs.

References

[1]

P. Saxena and C. L. Liu. Crosstalk minimization using wire perturbations. In Proceedings of Design Automation Conference DAC, pages 100--103, 1999.

Digital Library

Google Scholar

[2]

C. J. Alpert, A. Devgan, and S. T. Quay. Buffer insertion for noise and delay optimization. In Proceedings of Design Automation Conference DAC, pages 362--367, 1998.

Digital Library

Google Scholar

[3]

T. Xiao and M. Marek-Sadowska. Gate sizing to eliminate crosstalk induced timing violation. In Proceedings of ICCD, pages 186--191, 2001.

Digital Library

Google Scholar

[4]

M. Hashimoto, M. Takahashi, and H. Onodera. Crosstalk noise optimization by post-layout transistor sizing. In Proceedings of ISPD, pages 126--130, 2002.

Digital Library

Google Scholar

[5]

S. Alwar, D. Blaauw, A. Dasgupta, A. Grinshpon, R. Levy, C. Oh, B. Orshav, S. Sirichotiyakul, and V. Zolotov. Clarinet: A noise analysis tool for deep submicron design. In Proceedings of Design Automation Conference DAC, pages 233--238, June 2000.

Digital Library

Google Scholar

[6]

G. Even, J. Naor, B. Schieber, and M. Sudan. Approximating minimum feedback sets and multi-cuts in directed graphs. In Int. Conf. on Integer Prog. and Combinatorial Optimization, pages 14--28, 1995.

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Cited By

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Zhang TSapatnekar S(2007)Simultaneous shield and buffer insertion for crosstalk noise reduction in global routingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.89864115:6(624-636)Online publication date: 1-Jun-2007
https://dl.acm.org/doi/10.1109/TVLSI.2007.898641
Sinha DZhou HTang T(2005)Yield driven gate sizing for coupling-noise reduction under uncertaintyProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120803(192-197)Online publication date: 18-Jan-2005
https://dl.acm.org/doi/10.1145/1120725.1120803
Gyure AKasnavi ALo STehrani PShu WShahram MWang JZedja J(2005)Noise Library Characterization for Large Capacity Static Noise Analysis ToolsProceedings of the 6th International Symposium on Quality of Electronic Design10.1109/ISQED.2005.85(28-34)Online publication date: 21-Mar-2005
https://dl.acm.org/doi/10.1109/ISQED.2005.85
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Index Terms

Post-route gate sizing for crosstalk noise reduction
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
2. Mathematics of computing
  1. Discrete mathematics
    1. Graph theory
      1. Paths and connectivity problems

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Information & Contributors

Information

Published In

DAC '03: Proceedings of the 40th annual Design Automation Conference

June 2003

1014 pages

ISBN:1581136889

DOI:10.1145/775832

General Chair:
Ian Getreu
Ambric Inc., Portland, OR
,
Program Chairs:
Limor Fix
Intel Semiconductors Ltd., Haifa, Israel
,
Luciano Lavagno
Cadence Berkeley Labs., Berkeley, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 June 2003

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DAC03: 2003 40th Annual Design Automation Conference

June 2 - 6, 2003

CA, Anaheim, USA

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DAC '03 Paper Acceptance Rate 152 of 628 submissions, 24%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Zhang TSapatnekar S(2007)Simultaneous shield and buffer insertion for crosstalk noise reduction in global routingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.89864115:6(624-636)Online publication date: 1-Jun-2007
https://dl.acm.org/doi/10.1109/TVLSI.2007.898641
Sinha DZhou HTang T(2005)Yield driven gate sizing for coupling-noise reduction under uncertaintyProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120803(192-197)Online publication date: 18-Jan-2005
https://dl.acm.org/doi/10.1145/1120725.1120803
Gyure AKasnavi ALo STehrani PShu WShahram MWang JZedja J(2005)Noise Library Characterization for Large Capacity Static Noise Analysis ToolsProceedings of the 6th International Symposium on Quality of Electronic Design10.1109/ISQED.2005.85(28-34)Online publication date: 21-Mar-2005
https://dl.acm.org/doi/10.1109/ISQED.2005.85
Sinha DZhou HChu CAlpert, CGroeneveld P(2004)Optimal gate sizing for coupling-noise reductionProceedings of the 2004 international symposium on Physical design10.1145/981066.981104(176-181)Online publication date: 18-Apr-2004
https://dl.acm.org/doi/10.1145/981066.981104
Sinha DZhou H(2004)Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxationProceedings of the 2004 IEEE/ACM International conference on Computer-aided design10.1109/ICCAD.2004.1382535(14-19)Online publication date: 7-Nov-2004
https://dl.acm.org/doi/10.1109/ICCAD.2004.1382535

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Postroute gate sizing for crosstalk noise reduction

Crosstalk noise optimization by post-layout transistor sizing

NBTI tolerance and leakage reduction using gate sizing