Article

Signal integrity management in an SoC physical design flow

Authors:

Murat Becer,

Ravi Vaidyanathan,

Chanhee Oh,

Rajendran PandaAuthors Info & Claims

ISPD '03: Proceedings of the 2003 international symposium on Physical design

Pages 39 - 46

https://doi.org/10.1145/640000.640011

Published: 06 April 2003 Publication History

Get Access

Abstract

Signal integrity closure is one of the key challenges in DSM (Deep- SubMicron) physical design. In this paper, we propose a physical design methodology which includes signal integrity management through noise analysis and repair at multiple phases of the design so that a quick noise convergence can be achieved. The methodology addresses both functional and delay noise problems in the design and is targeted for block, platform, and chip level physical design of SoC (System-On-Chip) designs. A number of case studies are presented to illustrate the effectiveness of the proposed methodology and to provide valuable insights useful for successful signal integrity management.

References

[1]

S. Alwar, D. Blaauw, A. Dasgupta, A. Grinshpon, R. Levy, C. Oh, B. Orshaw, S. Sirichotiyakul, and V. Zolotov, "Clarinet: A Noise Analysis Tool for Deep Submicron Design," in Proceedings of Design Automation Conference DAC, June 2000, pp. 233--238.

Digital Library

Google Scholar

[2]

K. L. Shepard and V. Narayanan, "Noise in Deep submicron Digital Design," in Proceedings of the IEEE International COnference on Computer Aided Design, November 1996, pp. 524--531.

Digital Library

Google Scholar

[3]

S. Sirichotiyakul, D. Blaauw, C. Oh, R. Levy, V. Zolotov, and J. Zuo, "Driver Modeling and Alignment for Worst-case delay noise," in Proceedings of Design Automation Conference DAC, June 2001, pp. 720--725

Digital Library

Google Scholar

[4]

P. D. Gross, R. Arunachalam, K. Rajagopal, and L. T. Pileggi, "Determination of Worst-case Aggressor Alignment for Delay Calculation," in Proceedings of IEEE International Conference on Computer Aided Design, ICCAD-98

Digital Library

Google Scholar

[5]

H. Zhou and D. F. Wong, "Global Routing with Crosstalk Constraints" in Proceedings of Design Automation Conference DAC, June 1998, pp. 374--377

Digital Library

Google Scholar

[6]

P. Saxena and C. L. Liu, "Crosstalk Minimization using Wire Perturbations", in Proceedings of Design Automation Conference DAC, June 1999, pp. 100--103

Digital Library

Google Scholar

[7]

C. P. Chen and N. Menezes, "Noise Aware Repeater Insertion and Wire Sizing for on-chip Interconnect Using Hierarchical Moment Matching", in Proceedings of Design Automation Conference DAC, June 1999, pp. 502--506

Digital Library

Google Scholar

[8]

C. J. Alpert, A. Devgan, and S. T. Quay, "Buffer Insertion for Noise and Delay Optimization", in Proceedings of Design Automation Conference, June 1998, pp. 362--367

Digital Library

Google Scholar

[9]

I. H. R. Jiang, Y. W. Chang, and J. Y. Lou, "Crosstalk Driven Interconnect Optimization by Simultaneous Gate and Wire Sizing", IEEE Transactions on Computer Aided Design, v. 19, pp. 999--1010, September 2000

Digital Library

Google Scholar

[10]

M. Hashimoto, M. Takahashi, and H. Onodera, "Crosstalk Noise Optimization by Post-layout Transistor Sizing", in Proceedings of ISPD, April 2002, pp. 126--130

Digital Library

Google Scholar

[11]

A. Odabasioglu, M. Celik, and L. T. Pileggi, "PRIMA: Passive Reduced-order Interconnect Macromeodeling Algorithm", IEEE Transactions on Computer Aided Design, v. 17, pp. 645--653, August 1998

Digital Library

Google Scholar

[12]

R. Arunachalam, K. Rajagopal, and L. T. Pileggi, "TACO: Timing Analysis with Coupling", In Proceedings of ICCAD, Nov. 1998, pp. 1--8

Digital Library

Google Scholar

[13]

M. Becer, D. Blaauw, R. Panda, and I. N. Hajj, "Early Probabilistic Noise Estimation in Capacitively Coupled Interconnects," in Proceedings SLIP, April 2002, pp. 77--84

Digital Library

Google Scholar

Cited By

View all

Becer MBlaauw DAlgor IPanda ROh CZolotov VHajj I(2006)Postroute gate sizing for crosstalk noise reductionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2004.83673623:12(1670-1677)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2004.836736
Takeuchi KYanagisawa KSato TSakamoto KHojo S(2006)Probabilistic crosstalk delay estimation for ASICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2004.83360523:9(1377-1383)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2004.833605
Saxena PLalgudi KGreub HWang-Roveda JTang T(2005)A perturbation-aware noise convergence methodology for high frequency microprocessorsProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1121002(717-722)Online publication date: 18-Jan-2005
https://dl.acm.org/doi/10.1145/1120725.1121002
Show More Cited By

Index Terms

Signal integrity management in an SoC physical design flow
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design

Recommendations

Postroute gate sizing for crosstalk noise reduction

Gate sizing is a practical and a feasible crosstalk noise correction technique in the post route design stage, especially for block level sea-of-gates designs. The difficulty in gate sizing for noise reduction is that, by increasing a driver size, noise ...
Signal Integrity: Fault Modeling and Testing in High-Speed SoCs

As we approach 100 nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-on-chips. Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately ...
On-chip measurements complementary to design flow for integrity in SoCs
DAC '07: Proceedings of the 44th annual Design Automation Conference

On-chip monitors are used in a dual role of dynamically monitoring the behavior of a die as well as verifying EDA tools for integrity in sub-100-nm CMOS SoC designs. This paper describes on-chip measurement techniques of supply noise, delay variation, ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

ISPD '03: Proceedings of the 2003 international symposium on Physical design

April 2003

218 pages

ISBN:1581136501

DOI:10.1145/640000

General Chair:
Massoud Pedram
USC
,
Program Chair:
Charles J. Alpert
IBM

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 06 April 2003

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

ISPD03

Sponsor:

ISPD03: International Symposium on Physical Design

April 6 - 9, 2003

CA, Monterey, USA

Acceptance Rates

Overall Acceptance Rate 62 of 172 submissions, 36%

Upcoming Conference

ISPD '25

Sponsor:
sigda

International Symposium on Physical Design

March 16 - 19, 2025

Austin , TX , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

5
Total Citations
View Citations
512
Total Downloads

Downloads (Last 12 months)3
Downloads (Last 6 weeks)0

Reflects downloads up to 03 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Becer MBlaauw DAlgor IPanda ROh CZolotov VHajj I(2006)Postroute gate sizing for crosstalk noise reductionIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2004.83673623:12(1670-1677)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2004.836736
Takeuchi KYanagisawa KSato TSakamoto KHojo S(2006)Probabilistic crosstalk delay estimation for ASICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2004.83360523:9(1377-1383)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2004.833605
Saxena PLalgudi KGreub HWang-Roveda JTang T(2005)A perturbation-aware noise convergence methodology for high frequency microprocessorsProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1121002(717-722)Online publication date: 18-Jan-2005
https://dl.acm.org/doi/10.1145/1120725.1121002
Saxena PLalgudi KGreub HWang-Roveda J(2005)A perturbation-aware noise convergence methodology for high frequency microprocessorsProceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.10.1109/ASPDAC.2005.1466441(717-722)Online publication date: 2005
https://doi.org/10.1109/ASPDAC.2005.1466441
Renault PBazargan-Sabet P(2004)Splitting of RC-network for accurate model reductionProceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.10.1109/ICM.2004.1434771(734-737)Online publication date: 2004
https://doi.org/10.1109/ICM.2004.1434771

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Postroute gate sizing for crosstalk noise reduction

Signal Integrity: Fault Modeling and Testing in High-Speed SoCs

On-chip measurements complementary to design flow for integrity in SoCs