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ED&TC 1995: Paris, France
- 1995 European Design and Test Conference, ED&TC 1995, Paris, France, March 6-9, 1995. IEEE Computer Society 1995, ISBN 0-8186-7039-8
Session 1A: DSP and Multimedia
- Mario Kovac, N. Ranganathan, Martin Zagar:
A prototype VLSI chip architecture for JPEG image compression. 2-6 - J.-M. Bourguet, T. Nancy, Shao-Jun Wei, Jacques Leroy, Raymond Crappe:
A variant of Cooley-Tuckey algorithm with local memory management. 7-11 - Günter Knittel, Andreas Schilling
:
Eliminating the Z-Buffer bottleneck. 12-17
Session 1B: Mixed-Signal DFT
- F. C. M. Kuijstermans, Manoj Sachdev, A. P. Thijssen:
Defect-oriented test methodology for complex mixed-signal circuits. 18-23 - A. H. Bratt, Andrew Mark David Richardson
A design-for-test structure for optimising analogue and mixed signal IC test. 24-33 - Marcelo Lubaszewski, Vladimir Kolarik, Salvador Mir, C. Nielsen, Bernard Courtois:
Mixed-signal circuits and boards for high safety applications. 34-41
Session 1C: Exact Methods in Architectural Timing Optimization
- Adwin H. Timmer, Jochen A. G. Jess:
Exact scheduling strategies based on bipartite graph matching. 42-47 - Ivan P. Radivojevic, Forrest Brewer
On applicability of symbolic techniques to larger scheduling problems. 48-53 - Nelson L. Passos, Edwin Hsing-Mean Sha, Liang-Fang Chao:
Optimizing synchronous systems for multi-dimensional applications. 54-59
Session 2A: Circuit Partitioning
- Dennis J.-H. Huang, Andrew B. Kahng:
When clusters meet partitions: new density-based methods for circuit decomposition. 60-64 - Honghua Yang, D. F. Wong
Circuit clustering for delay minimization under area and pin constraints. 65-70 - Bernhard M. Riess, A. A. Schoene:
Architecture driven k-way partitioning for multichip modules. 71-79
Session 2C: Combinational Logic Synthesis
- Alessandro Bogliolo, Maurizio Damiani:
Synthesis of multilevel fault-tolerant combinational circuits. 80-85 - B. Kapoor:
Improved technology mapping using a new approach to Boolean matching. 86-90 - Rolf Drechsler
Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions. 91-99
Session 3A: Designs and Tools for Analogue and Mixed Signal ICs
- Nianxiong Tan, Sven Eriksson:
Low-voltage low-power switched-current circuits and systems. 100-104 - Anton Pletersek, Drago Strle, Janez Trontelj:
Low supply voltage, low noise fully differential programmable gain amplifiers. 105-112 - Kambiz Hayat-Dawoodi, Oluf Alminde, Vinko Kunc, Manfred Pauritsch:
A universal telephone audio circuit with loudhearing and handsfree operation in CMOS technology. 113-118 - Petar Veselinovic, Domine Leenaerts, W. van Bokhoven, Francky Leyn, F. Proesmans, Georges G. E. Gielen
A flexible topology selection program as part of an analog synthesis system. 119-125
Session 3B: Memory Testing
- Mark G. Karpovsky, Ad J. van de Goor, V. N. Yarmolik:
Pseudo-exhaustive word-oriented DRAM testing. 126-132 - Ad J. van de Goor, Ivo Schanstra, Yervant Zorian:
Functional test for shifting-type FIFOs. 133-138 - R. Dean Adams, John Connor, Garret S. Koch, Luigi Ternullo Jr.:
A 370-MHz memory built-in self-test state machine. 139-143
Session 3C: Sequential Logic Synthesis
- Bill Lin, Gjalt G. de Jong, Tilman Kolks:
Modeling and optimization of hierarchical synchronous circuits. 144-149 - Leon Stok, Ilan Y. Spillinger, Guy Even:
Improving initialization through reversed retiming. 150-154 - Zafar Hasan, Maciej J. Ciesielski:
Elimination of multi-cycle false paths by state encoding. 155-161
Session 4A: High Speed Telecom Design
- Pierre Plaza, Juan Carlos Diaz, Fermín Calvo, Luis A. Merayo, Maurizio Zamboni, Pietro Scarfone, Marco Barbini:
Input and output processor for an ATM high speed switch (2.5 Gb/s): the CMC. 162-166 - Akira Onozawa, Hitoshi Kitazawa, Kenji Kawai:
Post-layout optimization of power and timing for ECL LSIs. 167-172 - Mario Diaz-Nava, Didier Belot, P. Delerue, Joseph Bulone:
A 622/155 mbps ATM line terminator mono-chip. 173-179
Session 4B: System Synthesis
- Carlos A. Valderrama, Adel Changuel, P. V. Raghavan, Mohamed Abid, Tarek Ben Ismail, Ahmed Amine Jerraya:
A unified model for co-simulation and co-synthesis of mixed hardware/software systems. 180-184 - Frank Vahid, Daniel D. Gajski:
SLIF: a specification-level intermediate format for system design. 185-189 - Peter Altenbernd:
Deadline-monotonic software scheduling for the co-synthesis of parallel hard real-time systems. 190-197
Session 4C: Advanced DFT Techniques
- Marie-Lise Flottes, D. Hammad, Bruno Rouzeyre:
High-level synthesis for easy testability. 198-206 - Franco Fummi, Donatella Sciuto, Micaela Serra:
Sequential logic minimization based on functional testability. 207-211 - Li-Ren Huang, Sy-Yen Kuo, Ing-Yi Chen:
A Gauss-elimination based PRPG for combinational circuits. 212-217
Session 5A: Digital and System Simulation
- Francis Pichon, Stéphane Blanc, Bernard Candaele:
Mixed-signal modelling in VHDL for system-on-chip applications. 218-222 - J. W. G. Fleurkens, C. A. J. van Eijk, Jochen A. G. Jess:
Run-time consistency checking in discrete simulation models. 223-227 - Ing-Yi Chen, Geng-Lin Chen, Sy-Yen Kuo:
Delay models for the sea-of-wires array synthesis system. 228-233
Session 5B: Code Generation
- Augusli Kifli, G. Goosens, Hugo De Man:
A unified scheduling model for high-level synthesis and code generation. 234-238 - Rainer Leupers, Peter Marwedel:
A BDD-based frontend for retargetable compilers. 239-243 - Marino T. J. Strik, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess, Stefaan Note:
Efficient code generation for in-house DSP-cores. 244-251
Session 5C: Sequential ATPG and Diagnosis
- Thomas E. Marchok, Aiman El-Maleh
Complexity of sequential ATPG. 252-261 - Jaehong Park, Chanhee Oh, M. Ray Mercer:
Improved sequential ATPG using functional observation information and new justification methods. 262-266 - Fulvio Corno
GARDA: a diagnostic ATPG for large synchronous sequential circuits. 267-273
Session 6A: CAD Frameworks
- Yves Mathys, Marc Morgan, Salma Soudagar:
Controlling change propagation and project policies in IC design. 274-279 - Ewa Kwee-Christoph, Fridtjof Feldbusch, Ramayya Kumar, Arno Kunzmann:
Generic design flows for project management in a framework environment. 280-284 - Arno Kunzmann, Ralf Seepold
Enhanced functionality by coupling the JESSI-COMMON-Framework with an ECAD framework. 285-293
Session 6C: Test Generation and Testability
- Li-C. Wang, M. Ray Mercer, Thomas W. Williams:
Enhanced testing performance via unbiased test sets. 294-302 - M. H. C. Lee, Dali L. Tao:
A testability measure for hierarchical design environments. 303-307 - G. Van Brakel, Uwe Gläser, Hans G. Kerkhoff, Heinrich Theodor Vierhaus:
Gate delay fault test generation for non-scan circuits. 308-313
Session 7A: Applications of Symbolic Traversal Techniques
- Jürgen Frößl, Thomas Kropf:
Verifying real-time properties of MOS-transistor circuits. 314-319 - Fulvio Corno
Using symbolic techniques to find the maximum clique in very large sparse graphs. 320-324 - Alex Kondratyev, Jordi Cortadella
Checking signal transition graph implementability by symbolic BDD traversal. 325-332 - Fulvio Corno, Marco Cusinato, Mario Ferrero, Paolo Prinetto:
Proving testing preorders for process algebra descriptions. 333-339
Session 7B: Handling Physical Constraints in Architectural Synthesis
- Nancy D. Holmes, Daniel D. Gajski:
Architectural exploration for datapaths with memory hierarchy. 340-344 - Pradip K. Jha, Nikil D. Dutt
Design reuse through high-level library mapping. 345-350 - Alessandro Balboni, Claudio Costi, A. Pellencin, M. Quadrini, Donatella Sciuto:
Automatic clock tree generation in ASIC designs. 351-357
Session 7C: Self-Checking Approaches
- O. Kebichi, Yervant Zorian, Michael Nicolaidis:
Area versus detection latency trade-offs in self-checking memory design. 358-362 - Jamel M. Tahir, Satnam Singh Dlay, Raouf N. Gorgui-Naguib, Oliver R. Hinton:
Self-checking architectures for fast Hartley transform. 363-371 - Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu:
Built-in intermediate voltage testing for CMOS circuits. 372-377
Session 8A: Design Methodologies
- E. Kofi Vida-Torku, Charles H. Malley, Sung Park, R. Reed:
Design and test of the PowerPC 603 microprocessor. 378-384 - Maurizio Valle, Giovanni Nateri, Daniele D. Caviglia, Giacomo M. Bisio, Luciano Briozzo:
An ASIC design for real-time image processing in industrial applications. 385-390 - David L. Andrews
Rapid prototype of a hardware emulator for a SIMD processor array. 391-397
Session 8B: Power and Delay Issues in Logic Synthesis
- Jeroen A. J. Leijten, Jef L. van Meerbergen, Jochen A. G. Jess:
Analysis and reduction of glitches in synchronous networks. 398-403 - Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Decomposition of logic functions for minimum transition activity. 404-410 - Horng-Fei Jyu, Sharad Malik
Prediction of interconnect delay in logic synthesis. 411-417
Session 8C: BIST Methodologies
- Bernd Wurth, Karl Fuchs:
A BIST approach to delay fault testing with reduced test length. 418-423 - Christian Dufaza, H. Viallon, Cyril Chevalier:
BIST hardware generator for mixed test scheme. 424-430 - Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantin Halatsis:
Accumulator-based BIST approach for stuck-open and delay fault testing. 431-437
Session 9A: New Developments in Logic Representation and Verification Techniques
- Bernd Becker, Rolf Drechsler:
How many decomposition types do we need? [decision diagrams]. 438-443 - Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita:
VERIFUL: VERIfication using FUnctional Learning. 444-448 - S. Minato:
Implicit manipulation of polynomials using zero-suppressed BDDs. 449-457
Session 9C: Test Preparation for Mixed-Signal Systems
- Bechir Ayari, Naim Ben-Hamida, Bozena Kaminska:
Automatic test vector generation for mixed-signal circuits. 458-463 - Christian Sebeke, J. P. Teixeira, Michael J. Ohletz:
Automatic fault extraction and simulation of layout realistic faults for integrated analogue circuits. 464-468 - Pascal Caunegre, Claude Abraham:
Achieving simulation-based test program verification and fault simulation capabilities for mixed-signal systems. 469-479
Session 10A: Hierarchical Layout
- Bernd Schürmann, Joachim Altmeyer:
The effect of pin constraints on layout area. 480-485 - H. Schmidt, Dirk Theune, Ralf Thiele, Thomas Lengauer:
EMC-driven midway routing on PCBs. 486-491 - Masayuki Hayashi, Shuji Tsukiyama:
A hybrid hierarchical approach for multi-layer global routing. 492-497
Session 10B: Modeling and Design of ASIPs
- Jie Gong, Daniel D. Gajski, Sanjiv Narayan:
Software estimation using a generic-processor model. 498-502 - Andreas Fauth, Johan Van Praet, Markus Freericks:
Describing instruction set processors using nML. 503-507 - Frederick Onion, Alexandru Nicolau, Nikil D. Dutt
Incorporating compiler feedback into the design of ASIPs. 508-515
Session 10C: Delay Testing and Diagnosis
- B. Kapoor:
An efficient method for computing exact path delay fault coverage. 516-520 - Manfred Henftling, Hannes Wittman:
Bit parallel test pattern generation for path delay faults. 521-525 - Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez:
A trace-based method for delay fault diagnosis in synchronous sequential circuits. 526-533
Session 11A: New Applications of Analogue Simulation Algorithms
- Luís Miguel Silveira, Mattan Kamon, Jacob K. White:
Efficient reduced-order modeling of frequency-dependent coupling inductances associated with 3-D interconnect structures. 534-538 - E. Driouk, O. Jarov, A. Sukhodolsky:
On software development to support statistical simulation of analogue circuits. 539-543 - Vladimir A. Koval, Dmytro V. Fedasyuk
Multilevel thermal simulation of MCM's by system 'MONSTR-M'. 544-549
Session 11B: Design Problems in Pipelines
- Ulrich Holtmann, Rolf Ernst:
Combining MBP-speculative computation and loop pipelining in high-level synthesis. 550-556 - Maher Rahmouni, Ahmed Amine Jerraya:
PPS: a pipeline path-based scheduler. 557-561 - Albert E. Casavant:
Balancing structural hazards and hardware cost of pipelined processors. 562-567
Session 11C: IDDQ Testing
- Marcello Dalpasso
Correlation between IDDQ testing quality and sensor accuracy. 568-572 - Hans-Joachim Wunderlich, M. Herzog, Joan Figueras, Juan A. Carrasco, Angel Calderón:
Synthesis of IDDQ-testable circuits: integrating built-in current sensors. 573-580 - Antonio Rubio, Edmond Janssens, H. Casier, Joan Figueras, Diego Mateo
A built-in quiescent current monitor for CMOS VLSI circuits. 581-587
Poster Session
- Ian Montandon, David Burrows, Kenneth J. Hunt:
High speed communications links for ASICs. 588 - Jesus Crespo, F. Calvo, Juan I. Solana, Rafael Caravantes, J. L. Conesa:
TRJM: a high speed programmable ATM-SDH mapper. 589 - George-Peter K. Economou, John Ant. Hallas, Evaggelinos P. Mariatos, Constantinos E. Goutis:
Artificial neural networks in medical decision making systems: an application to pulmonary diseases' diagnosis through VHDL synthesis. 590 - D. A. Bensouiah, R. J. Mack, R. E. Massara:
Integration of an expert system for analogue layout synthesis into a commercial CAD framework. 591 - Bernd Becker
Synthesis for testability: circuits derived from ordered Kronecker functional decision diagrams. 592 - Raphaël Rochet, Régis Leveugle, Gabriele Saucier:
Efficient synthesis of fault-tolerant controllers. 593 - Henry Selvaraj, Tadeusz Luba:
A balanced multilevel decomposition method. 594 - Hisanori Fujisawa, Fumiyo Kawafuji, Tomoyasu Kitaura, Tetsuro Kage:
A precise event-driven circuit simulator based on predicted fan-in voltages. 595 - Arjan J. van Genderen:
Network initialization in a switch-level simulator. 596-597 - Witold A. Pleskacz, Wieslaw Kuzmicz:
SENSAT-a practical tool for estimation of the IC layout sensitivity to spot defects. 598 - Michele Favalli, Bruno Riccò, L. Penza:
A novel DFT technique for critical bridging faults in CMOS and BiCMOS ICs. 599 - Joan Carletta, Christos A. Papachristou
A method for testability analysis and BIST insertion at the RTL. 600 - Vladimír Székely, Márta Rencz:
Thermal test and monitoring [microelectronic structures]. 601 - A. Romankevich, V. Groll:
On testability of checkable digital circuits under pseudorandom signals. 602 - R. Kh. Latypov, Ye. L. Stolov:
Imperfect linear duplication of combinational circuits. 603 - Marcelino B. Santos, M. Simões, Isabel C. Teixeira, João Paulo Teixeira:
Test preparation methodology for high coverage of physical defects in CMOS digital ICs. 604 - J. Soares Augusto
Fully automatic DC fault dictionary construction and test nodes selection for analogue fault diagnosis. 605 - Dominique Dallet, Giovanni Franco, Philippe Marchegay, Carlo Morandi:
A comparative study of algorithms for A/D converter performance evaluation by statistical analysis. 606 - V. Y. Zagursky, N. Y. Semyonova, M. Sirovatkina:
A histogram method for analog-digital converters testing in time and spectral domain. 607
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