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Noel Menezes
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2010 – 2019
- 2019
- [c20]Noel Menezes:
Session details: Keynote. ISPD 2019
2000 – 2009
- 2008
- [c19]Noel Menezes, Chandramouli V. Kashyap, Chirayu S. Amin:
A "true" electrical cell model for timing, noise, and power grid verification. DAC 2008: 462-467 - 2007
- [j6]Farid N. Najm, Noel Menezes, Imad A. Ferzli:
A Yield Model for Integrated Circuits and its Application to Statistical Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3): 574-591 (2007) - [c18]Steven M. Burns, Mahesh Ketkar, Noel Menezes, Keith A. Bowman, James W. Tschanz, Vivek De:
Comparative Analysis of Conventional and Statistical Design Techniques. DAC 2007: 238-243 - [c17]Chandramouli V. Kashyap, Chirayu S. Amin, Noel Menezes, Eli Chiprout:
A nonlinear cell macromodel for digital applications. ICCAD 2007: 678-685 - [c16]Noel Menezes:
The good, the bad, and the statistical. ISPD 2007: 168 - 2006
- [c15]Chirayu S. Amin, Chandramouli V. Kashyap, Noel Menezes, Kip Killpack, Eli Chiprout:
A multi-port current source model for multiple-input switching effects in CMOS library cells. DAC 2006: 247-252 - 2005
- [c14]Chirayu S. Amin, Noel Menezes, Kip Killpack, Florentin Dartu, Umakanta Choudhury, Nagib Hakim, Yehea I. Ismail:
Statistical static timing analysis: how simple can we get? DAC 2005: 652-657 - [c13]Florentin Dartu, Anirudh Devgan, Noel Menezes:
Variability modeling and variability-aware design in deep submicron integrated circuits. ACM Great Lakes Symposium on VLSI 2005: 1 - 2004
- [j5]Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick:
Repeater scaling and its impact on CAD. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4): 451-463 (2004) - [c12]Farid N. Najm, Noel Menezes:
Statistical timing analysis based on a timing yield model. DAC 2004: 460-465 - 2003
- [c11]Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick:
The scaling challenge: can correct-by-construction design help? ISPD 2003: 51-58 - 2001
- [c10]Noel Menezes, Sachin S. Sapatnekar:
Optimization and Analysis Techniques for the Deep Submicron Regime. VLSI Design 2001: 3-4
1990 – 1999
- 1999
- [c9]Chung-Ping Chen, Noel Menezes:
Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching. DAC 1999: 502-506 - [c8]Noel Menezes, Chung-Ping Chen:
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect. VLSI Design 1999: 476- - 1997
- [j4]Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi:
Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(2): 210-215 (1997) - [j3]Noel Menezes, Ross Baldick, Lawrence T. Pileggi:
A sequential quadratic programming approach to concurrent gate and wire sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(8): 867-881 (1997) - [c7]Ashih D. Mehta, Yao-Ping Chen, Noel Menezes, D. F. Wong
, Lawrence T. Pileggi:
Clustering and Load Balancing for Buffered Clock Tree Synthesis. ICCD 1997: 217-223 - 1996
- [j2]Florentin Dartu, Noel Menezes, Lawrence T. Pileggi:
Performance computation for precharacterized CMOS gates with RC loads. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(5): 544-553 (1996) - [j1]Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi:
Post-processing of clock trees via wiresizing and buffering for robust design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(6): 691-701 (1996) - 1995
- [c6]Noel Menezes, Satyamurthy Pullela, Lawrence T. Pileggi:
Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization. DAC 1995: 690-695 - [c5]Noel Menezes, Ross Baldick, Lawrence T. Pileggi:
A sequential quadratic programming approach to concurrent gate and wire sizing. ICCAD 1995: 144-151 - 1994
- [c4]Florentin Dartu, Noel Menezes, Jessica Qian, Lawrence T. Pillage:
A Gate-Delay Model for high-Speed CMOS Circuits. DAC 1994: 576-580 - [c3]Ronn B. Brashear, Noel Menezes, Chanhee Oh, Lawrence T. Pillage, M. Ray Mercer:
Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis. EDAC-ETC-EUROASIC 1994: 332-337 - [c2]Noel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage:
RC interconnect synthesis-a moment fitting approach. ICCAD 1994: 418-425 - 1993
- [c1]Satyamurthy Pullela, Noel Menezes, Lawrence T. Pillage:
Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization. DAC 1993: 165-170
Coauthor Index
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