[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ skip to main content
10.5555/1129601.1129736acmconferencesArticle/Chapter ViewAbstractPublication PagesiccadConference Proceedingsconference-collections
Article

Pessimism reduction in crosstalk noise aware STA

Published: 31 May 2005 Publication History

Abstract

High performance circuits are facing increasingly severe signal integrity problems due to crosstalk noise and crosstalk noise awareness has become an integral part of static timing analysis (STA). Existing crosstalk noise aware STA methods compute noise induced delay uncertainty on a net by net basis and in a pessimistic way, without considering the overlap bounds of the victim and aggressor timing windows and realistic delay impact on early and late signal arrival times. Since crosstalk induced delay on individual nets contribute cumulatively on data and clock paths, even small amounts of pessimism in computation can add up to produce several unrealistic timing violations. Unlike glitch noise analysis where noise often attenuates during propagation, quality of delay noise analysis is severely affected by any pessimism in noise estimation and can unnecessarily cost valuable silicon and design resources for fixing unreal violations. In this paper, we propose two temporal techniques to reduce pessimism in crosstalk noise aware STA. The first method, "effective delay noise", is a net based method where the exact overlap points of victim and aggressor timing windows are considered to obtain the part of delay noise that actually impacts early and late signal arrival times. The second method, "path based delay noise", is a path based method where the reduced arrival uncertainty of the nets of a given path are utilized for pessimism reduction. We also propose a novel "uncertainty propagation" technique as part of the second method, which results in an iteration free crosstalk noise aware STA of the path with significantly reduced pessimism. The two techniques are combined in a proposed methodology that is compatible with existing industrial static timing analyzers with very little computational overhead compared to the traditional noise aware STA and a significant improvement in eliminating unreal violations. The proposed techniques resulted in 77% reduction of worst case negative slack and 57% reduction in the number of failing paths in the setup analysis of a 90nm industrial design.

References

[1]
{1} A. Glebov, S. Gavrilov, D. Blaauw, V. Zolotov, R. Panda, and C. Oh False-noise analysis usng resolution method. In Proceedings of ISQED- 02, pages 437-442, March 2002.
[2]
{2} D. Chai, A. Kondratyev, Y. Ran, K. H. Tseng, Y. Watanabe, and M. M. Sadowska. Temporofunctional crosstalk noise analysis. In Proceedings of DAC-03 Design Automation Conference, pages 860-863, June 2003.
[3]
{3} A. Glebov, S. Gavrilov, R. Soloviev, V. Zolotov, M. Becer, C. Oh, and R. Panda Delay noise pessimism reduction by logic correlations In Proceedings of ICCAD-04 Intl. Conference on Computer Aided Design, pages 160-167, November 2004.
[4]
{4} R. Levy, D. Blaauw, G. Braca, A. Dasgupta, A. Grinshpon, C. Oh, B. Orshav, S. Sirichotiyakul, and V. Zolotov ClariNet: A noise analysis tool for deep submicron design In Proceedings of DAC-00 Design Automation Conference, pages 233-238, June 2000.
[5]
{5} P. Chen and K. Keutzer. Towards true crosstalk noise analysis. In Proceedings of ICCAD-99 Intl. Conference on Computer Aided Design, pages 132-137, November 1999.
[6]
{6} P. Chen, Y. Kukimoto, and K. Keutzer. Refining switching window by time slots for crosstalk noise calculation. In Proceedings of ICCAD-02 Intl. Conference on Computer Aided Design, pages 583-586, November 2002.
[7]
{7} R. Arunachalam, K. Rajagopal, and L. T. Pileggi. Taco: Timing analysis with coupling. In Proceedings of the IEEE International Conference on Computer-Aided Design, ICCAD-98, pages 1-8, 1998.
[8]
{8} H. Zhou, N. Shenoy, and W. Nicholls. Timing analysis with crosstalk as fixpoints on complete lattice. In Proceedings of Design Automation Conference DAC, pages 714-719, June 2001.
[9]
{9} B. Thudi, and D. Blaauw. Non-iterative switching window computation for delay noise. In Proceedings of DAC-03 Design Automation Conference , pages 390-395, June 2003.
[10]
{10} P. Chen, and K. Keutzer. Miller factor for gate level coupling delay calculation. In Proceedings of the IEEE International Conference on Computer-Aided Design, ICCAD-00, pages 68-74, 2000.
[11]
{11} L. H. Chen, and M. Marek-Sadowska. Aggressor Alignment for worst-case crosstalk noise. In IEEE Transactions on Computer-Aided Design, Vol. 20, pages 612-621, May 2001.
[12]
{12} S. S. Sapatnekar. A timing model incorporating the effect of crosstalk on delay and its application to optimal channel routing. In IEEE Transactions on Computer-Aided Design, Vol. 19, pages 550-559, May 2000.
[13]
{13} A. B. Kahng, S. Muddu, and E. Sarto. On switch factor based analysis of coupled RC interconnects. In Proceedings of DAC-00 Design Automation Conference, pages 79-84, June 2000.
[14]
{14} P. Chen, Y. Kokimoto, C. Teng, and K. Keutzer. On the convergence of switching window computation in presence of noise. In Proceedings of International Symopsium on Physical Design ISPD-02, pages 84-89, 2002.
[15]
{15} S. S. Sapatnekar. On the chicken-and-egg problem of crossalk on delay in integrated circuits. In Proceedings of IEEE 8th Topical Meeting on Electrical Performance of Electronic Package, pages 245-248, 1999
[16]
{16} P. Chen, D. A. Kirkpatrick, and K. Kuetzer. Switching window computation for static timing analysis in presence of crosstalk noise. In Proceedings of the IEEE International Conference on Computer-Aided Design, ICCAD-00, pages 331-337, 2000.
[17]
{17} T. Xiao, et.al. Efficient static timing analysis in presence of crosstalk. In Proceedings of IEEE International ASIC/SOC Conference, pages 335- 339, 2000
[18]
{18} K. L. Shepard, et.al. Global Harmony: Coupled noise analysis for full-chip RC interconnect networks. In Proceedings of the IEEE International Conference on Computer-Aided Design, ICCAD-97, pages 139-146, 1997.
[19]
{19} P. D. Gross, et.al. Determination of worst-case aggressor alignment for delay calculation. In Proceedings of the IEEE International Conference on Computer-Aided Design, ICCAD-98, pages 212-219, 1998.
[20]
{20} T. Xiao, and M. Marek-Sadowska. Worst delay estimation in crosstalk aware static timing analysis. In Proceedings of IEEE ICCD, pages 115- 120, 2000
[21]
{21} J. M. Wang, O. Hafiz, and P. Chen A non-iterative model for switching window computation with crosstalk noise. In Proceedings of ASP-DAC, pages 846-851, 2004

Cited By

View all
  • (2017)Coupling-Aware Functional Timing Analysis for Tighter BoundsProceedings of the Great Lakes Symposium on VLSI 201710.1145/3060403.3060443(251-256)Online publication date: 10-May-2017
  • (2010)Crosstalk-induced delay, noise, and interconnect planarization implications of fill metal in nanoscale process technologyIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.201083018:3(378-391)Online publication date: 1-Mar-2010
  • (2010)Victim alignment in crosstalk-aware timing analysisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.203548429:2(261-274)Online publication date: 1-Feb-2010
  • Show More Cited By
  1. Pessimism reduction in crosstalk noise aware STA

    Recommendations

    Comments

    Please enable JavaScript to view thecomments powered by Disqus.

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    ICCAD '05: Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
    May 2005
    1032 pages
    ISBN:078039254X

    Sponsors

    Publisher

    IEEE Computer Society

    United States

    Publication History

    Published: 31 May 2005

    Check for updates

    Qualifiers

    • Article

    Acceptance Rates

    Overall Acceptance Rate 457 of 1,762 submissions, 26%

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)2
    • Downloads (Last 6 weeks)0
    Reflects downloads up to 02 Dec 2024

    Other Metrics

    Citations

    Cited By

    View all
    • (2017)Coupling-Aware Functional Timing Analysis for Tighter BoundsProceedings of the Great Lakes Symposium on VLSI 201710.1145/3060403.3060443(251-256)Online publication date: 10-May-2017
    • (2010)Crosstalk-induced delay, noise, and interconnect planarization implications of fill metal in nanoscale process technologyIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.201083018:3(378-391)Online publication date: 1-Mar-2010
    • (2010)Victim alignment in crosstalk-aware timing analysisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.203548429:2(261-274)Online publication date: 1-Feb-2010
    • (2009)Timing Arc Based Logic Analysis for false noise reductionProceedings of the 2009 International Conference on Computer-Aided Design10.1145/1687399.1687440(225-230)Online publication date: 2-Nov-2009
    • (2008)Incorporating logic exclusivity (LE) constraints in noise analysis using gain guided backtracking methodProceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design10.5555/1509456.1509626(783-789)Online publication date: 10-Nov-2008
    • (2007)Victim alignment in crosstalk aware timing analysisProceedings of the 2007 IEEE/ACM international conference on Computer-aided design10.5555/1326073.1326220(698-704)Online publication date: 5-Nov-2007
    • (2006)Generation of design guarantees for interconnect matchingProceedings of the 2006 international workshop on System-level interconnect prediction10.1145/1117278.1117285(29-34)Online publication date: 4-Mar-2006

    View Options

    Login options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Media

    Figures

    Other

    Tables

    Share

    Share

    Share this Publication link

    Share on social media