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Martin Gall
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2020 – today
- 2024
- [c11]P. Srinivasan, Oscar H. Gonzalez, Oscar D. Restrepo, J. Lestage, Shafi Syed, W. Taylor, Anirban Bandyopadhyay, Martin Gall, S. Ludvik:
Thermal Considerations on RF Reliability and Aging in SOI CMOS Based Power Amplifiers. IRPS 2024: 1-6 - [c10]Valeriy Sukharev, Jun-Ho Choy, Armen Kteyan, J. Shuster-Passage, Seungman Choi, Martin Gall:
A Unified Physics-Based Stochastic Model for EM-Induced Resistance Degradation in BEoL Interconnect Segments. IRPS 2024: 1-10 - [c9]J. Shuster-Passage, S. Abdel Razek, M. Mattoo, Meike Hauschildt, Seungman Choi, Martin Gall, Armen Kteyan, Jun-Ho Choy, Valeriy Sukharev, Matthias Kraatz, J. R. Lloyd:
A Novel Method for the Determination of Electromigration-Induced Void Nucleation Stresses. IRPS 2024: 10 - 2023
- [c8]P. Srinivasan, J. Lestage, Shafi Syed, X. Hui, Stephen Moss, Oscar D. Restrepo, Oscar H. Gonzalez, Y. Chen, T. McKay, Anirban Bandyopadhyay, Ned Cahoon, Fernando Guarin, Byoung Min, Martin Gall, S. Ludvik:
RF long term aging behavior and reliability in 22FDX WiFi Power Amplifier designs for 5G applications. IRPS 2023: 1-6 - [c7]Zhuo-Jie Wu, Ping-Chuan Wang, Seungman Choi, Patrick Justison, Martin Gall, Jae Kyu Cho, Takako Hirokawa, Yusheng Bian, Thomas Houghton, Vaishnavi Karra, Dan Moy, Karen Nummy, Dave Riggs, Norman Robson, Ian Melville, Ken Giewont:
Self-aligned Fiber Attach on Monolithic Silicon Photonic Chips: Moisture Effect and Hermetic Seal. OFC 2023: 1-3 - 2021
- [c6]P. Srinivasan, Fernando Guarin, Shafi Syed, Joris Angelo Sundaram Jerome, Wen Liu, Sameer H. Jain, Dimitri Lederer, Stephen Moss, Paul Colestock, Anirban Bandyopadhyay, Ned Cahoon, Byoung Min, Martin Gall:
RF Reliability of SOI-based Power Amplifier FETs for mmWave 5G Applications. IRPS 2021: 1-6 - [c5]Zhenjun Zhang, Matthias Kraatz, Meike Hauschildt, Seungman Choi, André Clausner, Ehrenfried Zschech, Martin Gall:
Strategy to Characterize Electromigration Short Length Effects in Cu/low-k Interconnects. IRPS 2021: 1-5
2010 – 2019
- 2018
- [c4]Jens Warmuth, Kay-Uwe Giering, André Lange, André Clausner, Simon Schlipf, Gottfried Kurz, Michael Otto, Jens Paul, Roland Jancke, Andreas Aal, Martin Gall, Ehrenfried Zschech:
Prediction of SRAM Reliability Under Mechanical Stress Induced by Harsh En§ironments. ESSDERC 2018: 178-181 - [c3]Matthias Kraatz, Christoph Sander, André Clausner, Meike Hauschildt, Yvonne Standke, Martin Gall, Ehrenfried Zschech:
Analysis of electromigration-induced backflow stresses in Cu(Mn) interconnects using high statistical sampling. IRPS 2018: 4 - [c2]André Clausner, Simon Schlipf, Gottfried Kurz, Michael Otto, Jens Paul, Kay-Uwe Giering, Jens Warmuth, André Lange, Roland Jancke, Andreas Aal, Rüdiger Rosenkranz, Martin Gall, Ehrenfried Zschech:
Analysis of 28 nm SRAM cell stability under mechanical load applied by nanoindentation. IRPS 2018: 5 - 2014
- [j4]Oliver Aubel, Armand Beyer, Georg Talut, Martin Gall:
Empirical BEOL-TDDB evaluation based on I(t)-trace analysis. Microelectron. Reliab. 54(9-10): 1671-1674 (2014) - [j3]Christoph Sander, Yvonne Standke, Sven Niese, Rüdiger Rosenkranz, André Clausner, Martin Gall, Ehrenfried Zschech:
Advanced methods for mechanical and structural characterization of nanoscale materials for 3D IC integration. Microelectron. Reliab. 54(9-10): 1959-1962 (2014)
2000 – 2009
- 2006
- [j2]Haldun Haznedar, Martin Gall, Vladimir Zolotov, Pon Sung Ku, Chanhee Oh, Rajendran Panda:
Impact of stress-induced backflow on full-chip electromigration risk assessment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1038-1046 (2006) - 2004
- [c1]Chanhee Oh, Haldun Haznedar, Martin Gall, Amir Grinshpon, Vladimir Zolotov, Pon Sung Ku, Rajendran Panda:
A Methodology for Chip-Level Electromigration Risk Assessment and Product Qualification. ISQED 2004: 232-237
1990 – 1999
- 1998
- [j1]Toshiaki Kirihata, Martin Gall, Kohji Hosokawa, Jean-Marc Dortu, Hing Wong, Peter Pfefferl, Brian L. Ji, Oliver Weinfurtner, John K. DeBrosse, Hartmud Terletzki, Manfred Selz, Wayne Ellis, Matthew R. Wordeman, Oliver Kiehl:
A 220-mm2, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture. IEEE J. Solid State Circuits 33(11): 1711-1719 (1998)
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last updated on 2024-11-06 21:32 CET by the dblp team
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