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Noise propagation and failure criteria for VLSI designs

Published: 10 November 2002 Publication History

Abstract

Noise analysis has become a critical concern in advanced chip designs. Traditional methods suffer from two common issues. First, noise that is propagated through the driver of a net is combined with noise injected by capacitively coupled aggressor nets using linear summation. Since this ignores the non-linear behavior of the driver gate the noise that develops on a net can be significantly underestimated. We therefore propose a new linear model that accurately combines propagated and injected noise on a net and which maintains the efficiency of linear simulation. After the propagated and injected noise are correctly combined on a victim net, it is necessary to determine if the noise can result in a functional failure. This is the second issue that we discuss in this paper. Traditionally, noise failure criteria have been based on unity gain points of the DC or AC transfer curves. However, we will show that for digital designs, these approaches can result in a pessimistic analysis in some cases, while in other cases, they allow circuit operation that is extremely close to regions that are unstable and do not allow sufficient margin for error in the analysis. In this paper, we compare the effectiveness of the discussed noise failure criteria and also present a propagation based method, which is intended to overcome these drawbacks. The proposed methods were implemented in a noise analysis tool and we demonstrate results on industrial circuits.

References

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  • (2009)Probabilistic analysis and design of metallic-carbon-nanotube-tolerant digital logic circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.202319728:9(1307-1320)Online publication date: 1-Sep-2009
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cover image ACM Conferences
ICCAD '02: Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
November 2002
793 pages
ISBN:0780376072
DOI:10.1145/774572
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 10 November 2002

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Cited By

View all
  • (2010)Carbon nanotube correlationProceedings of the 47th Design Automation Conference10.1145/1837274.1837497(889-892)Online publication date: 13-Jun-2010
  • (2010)Built-in sensor for signal integrity faults in digital interconnect signalsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.201039818:2(256-269)Online publication date: 1-Feb-2010
  • (2009)Probabilistic analysis and design of metallic-carbon-nanotube-tolerant digital logic circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.202319728:9(1307-1320)Online publication date: 1-Sep-2009
  • (2008)Noise separation in analog integrated circuits using independent component analysis techniqueIntegrated Computer-Aided Engineering10.5555/1367166.136717115:2(163-180)Online publication date: 1-Apr-2008
  • (2008)Compound noise separation in digital circuits using blind source separationMicroelectronics Journal10.1016/j.mejo.2008.01.07039:8(1083-1092)Online publication date: Aug-2008
  • (2006)Crosstalk analysis using reconvergence correlationProceedings of the 2006 Asia and South Pacific Design Automation Conference10.1145/1118299.1118318(79-83)Online publication date: 24-Jan-2006
  • (2006)Fast Sequential Cell Noise Immunity Characterization Using Meta-stable Point of Feedback LoopProceedings of the 7th International Symposium on Quality Electronic Design10.1109/ISQED.2006.67(153-159)Online publication date: 27-Mar-2006
  • (2006)TBNM - Transistor-Level Boundary Model for Fast Gate-Level Noise Analysis of Macro BlocksProceedings of the 7th International Symposium on Quality Electronic Design10.1109/ISQED.2006.131(147-152)Online publication date: 27-Mar-2006
  • (2005)Noise margin analysis for dynamic logic circuitsProceedings of the 2005 IEEE/ACM International conference on Computer-aided design10.5555/1129601.1129660(406-412)Online publication date: 31-May-2005
  • (2005)A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysisProceedings of the 42nd annual Design Automation Conference10.1145/1065579.1065630(186-189)Online publication date: 13-Jun-2005
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