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Emerging power management tools for processor design

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C. Oh,

T. EdwardsAuthors Info & Claims

ISLPED '98: Proceedings of the 1998 international symposium on Low power electronics and design

Pages 143 - 148

https://doi.org/10.1145/280756.280866

Published: 10 August 1998 Publication History

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Abstract

Power management is an increasing concern for processor design. In this paper, we presented an overview of traditional power simulation tools and discussed two emerging power management design technologies: power distribution integrity analysis and standby current measurement and optimization. We present methods for accurate peak current simulation, which is needed for power grid integrity analysis, and discuss the generation and compression of the simulation vectors. Also, static approaches for calculating an upper-bound on the maximum peak current are presented. Standby leakage current is state dependent and we present methods for calculating both the average and maximum leakage current. Finally, optimization methods for minimizing the leakage current by either assigning a standby state to the circuit or by using a dual-Vt process are discussed.

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Cited By

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Kalita TDas B(2016)A 4 bit Quantum Voltage Comparator based flash ADC for low noise applications2016 Conference on Emerging Devices and Smart Systems (ICEDSS)10.1109/ICEDSS.2016.7587689(24-29)Online publication date: Mar-2016
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Narendra SYe YBorkar SDe VChandrakasan A(2006)Leakage Dependence on Input VectorLeakage in Nanometer CMOS Technologies10.1007/0-387-28133-9_2(21-39)Online publication date: 2006
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Gupta PKahng AMuddu S(2005)Quantifying Error in Dynamic Power Estimation of CMOS CircuitsAnalog Integrated Circuits and Signal Processing10.1007/s10470-005-6759-442:3(253-264)Online publication date: 1-Mar-2005
https://dl.acm.org/doi/10.1007/s10470-005-6759-4
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Emerging power management tools for processor design

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Published In

ISLPED '98: Proceedings of the 1998 international symposium on Low power electronics and design

August 1998

318 pages

ISBN:1581130597

DOI:10.1145/280756

Chairmen:
Anantha Chandrakasan
MIT
,
Sayfe Kiaei
Motorola

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 August 1998

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ISLPED98

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IEEE-EDS
SIGDA
IEEE-SSCS
IEEE-CAS

ISLPED98: International Symposium on Low Power Electronics and Design

August 10 - 12, 1998

California, Monterey, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

View all

Kalita TDas B(2016)A 4 bit Quantum Voltage Comparator based flash ADC for low noise applications2016 Conference on Emerging Devices and Smart Systems (ICEDSS)10.1109/ICEDSS.2016.7587689(24-29)Online publication date: Mar-2016
https://doi.org/10.1109/ICEDSS.2016.7587689
Narendra SYe YBorkar SDe VChandrakasan A(2006)Leakage Dependence on Input VectorLeakage in Nanometer CMOS Technologies10.1007/0-387-28133-9_2(21-39)Online publication date: 2006
https://doi.org/10.1007/0-387-28133-9_2
Gupta PKahng AMuddu S(2005)Quantifying Error in Dynamic Power Estimation of CMOS CircuitsAnalog Integrated Circuits and Signal Processing10.1007/s10470-005-6759-442:3(253-264)Online publication date: 1-Mar-2005
https://dl.acm.org/doi/10.1007/s10470-005-6759-4
Narendra SDe VBorkar SAntoniadis DChandrakasan A(2004)Full-Chip Subthreshold Leakage Power Prediction and Reduction Techniques for Sub-0.18-<tex>$mu$</tex>m CMOSIEEE Journal of Solid-State Circuits10.1109/JSSC.2003.82177639:3(501-510)Online publication date: Mar-2004
https://doi.org/10.1109/JSSC.2003.821776
Kim KJung SKim TSaxena PLiu CKang S(2003)Coupling delay optimization by temporal decorrelation using dual threshold voltage techniqueIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2003.81711111:5(879-887)Online publication date: 1-Oct-2003
https://dl.acm.org/doi/10.1109/TVLSI.2003.817111
Vijaykrishnan NKandemir MIrwin MKim HYe WDuarte D(2003)Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation FrameworkIEEE Transactions on Computers10.1109/TC.2003.115975452:1(59-76)Online publication date: 1-Jan-2003
https://dl.acm.org/doi/10.1109/TC.2003.1159754
Gupta PKahng A(2003)Quantifying error in dynamic power estimation of CMOS circuitsFourth International Symposium on Quality Electronic Design, 2003. Proceedings.10.1109/ISQED.2003.1194745(273-278)Online publication date: 2003
https://doi.org/10.1109/ISQED.2003.1194745
Ho CTzi-Chiang Tang Chin-Ho Lee Chih-Ming Chen Hsin-Yang Tu Chin-Sung Wu Chao-Hsi Chang Chin-Meng Huang (2003)H.323 VoIP telephone implementation embedding a low-power SOC processor2003 IEEE Conference on Electron Devices and Solid-State Circuits (IEEE Cat. No.03TH8668)10.1109/EDSSC.2003.1283506(163-166)Online publication date: 2003
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Su HSapatnekar SNassif SSapatnekar SPedram M(2002)An algorithm for optimal decoupling capacitor sizing and placement for standard cell layoutsProceedings of the 2002 international symposium on Physical design10.1145/505388.505405(68-73)Online publication date: 7-Apr-2002
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QU GKAWABE NUSAMI KPOTKONJAK M(2002)CODE COVERAGE-BASED POWER ESTIMATION TECHNIQUES FOR MICROPROCESSORSJournal of Circuits, Systems and Computers10.1142/S021812660200061611:05(557-574)Online publication date: Oct-2002
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