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38th DAC 2001: Las Vegas, Nevada, USA
- Proceedings of the 38th Design Automation Conference, DAC 2001, Las Vegas, NV, USA, June 18-22, 2001. ACM 2001, ISBN 1-58113-297-2
Panel
- Rita Glover, Marc Halpern, Rich Becks, Richard Kubin, Henry Jurgens, Rick Cassidy, Ted Vucurevich:
Panel: The Electronics Industry Supply Chain: Who Will Do What? 1-2
Nanometer Futures
- Dennis Sylvester, Himanshu Kaul:
Future Performance Challenges in Nanometer Design. 3-8 - Wojciech Maly:
IC Design in High-Cost Nanometer-Technologies Era. 9-14
System-Level Configurability: Bus, Interface, and Processor Design
- Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana:
LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs. 15-20 - Tiberiu Chelcea, Steven M. Nowick:
Robust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive Protocols. 21-26 - Seapahn Meguerdichian, Milenko Drinic, Darko Kirovski:
Latency-Driven Design of Multi-Purpose Systems-On-Chip. 27-30 - Jagesh V. Sanghavi, Albert Wang:
Estimation of Speed, Area, and Power of Parameterizable, Soft IP. 31-34
Making Verification More Efficient
- Dong Wang, Pei-Hsin Ho, Jiang Long, James H. Kukula, Yunshan Zhu, Hi-Keung Tony Ma, Robert F. Damiano:
Formal Property Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines. 35-40 - Maher N. Mneimneh, Fadi A. Aloul, Christopher T. Weaver, Saugata Chatterjee, Karem A. Sakallah, Todd M. Austin:
Scalable Hybrid Verification of Complex Microprocessors. 41-46 - Alfred Kölbl, James H. Kukula, Robert F. Damiano:
Symbolic RTL Simulation. 47-52
SoC and High-Level DFT
- Bulent I. Dervisoglu:
A Unified DFT Architecture for Use with IEEE 1149.1 and VSIA/IEEE P1500 Compliant Test Access Controllers. 53-58 - Wei-Cheng Lai, Kwang-Ting Cheng
:
Instruction-Level DFT for Testing Processor and IP Cores in System-on-a-Chip. 59-64 - Kelly A. Ockunzzi, Christos A. Papachristou:
Test Strategies for BIST at the Algorithmic and Register-Transfer Levels. 65-70
Panel
- Rajesh K. Gupta, Shishpal Rawat, Ingrid Verbauwhede, Gérard Berry, Ramesh Chandra, Daniel Gajski, Kris Konigsfeld, Patrick Schaumont
Panel: The Next HDL: If C++ is the Answer, What was the Question? 71-72
Design for Subwavelength Manufacturability: Impact on EDA
- Warren Grobman, Matt Thompson, Ruoping Wang, Chi-Min Yuan, Ruiqi Tian, Ertugrul Demircan:
Reticle Enhancement Technology: Implications and Challenges for Physical Design. 73-78 - Lars Liebmann, Jennifer Lund, Fook-Luen Heng, Ioana Graur:
Enabling Alternating Phase Shifted Mask Designs for a Full Logic Gate Level: Design Rules and Design Rule Checking. 79-84 - Michael L. Rieger, Jeffrey P. Mayhew, Sridhar Panchapakesan:
Layout Design Methodologies for Sub-Wavelength Manufacturing. 85-88 - Franklin M. Schellenberg, Olivier Toublan, Luigi Capodieci, Bob Socha:
Adoption of OPC and the Impact on Design and Layout. 89-92 - Michael Sanie, Michel Côté, Philippe Hurat, Vinod Malhotra:
A Practical Application of Full-Feature Alternating Phase-Shifting Technology for a Phase-Aware Standard-Cell Design Flow. 93-96
New Ideas in Logic Synthesis
- Chih-Wei Jim Chang, Kai Wang, Malgorzata Marek-Sadowska:
Layout-Driven Hot-Carrier Degradation Minimization Using Logic Restructuring Techniques. 97-102 - Alan Mishchenko, Bernd Steinbach, Marek A. Perkowski:
An Algorithm for Bi-Decomposition of Logic Functions. 103-108 - Martin Charles Golumbic, Aviad Mintz, Udi Rotics:
Factoring and Recognition of Read-Once Functions using Cographs and Normality. 109-114 - Valentina Ciriani:
Logic Minimization using Exclusive OR Gates. 115-120
Analog Design and Modeling
- Jafar Savoj, Behzad Razavi:
Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems. 121-126 - David Goren, Eliyahu Shamsaev, Israel A. Wagner:
A Novel Method for Stochastic Nonlinearity Analysis of a CMOS Pipeline ADC. 127-132 - Sree Ganesan, Ranga Vemuri
Behavioral Partitioning in the Synthesis of Mixed Analog-Digital Systems. 133-138 - Wim Verhaegen, Georges G. E. Gielen:
Efficient DDD-based Symbolic Analysis of Large Linear Analog Circuits. 139-144
Scan-Based Testing
- Irith Pomeranz:
Random Limited-Scan to Improve Random Pattern Testing of Scan Circuits. 145-150 - Ismet Bayraktaroglu, Alex Orailoglu:
Test Volume and Application Time Reduction Through Scan Chain Concealment. 151-155 - Irith Pomeranz, Sudhakar M. Reddy:
An Approach to Test Compaction for Scan Circuits that Enhances At-Speed Testing. 156-161 - Sying-Jyan Wang
Generating Efficient Tests for Continuous Scan. 162-165 - Anshuman Chandra, Krishnendu Chakrabarty
Combining Low-Power Scan Testing and Test Data Compression for System-on-a-Chip. 166-169
Panel
- Gabe Moretti, Tim Hopes, Ramesh Narayanaswamy, Nanette Collins, Dave Kelf, Tom Anderson, Janick Bergeron, Ashish Dixit, Peter Flake:
Panel: Your Core - My Problem? Integration and Verification of IP. 170-171
Configurable Computing: Reconfiguring the Industry
- Patrick Schaumont
A Quick Safari Through the Reconfiguration Jungle. 172-177 - Bill Salefski, Levent Caglar:
Re-Configurable Computing in Wireless. 178-183 - Albert Wang, Earl Killian, Dror E. Maydan, Chris Rowen:
Hardware/Software Instruction Set Configurability for System-on-Chip Processors. 184-188
Interconnect Design Optimization
- Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia:
A Practical Methodology for Early Buffer and Wire Resource Allocation. 189-194 - Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh:
Creating and Exploiting Flexibility in Steiner Trees. 195-198 - Kevin M. Lepak, Irwan Luwandi, Lei He:
Simultaneous Shield Insertion and Net Ordering under Explicit RLC Noise Constraint. 199-202 - Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung:
On Optimum Switch Box Designs for 2-D FPGAs. 203-208
Power Estimation Techniques
- Sanjukta Bhanja, N. Ranganathan:
Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian Networks. 209-214 - Taewhan Kim, Ki-Seok Chung, Chien-Liang Liu:
A Static Estimation Technique of Power Sensitivity in Logic Circuits. 215-219 - Amit Sinha, Anantha P. Chandrakasan:
JouleTrack - A Web Based Tool for Software Energy Profiling. 220-225
Functional Validation Based on Boolean Reasoning (BDD, SAT)
- Miroslav N. Velev, Randal E. Bryant:
Effective Use of Boolean Satisfiability Procedures in the Formal Verification of Superscalar and VLIW Microprocessors. 226-231 - Andreas Kuehlmann, Malay K. Ganai, Viresh Paruthi:
Circuit-based Boolean Reasoning. 232-237 - Christoph Scholl, Bernd Becker
Checking Equivalence for Partial Implementations. 238-243
Verification: Life Beyond Algorithms
- Bob Bentley:
Validating the Intel Pentium 4 Microprocessor. 244-248 - Ken Albin:
Nuts and Bolts of Core and SoC Verification. 249-252 - Füsun Özgüner, Duane W. Marhefka, Joanne DeGroat, Bruce Wile, Jennifer Stofer, Lyle Hanrahan:
Teaching Future Verification Engineers: The Forgotten Side of Logic Design. 253-255
Dissecting an Embedded System: Lessons from Bluetooth
- Torbjörn Grahm, Barry Clark:
SoC Integration of Reusable Baseband Bluetooth IP. 256-261 - Paul T. M. van Zeijl:
One-chip Bluetooth ASIC Challenges. 262
Algorithmic and Compiler Transformations for High-Level Synthesis
- Michael Theobald, Steven M. Nowick:
Transformations for the Synthesis and Optimization of Asynchronous Distributed Control. 263-268 - Sumit Gupta, Nick Savoiu, Sunwoo Kim, Nikil D. Dutt
Speculation Techniques for High Level Synthesis of Control Intensive Designs. 269-272 - Kiran Bondalapati:
Parallelizing DSP Nested Loops on Reconfigurable Architectures using Data Context Switching. 273-276 - Armita Peymandoust, Giovanni De Micheli:
Using Symbolic Algebra in Algorithmic Level DSP Synthesis. 277-282
Gate Delay Calculation
- Clayton B. McDonald, Randal E. Bryant:
Computing Logic-Stage Delays Using Circuit Simulation and Symbolic Elmore Analysis. 283-288 - Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer:
A New Gate Delay Model for Simultaneous Switching and Its Applications. 289-294 - Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj:
Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI Circuits. 295-300
Memory, Bus and Current Testing
- Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Chih-Wea Wang, Cheng-Wen Wu
Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories. 301-306 - Shih-Yu Yang, Christos A. Papachristou
Improving Bus Test Via IDDT and Boundary Scan. 307-312 - Kaamran Raahemifar, Majid Ahmadi:
Fault Characterizations and Design-for-Testability Technique for Detecting IDDQ Faults in CMOS/BiCMOS Circuits. 313-316 - Li Chen, Xiaoliang Bai, Sujit Dey:
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores. 317-320
Panel
- Rob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen:
Panel: (When) Will FPGAs Kill ASICs? 321-322
Inductance 101 and Beyond
- Michael W. Beattie, Lawrence T. Pileggi:
Inductance 101: Modeling and Extraction. 323-328 - Kaushik Gala, David T. Blaauw, Junfeng Wang, Vladimir Zolotov, Min Zhao:
Inductance 101: Analysis and Design Issues. 329-334 - Michael W. Beattie, Lawrence T. Pileggi:
Modeling Magnetic Coupling for On-Chip Interconnect. 335-340 - Yi-Chang Lu
Min/max On-Chip Inductance Models and Delay Metrics. 341-346
Memory Optimization Techniques for DSP Processors
- Catherine H. Gebotys:
Utilizing Memory Bandwidth in DSP Embedded Processors. 347-352 - Sathishkumar Udayanarayanan, Chaitali Chakrabarti:
Address Code Generation for Digital Signal Processors. 353-358 - J. Ramanujam, Jinpyo Hong, Mahmut T. Kandemir, Amit Narayan:
Reducing Memory Requirements of Nested Loops for Embedded Systems. 359-364 - Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas:
Detection of Partially Simultaneously Alive Signals in Storage Requirement Estimation for Data Intensive Applications. 365-370
Technology Dependant Logic Synthesis
- Min Zhao, Sachin S. Sapatnekar:
A New Structural Pattern Matching Algorithm for Technology Mapping. 371-376 - Shrirang K. Karandikar, Sachin S. Sapatnekar:
Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect. 377-382 - Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska:
Latency and Latch Count Minimization in Wave Steered Circuits. 383-388 - Jason Cong, Michail Romesis:
Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping. 389-394
Collaborative and Distributed Design Frameworks
- Juan Antonio Carballo, Stephen W. Director:
Application of Constraint-Based Heuristics in Collaborative Design. 395-400 - Franc Brglez, Hemang Lavana:
A Universal Client for Distributed Networked Design and Computing. 401-406 - Darko Kirovski, Milenko Drinic, Miodrag Potkonjak:
Hypermedia-Aided Design. 407-412 - Tommy Kuhn, Tobias Oppold, Markus Winterholer, Wolfgang Rosenstiel, Mark Edwards, Yaron Kashai:
A Framework for Object Oriented Hardware Specification, Verification, and Synthesis. 413-418
Panel
- Georges G. E. Gielen, Mike Sottak, Mike Murray, Linda Kaye, Maria del Mar Hershenson, Kenneth S. Kundert, Philippe Magarshack, Akria Matsuzawa, Ronald A. Rohrer, Ping Yang:
Panel: When Will the Analog Design Flow Catch Up with Digital Methodology? 419
Closing the Gap Between ASIC and Custom: Design Examples
- David G. Chinnery
Achieving 550Mhz in an ASIC Methodology. 420-425 - Gregory A. Northrop, Pong-Fei Lu:
A Semi-Custom Design Flow in High-Performance Microprocessor Design. 426-431 - Stephen E. Rich, Matthew J. Parker, Jim Schwartz:
Reducing the Frequency Gap Between ASIC and Custom Designs: A Custom Perspective. 432-437
Energy and Flexibility Driven Scheduling
- Dongkun Shin, Jihong Kim, Seongsoo Lee:
Low-Energy Intra-Task Voltage Scheduling Using Static Timing Analysis. 438-443 - Jiong Luo, Niraj K. Jha:
Battery-Aware Static Scheduling for Distributed Real-Time Embedded Systems. 444-449 - Paul Pop
An Approach to Incremental Design of Distributed Embedded Systems. 450-455
Representation and Optimization for Digital Arithmetic Circuits
- Zhan Yu, Meng-Lin Yu, Alan N. Willson Jr.:
Signal Representation Guided Synthesis Using Carry-Save Adders For Synchronous Data-path Circuits. 456-461 - Anmol Mathur, Sanjeev Saluja:
Improved Merging of Datapath Operators using Information Content and Required Precision Analysis. 462-467 - In-Cheol Park
Digital Filter Synthesis Based on Minimal Signed Digit Representation. 468-473
Techniques for IP Protection
- Gang Qu:
Publicly Detectable Techniques for the Protection of Virtual Components. 474-479 - Rupak Majumdar, Jennifer L. Wong
Watermarking of SAT using Combinatorial Isolation Lemmas. 480-485 - Gregory Wolfe, Jennifer L. Wong
Watermarking Graph Partitioning Solutions. 486-489 - Farinaz Koushanfar
Hardware Metering. 490-493
Visualization and Animation for VLSI Design
- Phillip J. Restle:
Technical Visualizations in VLSI Design. 494-499 - Jeff Solomon, Mark Horowitz:
Using Texture Mapping with Mipmapping to Render a VLSI Layout. 500-505 - Marc Najork
Web-based Algorithm Animation. 506-511
Application-Specific Customization for Systems-on-a-Chip
- Peter Petrov, Alex Orailoglu:
Speeding Up Control-Dominated Applications through Microarchitectural Customizations in Embedded Processors. 512-517 - Damien Lyonnard, Sungjoo Yoo, Amer Baghdadi, Ahmed Amine Jerraya:
Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip. 518-523 - Tajana Simunic, Luca Benini, Andrea Acquaviva, Peter W. Glynn, Giovanni De Micheli:
Dynamic Voltage Scaling and Power Management for Portable Systems. 524-529
Satisfiability Solvers and Techniques
- Matthew W. Moskewicz, Conor F. Madigan, Ying Zhao, Lintao Zhang, Sharad Malik
Chaff: Engineering an Efficient SAT Solver. 530-535 - Aarti Gupta
Dynamic Detection and Removal of Inactive Clauses in SAT with Application in Image Computation. 536-541 - Jesse Whittemore, Joonyoung Kim, Karem A. Sakallah:
SATIRE: A New Incremental Satisfiability Engine. 542-545 - Emil Gizdarski, Hideo Fujiwara:
A Framework for Low Complexity Static Learning. 546-549
Power and Interconnect Analysis
- Sheldon X.-D. Tan, Chuanjin Richard Shi:
Fast Power/Ground Network Optimization Based on Equivalent Circuit Modeling. 550-554 - Taku Uchino, Jason Cong:
An Interconnect Energy Model Considering Coupling Effects. 555-558 - Tsung-Hao Chen, Charlie Chung-Ping Chen:
Efficient Large-Scale Power Grid Analysis Based on Preconditioned Krylov-Subspace Iterative Methods. 559-562 - Luca Daniel, Alberto L. Sangiovanni-Vincentelli, Jacob White:
Using Conduction Modes Basis Functions for Efficient Electromagnetic Analysis of On-Chip and Off-Chip Interconnect. 563-566 - Amir H. Ajami, Kaustav Banerjee, Massoud Pedram, Lukas P. P. P. van Ginneken:
Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs. 567-572
Domain Specific Design Methodologies
- Ireneusz Janiszewski, Bernhard Hoppe, Hermann Meuth:
VHDL-Based Design and Design Methodology for Reusable High Performance Direct Digital Frequency Synthesizers. 573-578 - Ramesh Karri
Concurrent Error Detection of Fault-Based Side-Channel Cryptanalysis of 128-Bit Symmetric Block Ciphers. 579-585 - Seapahn Meguerdichian, Farinaz Koushanfar
MetaCores: Design and Optimization Techniques. 585-590
Panel
- Andrew B. Kahng, Bing J. Sheu, Nancy Nettleton, John M. Cohn, Shekhar Borkar, Louis Scheffer, Ed Cheng, Sang Wang:
Panel: Is Nanometer Design Under Control? 591-592
Analysis and Implementation for Embedded Systems
- Leonardo Maria Reyneri, Franceso Cucinotta, Alessandro Serra, Luciano Lavagno:
A Hardware/Software Co-design Flow and IP Library Based of SimulinkTM. 593-598 - Amit Nandi, Radu Marculescu:
System-Level Power/Performance Analysis for Embedded Systems Design. 599-604 - Tat Kee Tan, Anand Raghunathan
High-level Software Energy Macro-modeling. 605-610
Industrial Case Studies in Verification
- Hoon Choi, Byeong-Whee Yun, Yun-Tae Lee, Hyunglae Roh:
Model Checking of S3C2400X Industrial Embedded SOC Product. 611-616 - Julia Dushina, Mike Benjamin, Daniel Geist:
Semi-Formal Test Generation with Genevieve. 617-622 - Murali Kudlugi, Soha Hassoun, Charles Selvidge, Duaine Pryor:
A Transaction-Based Unified Simulation/Emulation Architecture for Functional Verification. 623-628
Integrated High-Level Synthesis Based Solutions
- Alex Doboli, Ranga Vemuri:
Integrated High-Level Synthesis and Power-Net Routing for Digital Design under Switching Noise Constraints. 629-634 - Kia Bazargan, Seda Ogrenci, Majid Sarrafzadeh:
Integrating Scheduling and Physical Design into a Coherent Compilation Cycle for Reconfigurable Computing Architectures. 635-640 - Davide Bruni, Alessandro Bogliolo, Luca Benini:
Statistical Design Space Exploration for Application-Specific Unit Synthesis. 641-646
Timing Verification and Simulation
- Murali Kudlugi, Charles Selvidge, Russell Tessier:
Static Scheduling of Multiple Asynchronous Domains For Functional Verification. 647-652 - Tong Xiao, Malgorzata Marek-Sadowska:
Functional Correlation Analysis in Crosstalk Induced Critical Paths Identification. 653-656 - Hakan Yalcin, Robert Palermo, Mohammad Mortazavi, Cyrus Bamji, Karem A. Sakallah, John P. Hayes:
An Advanced Timing Characterization Method Using Mode Dependency. 657-660 - Jing-Jia Liou, Kwang-Ting Cheng, Sandip Kundu, Angela Krstic:
Fast Statistical Timing Analysis By Probabilistic Event Propagation. 661-666
On-Chip Communication Architectures
- Marco Sgroi, Michael Sheets, Andrew Mihal, Kurt Keutzer, Sharad Malik
Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design. 667-672 - Drew Wingard:
MicroNetwork-Based Integration for SOCs. 673-677 - Faraydon Karim, Anh Nguyen, Sujit Dey, Ramesh R. Rao:
On-Chip Communication Architecture for OC-768 Network Processors. 678-683 - William J. Dally, Brian Towles:
Route Packets, Not Wires: On-Chip Interconnection Networks. 684-689
Compiler and Architecture Interactions
- Mahmut T. Kandemir, J. Ramanujam
Dynamic Management of Scratch-Pad Memory Space. 690-695 - Margarida F. Jacome, Gustavo de Veciana, Satish Pillai:
Clustered VLIW Architectures with Predicated Switching. 696-701 - Viktor S. Lapinskii, Margarida F. Jacome, Gustavo de Veciana:
High-Quality Operation Binding for Clustered VLIW Datapaths. 702-707 - Holger Keding, Martin Coors, Olaf Lüthje, Heinrich Meyr:
Fast Bit-True Simulation. 708-713
Timing with Crosstalk
- Hai Zhou, Narendra V. Shenoy, William Nicholls:
Timing Analysis with Crosstalk as Fixpoints on Complete Lattice. 714-719 - Supamas Sirichotiyakul, David T. Blaauw, Chanhee Oh, Rafi Levy, Vladimir Zolotov, Jingyan Zuo:
Driver Modeling and Alignment for Worst-Case Delay Noise. 720-725 - Ravishankar Arunachalam, Ronald D. Blanton, Lawrence T. Pileggi:
False Coupling Interactions in Static Timing Analysis. 726-731 - Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang:
Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. 732-737
Low Power Design: Systems to Interconnect
- Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha:
Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optimization. 738-743 - Jörg Henkel, Haris Lekatsas:
A2BC: Adaptive Address Bus Coding for Low Power Deep Sub-Micron Designs. 744-749 - Youngsoo Shin, Takayasu Sakurai:
Coupling-Driven Bus Design for Low-Power Application-Specific Systems. 750-753 - Clark N. Taylor, Sujit Dey, Yi Zhao:
Modeling and Minimization of Interconnect Energy Dissipation in Nanometer Technologies. 754-757 - Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou:
A True Single-Phase 8-bit Adiabatic Multiplier. 758-763
Floorplanning Representations and Placement Algorithms
- Jai-Ming Lin, Yao-Wen Chang:
TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans. 764-769 - Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List. 770-775 - Mehmet Can Yildiz, Patrick H. Madden:
Improved Cut Sequences for Partitioning Based Placement. 776-779 - Bill Halpin, C. Y. Roger Chen, Naresh Sehgal:
Timing Driven Placement using Physical Net Constraints. 780-783 - Luca Benini, Luca Macchiarulo, Alberto Macii, Enrico Macii, Massimo Poncino:
From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip. 784-789
Panel
- Steven E. Schulz, Georgia Marszalek, Greg Hinckley, Gregory S. Spirakis, Karen Vahtra, John A. Darringer, J. George Janac, Handel H. Jones:
Panel: What Drives EDA Innovation? 790-791
Signal Integrity: Avoidance and Test Techniques
- Mehrdad Nourani, Amir Attarha:
Built-In Self-Test for Signal Integrity. 792-797 - Kaustav Banerjee, Amit Mehrotra:
Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects. 798-803 - Yehia Massoud, Jamil Kawa, Don MacMillen, Jacob White:
Modeling and Analysis of Differential Signaling for Minimizing Inductive Cross-Talk. 804-809
Novel Approaches to Microprocessor Design and Verification
- Daniel Kroening
Automated Pipeline Design. 810-815 - Kazuyoshi Kohno, Nobu Matsumoto:
A New Verification Methodology for Complex Pipeline Behavior. 816-821 - Richard Lee, Benjamin Tsien:
Pre-silicon Verification of the Alpha 21364 Microprocessor Error Handling System. 822-827
Scheduling Techniques for Power Management
- Gang Quan
Energy Efficient Fixed-Priority Scheduling for Real-Time Systems on Variable Voltage Processors. 828-833 - Qinru Qiu, Qing Wu, Massoud Pedram:
Dynamic Power Management in a Mobile Multimedia System with Guaranteed Quality-of-Service. 834-839 - Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh, Fadi J. Kurdahi:
Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems. 840-845
Novel Devices and Yield Optimization
- Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes:
Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration. 846-851 - Seungbae Lee, Gi-Joon Nam, Junseok Chae, Hanseup Kim, Alan J. Drake:
Two-Dimensional Position Detection System with MEMS Accelerometer for MOUSE Applications. 852-857 - Frank Schenkel, Michael Pronath, Stephan Zizala, Robert Schwencker, Helmut E. Graeb, Kurt Antreich:
Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search. 858-863
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