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ISQED 2001: San Jose, California, USA
- 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA. IEEE Computer Society 2001, ISBN 0-7695-1025-6
Tutorial
- Yervant Zorian:
System-on-Chip: Embedded Test Strategies. 7 - Kaushik Roy, Ali Keshavarzi:
Design and Test of Low Voltage CMOS Circuits. 7 - Mo Tamjidi, Bejoy G. Oomman:
Redundancy Requirements for Embedded Memories. 8 - Andrew B. Kahng, Ronald Collett, Ton. H. van de Kraats:
Design Metrics to Achieve Design Quality. 9 - Phil Dworsky, Warren Savage:
Fundamental Methods to Enable SoC Design and Reuse. 9 - Charvaka Duvvury:
Issues in Deep Submicron State-of-the-Art ESD Design. 10 - Noel R. Strader, Gérard Memmi, Carl Pixley:
Application of Formal Verification to Design Creation and Implementation. 11 - Magdy S. Abadir, Li-C. Wang:
Verification and Validation of Complex Digital Systems: An Industrial Perspective. 11-12 - Daniel Foty, David M. Binkley:
Re-Connecting MOS Modeling and Circuit Design: New Methods for Design Quality. 13 - Narain Arora, N. S. Nagaraj:
Interconnect Modeling for Timing, Signal Integrity and Reliability. 13 - Tak Young:
On-Chip Inductance Extraction and Modeling. 14
Evening Panel Discussion
- Rick Merritt, Richard Goering:
The 50-Million Transistor Chip: The Quality Challenge for 2001. 15-18
Plenary Session
- Hajimi Sasaki:
Future Platform for Mobile Communication. 21-22 - Joe Costello:
Delivering Quality Delivers Profits. 23-24 - Raul Camposano:
The Expanding Use of Formal Techniques in Electronic Design. 25-26 - Edward C. Ross:
IC Design Methodology in the Foundry Era: Introducing , Heads-Up(tm) Design. 27-
Impact of Verification on Complex SOC Quality
- Amjad Hajjar, Tom Chen, Isabelle Munn, Anneliese Amschler Andrews, Maria Bjorkman:
Stopping Criteria Comparison: Towards High Quality Behavioral Verification. 31-37 - Umberto Rossi, Andrea Fedeli, Marco Boschini, Franco Toto:
Concrete Impact of Formal Verification on Quality in IP Design and Implementation. 38-43 - Zan Yang, Byeong Min, Gwan Choi:
Simulation Using Code-Perturbation: Black- and White-Box Approach. 44-49 - F. Sforza, L. Battú, M. Brunelli, A. Castelnuovo, M. Magnaghi:
A "Design for Verification" Methodology. 50-55 - Mohammed El Shobaki, Lennart Lindh:
A Hardware and Software Monitor for High-Level System-on-Chip Verification. 56-61
Quality of EDA Tools and Design Methodologies
- Paul Kartschoke, Shervin Hojat:
Techniques that Improved the Timing Convergence of the Gekko PowerPC Microprocessor. 65-70 - Gulsun Yasar, Charles Chiu, Robert A. Proctor, James P. Libous:
I/O Cell Placement and Electrical Checking Methodology for ASICs with Peripheral I/Os. 71-75 - Giora Ben-Yaacov, Edward P. Stone, Richard Goldman:
Applying Moore's Technology Adoption Life Cycle Model to Quality of EDA Software. 76-80 - Andrew B. Kahng, Stefanus Mantik:
A System for Automatic Recording and Prediction of Design Quality Metrics. 81-86 - Pinhong Chen, Kurt Keutzer, Desmond Kirkpatrick:
Scripting for EDA Tools: A Case Study. 87-93
Design, Fabrication and Reliability Challenges for Emerging Technologies
- Akira Matsuzawa:
High Quality Analog CMOS and Mixed Signal LSI Design. 97-104 - Kenneth L. Shepard:
CAD Issues for CMOS VLSI Design in SOI. 105-110 - Sheldon Wu, Fred Wang, Lie-Szu Juang:
Foundry's Perspective of System Integration: Quality Design and Time-to-Volume. 111-116 - Choshu Ito, Kaustav Banerjee, Robert W. Dutton:
Analysis and Design of ESD Protection Circuits for High-Frequency/RF Applications. 117-122 - J. W. McPherson:
Scaling-Induced Reductions in CMOS Reliability Margins and the Escalating Need for Increased Design-In Reliability Efforts. 123-130
Capacitive Crosstalk Analysis
- Ninglong Lu, Ibrahim N. Hajj:
A Fast Coupling Aware Delay Estimation Scheme Based on Simplified Circuit Model. 133-138 - Pirouz Bazargan-Sabet, Fabrice Ilponse:
A Model for Crosstalk Noise Evaluation in Deep Submicron Processes. 139-144 - Andrew B. Kahng, Sudhakar Muddu, Niranjan Pol, Devendra Vidhani:
Noise Model for Multiple Segmented Coupled RC Interconnects. 145-150 - Qingjian Yu, Ernest S. Kuh:
New Efficient and Accurate Moment Matching Based Model for Crosstalk Estimation in Coupled RC Trees. 151-157 - Murat R. Becer, David T. Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov, Jingyan Zuo, Rafi Levy, Ibrahim N. Hajj:
A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance. 158-163
Interconnect Modeling and Analysis
- Asim Husain:
Models For Interconnect Capacitance Extraction. 167-172 - Tom Chen:
Impact of On-Chip Inductance When Transitioning from Al to Cu Based Technology. 173-178 - Yusuke Nakashima, Makoto Ikeda, Kunihiro Asada:
Computational Cost Reduction in Extracting Inductance. 179-184 - Yu Cao, Xuejue Huang, Chenming Hu, Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie:
Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion. 185-190 - Mehdi M. Mechaik:
Signal Attenuation in Transmission Lines. 191-196
Power-Aware Design
- Wei-Chung Cheng, Massoud Pedram:
Memory Bus Encoding for Low Power: A Tutorial. 199-204 - Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj:
RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits. 205-210 - Zhenyu Tang, Lei He, Norman Chang, Shen Lin, Weize Xie, O. Sam Nakagawa:
Instruction Prediction for Step Power Reduction. 211-216 - Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes:
Power Trends and Performance Characterization of 3-Dimensional Integration for Future Technology Generations. 217-222 - Juan A. Montiel-Nelson, V. de Armas
, Roberto Sarmiento
A Compact Layout Technique for Reducing Switching Current Effects in High Speed Circuits. 223-228
Evening Panel Discussion
- Bill Alexander, Jacques Benkoski:
0.13 micron: Will the Speed Bumps Slow the Race to Market? 229-232
Plenary Session II
- Wojciech Maly:
Quality of Design from an IC Manufacturing Perspective. 235-236 - Vinod Agrawal:
Embedded Test Leads to Embedded Quality. 237-238 - Aki Fujimura:
Quality on Time. 239-240 - Philippe Magarshack:
Quality of SoC Designs through Quality of the Design Flow: Status and Needs. 241-
Ph.D. Student Forum
- Nguyen Quang Trung, Krystyna Siekierska:
Soft Core Based Model of a Microcomputer Family. 245-246 - Tung-Yang Chen, Ming-Dou Ker:
Design on ESD Protection Circuit with Very Low and Constant Input Capacitance. 247-248 - Subhasish Mitra, Edward J. McCluskey:
Diversity Techniques for Concurrent Error Detection. 249-250 - Peter Verplaetse:
Refinements of Rent's Rule Allowing Accurate Interconnect Complexity Modeling. 251-252 - Vlado Vorisek:
Test Pattern Generators for Distributed and Embedded Built-in Self-Test at Register Transfer Level. 253-254 - Steffen Klupsch:
Design, Integration and Validation of Heterogeneous Systems. 255-256 - Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj:
RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits. 257-258
Poster Session
- Ming-Dou Ker, Wen-Yu Lo, Tung-Yang Chen, Howard Tang, S.-S. Chen, Mu-Chun Wang
Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process. 267-272 - Alexander Zemliak:
One Approach to Analog System Design Problem Formulation. 273-278 - Mark Birnbaum, Charlene C. Johnson:
VSIA Quality Metrics for IP and SoC. 279-283 - Wei Li, Qiang Li, J. S. Yuan, Joshua McConkey, Yuan Chen, Sundar Chetlur, Jonathan Zhou, A. S. Oates:
Hot-carrier-Induced Circuit Degradation for 0.18 µm CMOS Technology. 284-289 - Tom Egan, Samiha Mourad:
Verification of Embedded Phase-Locked Loops. 290-295 - Alexander Korshak, Jyh-Chwen Lee:
An Effective Current Source Cell Model for VDSM Delay Calculation. 296-300 - Mehdi M. Mechaik:
An Evaluation of Single-Ended and Differential Impedance in PCBs. 301-306 - Yi-Min Jiang, Han Young Koh, Kwang-Ting Cheng
HRM - A Hierarchical Simulator for Full-Chip Power Network Reliability Analysis. 307-312 - Ning Zhu, Han Young Koh:
Power Grid Modeling Technique for Hierarchical Power Network Analysis. 313-318 - Imed Ben Dhaou
Energy Efficient Signaling in Deep Submicron CMOS Technology. 319-324 - Rong Lin:
Trading Bitwidth For Array Size: A Unified Reconfigurable Arithmetic Processor Design. 325-330 - Mihaela Radu, Dan Pitica, Radu Munteanu, Cristian Posteuca:
Complex Reliability Evaluation of Voters for Fault Tolerant Designs. 331-336 - Josef Schmid, Timo Schüring, Christoph Smalla:
Using the Boundary Scan Delay Chain for Cross-Chip Delay Measurement and Characterization of Delay Modeling Flow. 337-342 - Nektarios Kranitis
An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths. 343-349 - Dimitris Bakalis, Dimitris Nikolos, Haridimos T. Vergos, Xrysovalantis Kavousianos:
On Accumulator-Based Bit-Serial Test Response Compaction Schemes. 350-355
Defect Analysis and Test Generation
- Michel Renovell:
Revisiting the Classical Fault Models through a Detailed Analysis of Realistic Defects. 359-364 - Wieslaw Kuzmicz
Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. 365-371 - Chien-Nan Jimmy Liu, Chia-Chih Yen, Jing-Yang Jou:
Automatic Functional Vector Generation Using the Interacting FSM Model. 372-377 - Jayant Deodhar, Spyros Tragoudas:
Color Counting and its Application to Path Delay Fault Coverage. 378-383 - Maria K. Michael, Spyros Tragoudas:
ATPG for Path Delay Faults without Path Enumeration. 384-389
Design of Programmable and Platform-Based IP
- Rafael Peset Llopis, Marcel Oosterhuis, Ramanathan Sethuraman, Paul E. R. Lippens, Albert van der Werf, Steffen Maul, Jim Lin:
HW-SW Co-Design and Verification of a Multi-Standard Video and Image Codec. 393-398 - Martin Speitel, Michael Schlicht, Martin Leyh:
Acceleration of DAB Chipset Development by Deployment of a Real-time Rapid Prototyping Approach based on Behavioral Synthesis. 399-404 - Chih-Yuan Chen, Shing-Wu Tung:
ELITE Design Methodology of Foundation IP for Improving Synthesis Quality. 405-408 - Artur Chojnacki, Lech Józwiak:
High-quality FPGA Designs through Functional Decomposition with Sub-function Input Support Selection Based on Information Relationship Measures. 409-414 - Kazimierz Wiatr, Ernest Jamro:
Implementation of Multipliers in FPGA Structures. 415-420
Embedded Panel Discussion
- Nader Vasseghi, Steve Ohr:
Consequences of Technology: What is the Impact of Electronic Design on the Quality of Life? 421-
Design for Manufacturability
- Ron Ross, Keith McCasland:
Early Detection of Design Sensitivities that Cause Yield Loss for New Products. 427-430 - Emrah Acar, Lawrence T. Pileggi, Sani R. Nassif, Ying Liu:
Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations. 431-436 - Anne E. Gattiker, Sani R. Nassif, Rashmi Dinakar, Chris Long:
Timing Yield Estimation from Static Timing Analysis. 437-442 - Tae-Jin Kwon, Sang-Hoon Lee, Tae-Seon Kim
Performance Improvement for High Speed Devices Using E-tests and the SPICE Model. 443-447
Embedded Memories
- Pierluigi Daglio, M. Araldi, Michele Morbarigazzi
A Fully Qualified Analog Design Flow for Non Volatile Memories Technologies. 451-455 - Konstantinos Tatas
Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores 1. 456-461 - Nai-Yin Sung, Tsung-Yi Wu:
A Method of Embedded Memory Access Time Measurement. 462-465
Device Modeling and Design Quality
- Amit Mehrotra:
Noise in Radio Frequency Circuits: Analysis and Design Implications. 469-476 - Peter Bendix:
Spice Model Quality: Process Development Viewpoint. 477-481 - Yoshitaka Murasaka, Makoto Nagata
Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation. 482-487 - Stefano Zanella, Andrea Neviani
Modeling of Substrate Noise Injected by Digital Libraries. 488-492
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