[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ skip to main content
10.1145/337292.337400acmconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
Article
Free access

ClariNet: a noise analysis tool for deep submicron design

Published: 01 June 2000 Publication History

Abstract

Coupled noise analysis has become a critical issue for deep-submicron, high performance design. In this paper, we present, ClariNet, an industrial noise analysis tool, which was developed to efficiently analyze large, high performance processor designs. We present the overall approach and tool flow of ClariNet and discuss three critical large-processor design issues which have received limited discussion in the past. First, we present how the driver gates of a coupled interconnect network are represented with accurate linear models. Second, we show how to speed the analysis of large designs by using noise filters based on reduced interconnect representations and then pruning the nets coupled to a signal net. Third, we show how to incorporate logic and timing correlations into noise analysis to reduce its pessimism. We present the results from several industrial circuits, including a large high performance microprocessor design and a DSP design.

References

[1]
A. Devgan, "Efficient coupled noise estimation for on-chip interconnects," Proc. IEEE Intl. Conf. Computer-Aided Design, pp. 147-151, Nov. 1997.
[2]
A. Dharchoudhury, D. Blaauw, J. Norton, S. Pullela and J. Dunning, "Transistor-level sizing and timing verification of domino circuits in the PowerPCTM microprocessor", Proc. Intl. Conf. Computer Design, pp. 143-148, 1997.
[3]
M. Kuhlmann, S. S. Sapatnekar and K. K. Parhi," Efficient crosstalk Estimation," Proc. IEEE Intl. Conf. Computer Design, pp. 266-272, Oct 1999.
[4]
A. Odabasioglu, M. Celik and L. T. Pileggi, "PRIMA: Passive reduced-order interconnect macromodeling algorithm," Proc. Intl. Conf. Computer-Aided Design, pp. 58- 65, 1997.
[5]
J. Qian, S. Pullela and L. T. Pillage, "Modeling the effective capacitance for the RC interconnect of CMOS gates," IEEE Trans. Computer-Aided Design, pp. 1526-1555, Dec 1994.
[6]
K.L. Sheppard, V. Narayanan, E C. Elementary and G. Zheng, "Global Harmony: Coupled noise analysis for fullchip RC interconnect networks," Proc. Intl. Conf. Computer-Aided Design, pp. 139-146, 1997.
[7]
M. Zurada, Y. S. Joo, S. V. Bell, "Dynamic noise margins MOS logic gates", Proc. IEEE ISCAS, pp. 1153-1156, 989.
[8]
V. Zolotov et al," Closed form noise filter expressions", Tech Report, Motorola.

Cited By

View all

Recommendations

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences
DAC '00: Proceedings of the 37th Annual Design Automation Conference
June 2000
819 pages
ISBN:1581131879
DOI:10.1145/337292
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 2000

Permissions

Request permissions for this article.

Check for updates

Qualifiers

  • Article

Conference

DAC00
Sponsor:
DAC00: ACM/IEEE-CAS/EDAC Design Automation Conference
June 5 - 9, 2000
California, Los Angeles, USA

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25
62nd ACM/IEEE Design Automation Conference
June 22 - 26, 2025
San Francisco , CA , USA

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)73
  • Downloads (Last 6 weeks)6
Reflects downloads up to 06 Dec 2024

Other Metrics

Citations

Cited By

View all
  • (2022)Routing in SoC Physical DesignSoC Physical Design10.1007/978-3-030-98112-9_5(65-80)Online publication date: 7-Jun-2022
  • (2015)Variation aware cross-talk aggressor alignment by mixed integer linear programmingProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744924(1-6)Online publication date: 7-Jun-2015
  • (2014)A New Spatial Correlation Model Based on the Distributed RC- ModelAdvanced Materials Research10.4028/www.scientific.net/AMR.989-994.2204989-994(2204-2207)Online publication date: Jul-2014
  • (2013)Crosstalk timing windows overlap in statistical static timing analysisInternational Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2013.6523617(245-251)Online publication date: Mar-2013
  • (2011)Fast waveform estimation (FWE) for timing analysisIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2010.204180119:5(846-856)Online publication date: 1-May-2011
  • (2010)Built-in sensor for signal integrity faults in digital interconnect signalsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.201039818:2(256-269)Online publication date: 1-Feb-2010
  • (2010)Victim alignment in crosstalk-aware timing analysisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.203548429:2(261-274)Online publication date: 1-Feb-2010
  • (2008)Transistor level gate modeling for accurate and fast timing, noise, and power analysisProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391588(456-461)Online publication date: 8-Jun-2008
  • (2008)A noniterative equivalent waveform model for timing analysis in presence of crosstalkACM Transactions on Design Automation of Electronic Systems10.1145/1344418.134442113:2(1-21)Online publication date: 23-Apr-2008
  • (2008)Static Crosstalk Noise Analysis with Transition Map4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008)10.1109/DELTA.2008.26(462-465)Online publication date: Jan-2008
  • Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media