Coupled noise analysis has become a critical issue for deep-submicron, high performance design. In this paper, we present, ClariNet, an industrial noise analysis tool, which was developed to efficiently analyze large, high performance processor designs. We present the overall approach and tool flow of ClariNet and discuss three critical large-processor design issues which have received limited discussion in the past. First, we present how the driver gates of a coupled interconnect network are represented with accurate linear models. Second, we show how to speed the analysis of large designs by using noise filters based on reduced interconnect representations and then pruning the nets coupled to a signal net. Third, we show how to incorporate logic and timing correlations into noise analysis to reduce its pessimism. We present the results from several industrial circuits, including a large high performance microprocessor design and a DSP design.

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Chakravarthi VKoteshwar SChakravarthi VKoteshwar S(2022)Routing in SoC Physical DesignSoC Physical Design10.1007/978-3-030-98112-9_5(65-80)Online publication date: 7-Jun-2022
https://doi.org/10.1007/978-3-030-98112-9_5
Zolotov VFeldmann P(2015)Variation aware cross-talk aggressor alignment by mixed integer linear programmingProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744924(1-6)Online publication date: 7-Jun-2015
https://dl.acm.org/doi/10.1145/2744769.2744924
Liu XShao JZhao L(2014)A New Spatial Correlation Model Based on the Distributed RC-_∏ ModelAdvanced Materials Research10.4028/www.scientific.net/AMR.989-994.2204989-994(2204-2207)Online publication date: Jul-2014
https://doi.org/10.4028/www.scientific.net/AMR.989-994.2204
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ClariNet: a noise analysis tool for deep submicron design

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DAC '00: Proceedings of the 37th Annual Design Automation Conference

June 2000

819 pages

ISBN:1581131879

DOI:10.1145/337292

Chairman:
Giovanni De Micheli
Stanford Univ., Stanford, CA

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Chakravarthi VKoteshwar SChakravarthi VKoteshwar S(2022)Routing in SoC Physical DesignSoC Physical Design10.1007/978-3-030-98112-9_5(65-80)Online publication date: 7-Jun-2022
https://doi.org/10.1007/978-3-030-98112-9_5
Zolotov VFeldmann P(2015)Variation aware cross-talk aggressor alignment by mixed integer linear programmingProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744924(1-6)Online publication date: 7-Jun-2015
https://dl.acm.org/doi/10.1145/2744769.2744924
Liu XShao JZhao L(2014)A New Spatial Correlation Model Based on the Distributed RC-_∏ ModelAdvanced Materials Research10.4028/www.scientific.net/AMR.989-994.2204989-994(2204-2207)Online publication date: Jul-2014
https://doi.org/10.4028/www.scientific.net/AMR.989-994.2204
Fatemi HTehrani P(2013)Crosstalk timing windows overlap in statistical static timing analysisInternational Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2013.6523617(245-251)Online publication date: Mar-2013
https://doi.org/10.1109/ISQED.2013.6523617
Xu JChowdhury M(2011)Fast waveform estimation (FWE) for timing analysisIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2010.204180119:5(846-856)Online publication date: 1-May-2011
https://dl.acm.org/doi/10.1109/TVLSI.2010.2041801
Champac VAvendaño VFigueras J(2010)Built-in sensor for signal integrity faults in digital interconnect signalsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.201039818:2(256-269)Online publication date: 1-Feb-2010
https://dl.acm.org/doi/10.1109/TVLSI.2008.2010398
Gandikota RChopra KBlaauw DSylvester D(2010)Victim alignment in crosstalk-aware timing analysisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.203548429:2(261-274)Online publication date: 1-Feb-2010
https://dl.acm.org/doi/10.1109/TCAD.2009.2035484
Raja SVaradi FBecer MGeada JFix L(2008)Transistor level gate modeling for accurate and fast timing, noise, and power analysisProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391588(456-461)Online publication date: 8-Jun-2008
https://dl.acm.org/doi/10.1145/1391469.1391588
Muchherla KChen PMa DWang J(2008)A noniterative equivalent waveform model for timing analysis in presence of crosstalkACM Transactions on Design Automation of Electronic Systems10.1145/1344418.134442113:2(1-21)Online publication date: 23-Apr-2008
https://dl.acm.org/doi/10.1145/1344418.1344421
Zhang MLi HLi X(2008)Static Crosstalk Noise Analysis with Transition Map4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008)10.1109/DELTA.2008.26(462-465)Online publication date: Jan-2008
https://doi.org/10.1109/DELTA.2008.26
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