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JPH05211128A - 薄い半導体材料フィルムの製造方法 - Google Patents

薄い半導体材料フィルムの製造方法

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Publication number
JPH05211128A
JPH05211128A JP4246594A JP24659492A JPH05211128A JP H05211128 A JPH05211128 A JP H05211128A JP 4246594 A JP4246594 A JP 4246594A JP 24659492 A JP24659492 A JP 24659492A JP H05211128 A JPH05211128 A JP H05211128A
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Prior art keywords
wafer
ions
temperature
semiconductor
thin film
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JP3048201B2 (ja
Inventor
Michel Bruel
ミシエル・ブリユエル
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Abstract

(57)【要約】 【目的】 単結晶質フィルムの製造に適用可能な薄い半
導体材料フィルムの製造方法を提供する。 【構成】 薄い単結晶質又は多結晶質半導体材料フィル
ムの製造方法は、平面を有する半導体材料ウェーハを、
以下の３つの段階：基板のバルクを構成する下方区域６
と薄いフィルムを構成する上方区域５とを前記ウェーハ
の容積部内に限定する微小気泡の層３を前記ウェーハの
容積部に生じる、イオンにより行われる前記ウェーハ１
の面４へのボンバード２による注入の第１段階と、前記
ウェーハの平面４を、少なくとも１つの剛性材料層から
なる補剛材７と密着させる第２段階と、イオンボンバー
ド２が実施される温度よりも高く、且つウェーハ１中の
結晶再配列作用及び微小気泡内の圧力作用により薄いフ
ィルム５と基板６のバックとを分離させるのに十分な温
度で前記ウェーハ１と前記補剛材７とのアセンブリを熱
処理する第３段階とに付すことを包含することを特徴と
する。

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は、薄い半導体材料フィル
ム、好ましくは単結晶質フィルムの製造に適用可能な製
造方法に関する。
【０００２】
【従来の技術】単結晶質半導体フィルムの製造には種々
の方法があるが、多結晶質材料フィルム又は非晶質材料
フィルムの製造が比較的簡単である一方で、単結晶質フ
ィルムの製造が遥かに困難なために、これらの方法の実
施がしばしば複雑で、費用がかかることは知られてい
る。
【０００３】単結晶質フィルムの製造に使用されている
方法の中には、いわゆる“絶縁体上シリコン”基板の製
造に使用されている方法がある。この方法の目的は、フ
ィルムから電気的に絶縁された基板上に位置する単結晶
質シリコンフィルムを製造することである。
【０００４】結晶成長ヘテロエピタキシ法により、格子
パラメータがシリコンのパラメータに近い他の型の単結
晶質基板、例えばサファイア基板（Ａｌ2Ｏ3）又はフッ
化カルシウム基板（ＣａＦ2）上に例えば薄いフィルム
のシリコン結晶を成長させることができる。（参考文献
５を参照）。
【０００５】ＳＩＭＯＸ法（この名称は文献で使用され
ている）は、基板のバルクから単結晶質シリコンフィル
ムを分離する酸化シリコン層をシリコン容積部内に設け
るために、シリコン基板内への酸素線量の多いイオンの
注入を使用している。（参考文献１参照）。
【０００６】他の方法は、化学的又はメカノケミカル的
摩耗によるウェーハの薄片化（ｔｈｉｎｎｉｎｇ）の原
理を使用している。このカテゴリーで最も成功をおさめ
た方法は更にエッチストップの原理を使用している。こ
の方法では、必要な厚さが達せられるとすぐにウェーハ
の薄片化を停止させることができ、このようにして均一
な厚さを確保することができる。この方法は例えば、製
造が所望されているフィルムの厚さ全体にわたりｎ型基
板へのｐ型ドーピングを施し、次いでｎ型シリコンには
活性で、ｐ型シリコンには不活性な化学浴で基板を化学
腐食させることからなる（参考文献２及び３を参照）。
【０００７】単結晶質半導体フィルムの主要用途は、Ｘ
線リソグラフィマスク、センサ、太陽電池及び複数の活
性層を有する集積回路の製造のための絶縁体上シリコン
基板、自立シリコン膜又は自立炭化シリコン膜である。
【０００８】薄い単結晶質フィルムの種々の製造方法
は、製造手順に関して欠点がある。
【０００９】ヘテロエピタキシ法は基板の種類によって
制限される。基板の格子パラメータは半導体のパラメー
タと精密には同一ではないので、フィルムは多数の結晶
上の欠陥を有する。更には、これらの基板は高価で、脆
く、且つ限定された寸法でのみ存在している。
【００１０】ＳＩＭＯＸ法は、非常に線量の多いイオン
注入を必要とし、この注入は非常に重く且つ複雑な注入
機械を要する。このような機械の出力は制限され、出力
を著しく増すことは困難であろう。
【００１１】薄片化法は、エッチストップの原理を使用
する場合を除いて、均質性及び品質の観点から競合的で
はない。不運なことに、このエッチストップの導入によ
り方法は複雑になり、場合によってはフィルムの使用が
制限され得る。
【００１２】従って、エッチストップがｎ型基板へのｐ
型ドーピングによって実施されるならば、フィルム内で
製造される任意の電子デバイスはフィルムのｐ型特性に
適合させねばならない。
【００１３】
【発明が解決しようとする課題】本発明は、選択される
半導体とは種類の異なった初期基板も、非常に多い注入
線量も、エッチストップをも必要とせずに前述した欠点
を克服し得、且つ更に均質で調整された厚さを有するフ
ィルムの製造を可能とする薄い半導体材料フィルムの製
造方法に関する。
【００１４】
【課題を解決するための手段】この薄いフィルムの製造
方法は、半導体材料が完全に単結晶質の場合にはその面
が主要結晶面と実質的に平行であり、材料が多結晶質の
場合にはその面が全ての粒子に対して同一指数の主要結
晶面に対して僅かに傾斜している半導体材料ウェーハ
を、以下の３つの段階：基板のバルクを構成する下方区
域６と薄いフィルムを構成する上方区域５とを前記ウェ
ーハの容積部内に限定する微小気泡の層３をイオンの平
均進入深さに近い深さの前記ウェーハの容積部に生じ
る、イオンにより行われる前記ウェーハ１の面４へのボ
ンバード２による注入の第１段階であって、イオンは水
素ガスイオン又は稀ガスイオンの中から選択され、注入
中のウェーハ温度は、注入イオンにより発生されたガス
が拡散により半導体から放出し得る温度より低く維持さ
れている第１段階と、前記ウェーハの平面４を、少なく
とも１つの剛性材料層からなる補剛材７と密着させる第
２段階と、イオンボンバード２が実施される温度よりも
高く、且つこの段階中に前記補剛材と前記ウェーハの平
面とは密着させたままで、ウェーハ１中の結晶の再配列
作用及び微小気泡内の圧力作用により薄いフィルム５と
基板６のバルクとを分離させるのに適した温度で前記ウ
ェーハ１と前記補剛材７とのアセンブリを熱処理する第
３段階とで処理することを包含することを特徴とする。
【００１５】従って、本発明は、格子を構成する全ての
粒子が半導体面に実質的に平行な主要結晶面（該面は全
ての半導体粒子に対して同一指数、例えば（１，０，
０）を有する）を有するならば、多結晶質半導体材料に
も適用される。半導体材料に関しては、ＺＭＲＳＯＩ
（ＺＭＲ＝帯−溶融−再結晶化）が挙げられ得る（参考
文献４を参照）。注入段階という用語は、１回の注入段
階と、異なる線量及び／又は異なるエネルギ及び／又は
異なるイオンでの注入の連続とを意味する。
【００１６】本発明方法の変形例として、１つ以上の材
料層を通じて半導体材料内へのイオン注入を実施するの
が有利であり得る。該“封入（ｅｎｃａｐｓｕｌａｔｉ
ｎｇ）”層は、イオンがこの材料層を貫通して、半導体
に進入するように選択される。例えば封入層は、より薄
い膜を製造するために半導体内へのイオンの進入を抑え
る手段としても、考えられ得る汚染から半導体を保護す
る手段としても、又は半導体面の物理化学的状態を調整
する手段としても使用され得る。ウェーハを構成する基
板がシリコンから製造されるときには、高温酸化シリコ
ンからなり且つ厚さが例えば２５〜５００ｎｍの封入層
を選択することが有利であり得る。これらの封入層は注
入段階後に保持され得るか又は除去され得る。
【００１７】本発明では、イオン注入が実施されるウェ
ーハの温度は作業中常に調整され、その結果温度は、注
入イオンによって発生されたガスが急速に拡散し且つ半
導体から放出する臨界温度よりも低く維持される。例え
ば該臨界温度はシリコンへの水素注入の場合で約５００
℃である。この温度を超えると、微小気泡が形成されな
いために、この方法は効果がなくなる。シリコンの場合
には、２０〜４５０℃の注入温度が好ましい。
【００１８】ウェーハ−補剛材アセンブリの熱処理とい
う第３段階中には、イオン注入によって発生された無秩
序に続いての結晶の再配列が生じる。共に第３段階の熱
処理によって生じる結晶の再配列とマクロな気泡を生じ
る気泡の凝集とによってフィルムと基板とが分離され
る。これらの気泡内の気体圧力の作用下では、半導体面
は高い応力を受ける。表面変形及び形成されたマクロ気
泡に相当する火ぶくれ状態の生成を避けることが所望さ
れるならば、これらの応力を補償することが重要であ
る。従って、火ぶくれ状態は、マクロな気泡がその最終
成長段階に達して互いに凝集する前に、小さく粉々にな
り得る。従って、連続する半導体フィルムの製造が所望
されるならば、熱処理段階中に生じる応力を補償するこ
とが必要である。本発明に基づけば、この補償は半導体
ウェーハ面と補剛材とを密着させることによって行われ
る。補剛材の機能は、ウェーハ面との接触及びその機械
特性により、マクロな気泡によって発生された応力が補
償されることである。従って、半導体フィルムは最終的
に壁開するまで、熱処理段階中常に平坦且つ損なわれな
いままであり得る。
【００１９】本発明の基づけば、補剛材の製造方法の選
択及び補剛材の種類はフィルムについて考えられる各適
用によって決まる。例えば意図される用途が絶縁体上シ
リコン基板の製造ならば、補剛材は、酸化物層又は窒化
物層のような少なくとも１つの誘電層によって被覆され
たシリコンウェーハからなることが有利であり得る。補
剛材の酸化物は、それからフィルムが製造されるべきウ
ェーハと密着されており、ウェーハは例えば酸化シリコ
ン封入層を任意に有している。
【００２０】補剛材について選択された厚さが適当であ
れば、即ち数マイクロメータ〜数十マイクロメータなら
ば、補剛材は蒸発、アトマイゼーション、プラズマ又は
光子によって任意に支援され得る化学蒸着のような方法
によってウェーハに結合され得るか又はウェーハ上に製
造され得る。
【００２１】密着という用語は、例えば静電圧力及び／
又は付着接触によって補剛材をウェーハ上に押圧するこ
とによって得られる接触を意味する。
【００２２】従って、本発明の補剛材は更に、補剛材及
びウェーハ両方に接着性物質を使用して、又は接着性物
質の使用が所望されない場合には補剛材と半導体ウェー
ハとの原子間結合を助けるために、結合されるべき表面
の少なくとも１つを先に製造し且つ任意に圧力の選択を
伴う熱処理及び／又は静電処理を実施することにより半
導体ウェーハに結合され得る。補剛材は静電圧力によっ
てもウェーハに付着され得る。
【００２３】自立膜の製造に関する適用については、補
剛材をフィルムから簡単且つ選択的に分離することがで
きるように補剛材の種類を選択することが適切である。
参考までに、単結晶質シリコン膜を製造するには、例え
ば酸化シリコン補剛材を選択することが可能であり、こ
の補剛材はそれから、プロセスの第３の熱処理段階の後
にフッ化水素酸浴中で除去される。
【００２４】本発明方法の特徴として、第２段階及び第
３段階での作業温度の選択は以下の要件に適合せねばな
らない。ウェーハ上に補剛材を設置するには、第３段階
の処理を開始させ得る温度を適用してはならない。この
ために本発明に基づけば、第３段階の熱処理の温度より
も低い温度でプロセスの第２段階を実施することが必要
である。本発明ではこの熱処理は、結晶再配列と気泡の
凝集とが効果的に生じる温度で実施されねばならない。
例えばシリコンの場合、結晶再配列と気泡の凝集とが適
切な動力学で生じ得るには約５００℃を超える温度が必
要である。
【００２５】本発明方法を実施するに当たって、ボンバ
ードによる注入に使用されるイオンは通常Ｈ+イオンで
あるが、この選択は限定的であるとみなすべきではな
い。従って本方法の原理は、分子水素イオン又はヘリウ
ム、ネオン、クリプトン及びキセノンのような稀ガスの
イオンを単独で若しくは組み合わせて使用して適用され
得る。本発明方法を工業的に適用するには、ＩＶ族半導
体が好ましく、例えばシリコン、ゲルマニウム、炭化シ
リコン及びシリコン−ゲルマニウム合金の使用が可能で
ある。
【００２６】
【実施例】添付図面を参照して本発明の非制限的実施例
を更に詳細に説明する。
【００２７】これから添付図面を参照して説明する実施
例は、Ｈ+イオン注入による単結晶質シリコンウェーハ
内での薄いフィルムの製造に関する。
【００２８】その表面が主要結晶面、例えば（１，０，
０）面に相当する単結晶質シリコンウェーハに１５０ｋ
ｅＶでＨ+イオン（プロトン）を注入すると、注入線量
が少ない（＜１０16ｃｍ-2）場合には、図１に示すよう
に深さＲｐで最大濃度を有する深さＰに対する水素濃度
プロフィールＣが得られる。シリコン内へのプロトン注
入の場合には、Ｒｐは約１．２５マイクロメータであ
る。
【００２９】約１０16ｃｍ-2の線量では、注入水素原子
は気泡を形成し始め、これらの気泡は表面に平行な面の
付近に配分されている。表面の面は主要結晶面に相当
し、また結果的に劈開面となる微小気泡面についても同
様である。
【００３０】１０16ｃｍ-2を超える（例えば５・１０16
ｃｍ-2）注入線量では、シリコンを２つの部分に劈開さ
せる気泡と、厚さが１．２マイクロメータの上方フィル
ム（薄いフィルム）と、基板のバックとの融合を加熱に
より開始させることが可能である。
【００３１】水素注入は有利な例である。何故ならば、
シリコン中でのイオンの制動プロセスは事実上イオン化
（電子制動）だからである。原子移動による原子核型制
動は飛程の最後にのみ生じる。それ故シリコンの表面層
では非常に僅かな欠陥だけが生じ、限定された厚さにわ
たり、気泡が深さＲｐ（最大濃度の深さ）の付近に集中
されている。これにより、穏当な注入線量（５・１０16
ｃｍ-2）で方法の必要な効率、及び表面層の分離後には
粗度の限定された表面を得ることが可能となる。
【００３２】本発明方法を使用すると、注入エネルギを
選択することにより広い厚さ範囲内で薄いフィルムの厚
さを選択することが可能となる。この特性は、注入イオ
ンの原子番号ｚが小さいだけに一層重要である。例えば
以下の表は、Ｈ+イオン（ｚ＝１）の異なる注入エネル
ギに対して得られ得るフィルムの厚さを示している。
【００３３】 Ｈ+イオンのエネルギ（ｋｅＶ） 10 50 100 150 200 500 1000 フィルムの厚さ（μｍ） 0.1 0.5 0.9 1.2 1.6 4.7 13.5 図２は封入層１０で任意に被覆された半導体ウェーハ１
を示し、該層は、主要結晶面に平行な平面４を通しての
Ｈ+イオンのイオンボンバード２を受けている。面４に
平行に微小気泡層３を認めることができる。層３及び面
４は薄いフィルム５を限定している。半導体基板６の他
の部分は、基板のバルクを構成している。
【００３４】図３は、半導体ウェーハ１の面４と密着さ
れた補剛材７を示している。本発明の有利な実施例で
は、材料へのイオン注入は高温酸化シリコン封入層１０
を通じて行われ、補剛材７は少なくとも１つの誘電層に
よって被覆されたシリコンウェーハからなっている。
【００３５】他の実施例は、半導体材料に補剛材を固定
するために静電圧力を使用している。この場合、例えば
５０００Ａ厚さの酸化シリコン層を有するシリコン補剛
材が選択される。ウェーハの平面は補剛材の酸化物と接
触させられ、ウェーハと補剛材との間には数十ボルトの
電位差が適用される。ここで得られる圧力は数１０5〜
１０6パスカルである。
【００３６】図４は、基板６のバルクから空間８によっ
て離隔された、補剛材７に結合されたフィルム５を示し
ている。
【００３７】本明細書は以下の資料を参照している。
【００３８】（１）ＳＩＭＯＸ ＳＯＩ ｆｏｒ Ｉｎ
ｔｅｇｒａｔｅｄ ＣｉｒｃｕｉｔＦａｂｒｉｃａｔｉ
ｏｎ ｂｙ Ｈｏｎ Ｗａｉ Ｌａｍ， ＩＥＥＥ Ｃ
ｉｒｃｕｉｔｓ ａｎｄ Ｄｅｖｉｃｅｓ Ｍａｇａｚ
ｉｎｅ， Ｊｕｌｙ １９８７． （２）Ｓｉｌｉｃｏｎ ｏｎ Ｉｎｓｕｌａｔｏｒ Ｗ
ａｆｅｒ Ｂｏｎｄｉｎｇ， Ｗａｆｅｒ Ｔｈｉｎｎ
ｉｎｇ， Ｔｅｃｈｎｏｌｏｇｉｃａｌ Ｅｖａｌｕａ
ｔｉｏｎｓ ｂｙ Ｈａｉｓｍａ， Ｓｐｉｅｒｉｎｇ
ｓ， Ｂｉｅｒｍａｎｎ ｅｔ Ｐａｌｓ， Ｊａｐａ
ｎｅｓｅ Ｊｏｕｒｎａｌ ｏｆ Ａｐｐｌｉｅｄ Ｐ
ｈｙｓｉｃｓ， ｖｏｌ．２８，ｎｏ．８，Ａｕｇｕｓ
ｔ １９８９． （３）Ｂｏｎｄｉｎｇ ｏｆ ｓｉｌｉｃｏｎ ｗａｆ
ｅｒｓ ｆｏｒ ｓｉｌｉｃｏｎ ｏｎ ｉｎｓｕｌａ
ｔｏｒ ｂｙ Ｍａｓｚａｒａ，Ｇｏｅｔｚ，Ｃａｖｉ
ｇｌｉａ ａｎｄ ＭｃＫｉｔｔｅｒｉｃｋ， Ｊｏｕ
ｒｎａｌ ｏｆＡｐｐｌｉｅｄ Ｐｈｙｓｉｃ ６４
（１０）１５ Ｎｏｖｅｍｂｅｒ １９８８． （４）Ｚｏｎｅ ｍｅｌｔｉｎｇ ｒｅｃｒｙｓｔａｌ
ｌｉｚａｔｉｏｎ ｓｉｌｉｃｏｎ ｏｎ ｉｎｓｕｌ
ａｔｏｒ ｔｅｃｈｎｏｌｏｇｙ ｂｙ ＢｏｒＹｅｕ
Ｔｓａｕｒ， ＩＥＥＥ Ｃｉｒｃｕｉｔｓ ａｎｄ
Ｄｅｖｉｃｅｓ Ｍａｇａｚｉｎｅ， Ｊｕｌｙ １
９８７． （５）１９８６ ＩＥＥＥ ＳＯＳ／ＳＯＩ Ｔｅｃｈ
ｎｏｌｏｇｙ Ｗｏｒｋｓｈｏｐ， Ｓｅｐｔｅｍｂｅ
ｒ ３０−Ｏｃｔｏｂｅｒ ２， １９８６，Ｓｏｕｔ
ｈ Ｓｅａｓ ｐｌａｎｔａｔｉｏｎ ｒｅｓｏｒｔ
ａｎｄ ｙａｃｈｔ Ｈａｒｂｏｕｒ， Ｃａｐｔｉｖ
ａ Ｉｓｌａｎｄ， Ｆｌｏｒｉｄａ．
【図面の簡単な説明】
【図１】進入深さに対する水素イオンの濃度プロフィー
ルを示すグラフである。
【図２】Ｈ+イオンのボンバードにさらされ且つ注入粒
子によって生じた微小気泡層が内部に出現した、単結晶
質フィルム源として本発明で使用される単結晶質半導体
ウェーハの断面図である。
【図３】補剛材で被覆された図２の半導体ウェーハを示
す図である。
【図４】熱処理段階後にフィルムと基板バルクとの間に
劈開が生じたときの、図３の半導体ウェーハと補剛材と
のアセンブリを示す図である。
【符号の説明】
１ ウェーハ ４ 平面 ５ フィルム ６ 基板 ７ 補剛材
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 27/12 Ｅ 8728−4Ｍ 31/04 7376−4Ｍ Ｈ０１Ｌ 31/04 Ｘ

Claims (9)

    【特許請求の範囲】
  1. 【請求項１】 薄い半導体材料フィルムの製造方法であ
    って、半導体材料が完全に単結晶質の場合にはその面が
    主要結晶面と実質的に平行であり、材料が多結晶質の場
    合にはその面が全ての粒子に対して同一指数の主要結晶
    面に対して僅かに傾斜している半導体材料ウェーハを、
    以下の３つの段階：基板のバルクを構成する下方区域と
    薄いフィルムを構成する上方区域とを前記ウェーハの容
    積部内に限定する微小気泡の層をイオンの平均進入深さ
    に近い深さの前記ウェーハの容積部に生じる、イオンに
    より行われる前記ウェーハの面へのボンバードによる注
    入の第１段階であって、イオンは水素ガスイオン又は稀
    ガスイオンの中から選択され、注入中のウェーハ温度
    は、注入イオンにより発生されたガスが拡散により半導
    体から放出し得る温度よりも低く維持されている第１段
    階と、 前記ウェーハの平面を、少なくとも１つの剛性材料層か
    らなる補剛材と密着させる第２段階と、 イオンボンバードが実施される温度よりも高く、且つこ
    の段階中に前記補剛材と前記ウェーハの平面とは密着さ
    せたままで、ウェーハ中の結晶の再配列作用及び微小気
    泡内の圧力作用により薄いフィルムと基板のバルクとを
    分離させるのに適した温度で前記ウェーハと前記補剛材
    とのアセンブリを熱処理する第３段階とで処理すること
    を包含することを特徴とする方法。
  2. 【請求項２】 半導体材料内へのイオンの注入段階が、
    イオンによって横断され得るような種類及び厚さの１つ
    以上の材料層を通じて実施されることを特徴とする請求
    項１に記載の薄いフィルムの製造方法。
  3. 【請求項３】 半導体がＩＶ族の共有結合を有すること
    を特徴とする請求項１に記載の薄いフィルムの製造方
    法。
  4. 【請求項４】 半導体がシリコンであり、注入イオンが
    水素ガスイオンであり、注入ガスの温度が２０〜４５０
    ℃であり、且つ第３の熱処理段階の温度が５００℃を超
    えることを特徴とする請求項１から３のいずれか一項に
    記載の薄いフィルムの製造方法。
  5. 【請求項５】 注入が封入高温酸化シリコン層を通じて
    実施され、且つ補剛材が少なくとも１つの酸化シリコン
    層によって被覆されたシリコンウェーハであることを特
    徴とする請求項２に記載の薄いフィルムの製造方法。
  6. 【請求項６】 前記ウェーハの平面を補剛材と密着させ
    る第２段階が、静電圧力を加えることにより実施される
    ことを特徴とする請求項１に記載の薄いフィルムの製造
    方法。
  7. 【請求項７】 補剛材が、蒸発、プラズマ若しくは光子
    により任意に支援される化学蒸着、又はアトマイゼーシ
    ョンからなる群の中から選択された１つ以上の方法によ
    って付着されることを特徴とする請求項１に記載の薄い
    フィルムの製造方法。
  8. 【請求項８】 補剛材が接着性物質によって前記ウェー
    ハに結合されることを特徴とする請求項１に記載の薄い
    フィルムの製造方法。
  9. 【請求項９】 補剛材が原子間結合を促進する処理によ
    ってウェーハに付着させられることを特徴とする請求項
    １に記載の薄いフィルムの製造方法。
JP4246594A 1991-09-18 1992-09-16 半導体材料薄膜の製造方法 Expired - Lifetime JP3048201B2 (ja)

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FR9111491 1991-09-18
FR9111491A FR2681472B1 (fr) 1991-09-18 1991-09-18 Procede de fabrication de films minces de materiau semiconducteur.

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US6239004B1 (en) 1997-08-29 2001-05-29 Shin-Etsu Handotai Co., Ltd. Method of forming oxide film on an SOI layer and method of fabricating a bonded wafer
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US6251754B1 (en) 1997-05-09 2001-06-26 Denso Corporation Semiconductor substrate manufacturing method
US6284629B1 (en) 1998-07-07 2001-09-04 Shin-Etsu Handotai Co., Ltd. Method of fabricating an SOI wafer and SOI wafer fabricated by the method
US6284628B1 (en) 1998-04-23 2001-09-04 Shin-Etsu Handotai Co., Ltd. Method of recycling a delaminated wafer and a silicon wafer used for the recycling
US6312797B1 (en) 1998-07-10 2001-11-06 Shin-Etsu Handotai Co., Ltd. Method for manufacturing bonded wafer and bonded wafer
JP2001525991A (ja) * 1997-05-12 2001-12-11 シリコン・ジェネシス・コーポレーション 制御された劈開プロセス
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US5374564A (en) 1994-12-20
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