FR2867307B1 - Traitement thermique apres detachement smart-cut - Google Patents
Traitement thermique apres detachement smart-cutInfo
- Publication number
- FR2867307B1 FR2867307B1 FR0402340A FR0402340A FR2867307B1 FR 2867307 B1 FR2867307 B1 FR 2867307B1 FR 0402340 A FR0402340 A FR 0402340A FR 0402340 A FR0402340 A FR 0402340A FR 2867307 B1 FR2867307 B1 FR 2867307B1
- Authority
- FR
- France
- Prior art keywords
- detachment
- smart
- cut
- heat treatment
- treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000010438 heat treatment Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Recrystallisation Techniques (AREA)
Priority Applications (21)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0402340A FR2867307B1 (fr) | 2004-03-05 | 2004-03-05 | Traitement thermique apres detachement smart-cut |
FR0409980A FR2867310B1 (fr) | 2004-03-05 | 2004-09-21 | Technique d'amelioration de la qualite d'une couche mince prelevee |
US11/059,122 US7276428B2 (en) | 2004-03-05 | 2005-02-16 | Methods for forming a semiconductor structure |
US11/058,992 US7285495B2 (en) | 2004-03-05 | 2005-02-16 | Methods for thermally treating a semiconductor layer |
KR1020067020815A KR100860271B1 (ko) | 2004-03-05 | 2005-03-07 | 분기되는 박층의 품질 향상법 |
EP05737043A EP1733423A1 (fr) | 2004-03-05 | 2005-03-07 | TRAITEMENT THERMIQUE D’AMELIORATION DE LA QUALITE D’UNE COUCHE MINCE PRELEVEE |
KR1020067020808A KR100910687B1 (ko) | 2004-03-05 | 2005-03-07 | 스마트 컷 분리 후 열처리 |
JP2007501320A JP4876068B2 (ja) | 2004-03-05 | 2005-03-07 | スマートカット(登録商標)剥離後の熱処理方法 |
PCT/FR2005/000541 WO2005086226A1 (fr) | 2004-03-05 | 2005-03-07 | Traitement thermique d’amelioration de la qualite d’une couche mince prelevee |
EP05737045A EP1721333A1 (fr) | 2004-03-05 | 2005-03-07 | Technique d'amelioration de la qualite d'une couche mince prelevee |
PCT/FR2005/000543 WO2005086228A1 (fr) | 2004-03-05 | 2005-03-07 | Traitement thermique apres detachement smart-cut |
CN2005800141634A CN1950937B (zh) | 2004-03-05 | 2005-03-07 | 用于改善剥离薄层的质量的方法 |
CNA2005800071260A CN1930674A (zh) | 2004-03-05 | 2005-03-07 | 用于改进所剥离薄层质量的热处理 |
PCT/FR2005/000542 WO2005086227A1 (fr) | 2004-03-05 | 2005-03-07 | Technique d’amelioration de la qualite d’une couche mince prelevee |
CN200580014164A CN100592493C (zh) | 2004-03-05 | 2005-03-07 | 智能剥离分开后的热处理 |
EP05737041A EP1726039A1 (fr) | 2004-03-05 | 2005-03-07 | Traitement thermique apres detachement smart-cut |
JP2007501318A JP2007526644A (ja) | 2004-03-05 | 2005-03-07 | 採取薄膜の品質改善熱処理方法 |
JP2007501319A JP4876067B2 (ja) | 2004-03-05 | 2005-03-07 | 採取薄膜の品質改善処理方法 |
US11/179,713 US7449394B2 (en) | 2004-03-05 | 2005-07-11 | Atomic implantation and thermal treatment of a semiconductor layer |
US11/233,318 US20060014363A1 (en) | 2004-03-05 | 2005-09-21 | Thermal treatment of a semiconductor layer |
US11/357,883 US7282449B2 (en) | 2004-03-05 | 2006-02-17 | Thermal treatment of a semiconductor layer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0402340A FR2867307B1 (fr) | 2004-03-05 | 2004-03-05 | Traitement thermique apres detachement smart-cut |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2867307A1 FR2867307A1 (fr) | 2005-09-09 |
FR2867307B1 true FR2867307B1 (fr) | 2006-05-26 |
Family
ID=34855097
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0402340A Expired - Lifetime FR2867307B1 (fr) | 2004-03-05 | 2004-03-05 | Traitement thermique apres detachement smart-cut |
Country Status (7)
Country | Link |
---|---|
US (1) | US7285495B2 (fr) |
EP (1) | EP1726039A1 (fr) |
JP (1) | JP4876068B2 (fr) |
KR (1) | KR100910687B1 (fr) |
CN (3) | CN1950937B (fr) |
FR (1) | FR2867307B1 (fr) |
WO (1) | WO2005086228A1 (fr) |
Families Citing this family (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6717213B2 (en) * | 2001-06-29 | 2004-04-06 | Intel Corporation | Creation of high mobility channels in thin-body SOI devices |
FR2858462B1 (fr) * | 2003-07-29 | 2005-12-09 | Soitec Silicon On Insulator | Procede d'obtention d'une couche mince de qualite accrue par co-implantation et recuit thermique |
KR20060030911A (ko) * | 2003-07-29 | 2006-04-11 | 에스. 오. 이. 떼끄 씰리꽁 오 냉쉴라또흐 떼끄놀로지 | 공동-임플란트 및 열적 아닐링에 의한 개선된 품질의 박층제조방법 |
KR100956711B1 (ko) * | 2003-12-16 | 2010-05-06 | 인터내셔널 비지네스 머신즈 코포레이션 | 실리콘-온-절연체 웨이퍼의 컨투어화 된 절연체 층 및 이의제조 프로세스 |
FR2898431B1 (fr) * | 2006-03-13 | 2008-07-25 | Soitec Silicon On Insulator | Procede de fabrication de film mince |
US20070281440A1 (en) * | 2006-05-31 | 2007-12-06 | Jeffrey Scott Cites | Producing SOI structure using ion shower |
FR2914495B1 (fr) | 2007-03-29 | 2009-10-02 | Soitec Silicon On Insulator | Amelioration de la qualite d'une couche mince par recuit thermique haute temperature. |
FR2923079B1 (fr) * | 2007-10-26 | 2017-10-27 | S O I Tec Silicon On Insulator Tech | Substrats soi avec couche fine isolante enterree |
CN101855703B (zh) * | 2007-12-27 | 2013-03-13 | 夏普株式会社 | 半导体装置的制造方法 |
JP5303957B2 (ja) * | 2008-02-20 | 2013-10-02 | 株式会社デンソー | グラフェン基板及びその製造方法 |
US8133800B2 (en) * | 2008-08-29 | 2012-03-13 | Silicon Genesis Corporation | Free-standing thickness of single crystal material and method having carrier lifetimes |
JP5493343B2 (ja) | 2008-12-04 | 2014-05-14 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
US20110207306A1 (en) * | 2010-02-22 | 2011-08-25 | Sarko Cherekdjian | Semiconductor structure made using improved ion implantation process |
US8196546B1 (en) | 2010-11-19 | 2012-06-12 | Corning Incorporated | Semiconductor structure made using improved multiple ion implantation process |
US8558195B2 (en) | 2010-11-19 | 2013-10-15 | Corning Incorporated | Semiconductor structure made using improved pseudo-simultaneous multiple ion implantation process |
US8008175B1 (en) | 2010-11-19 | 2011-08-30 | Coring Incorporated | Semiconductor structure made using improved simultaneous multiple ion implantation process |
CN102184882A (zh) * | 2011-04-07 | 2011-09-14 | 中国科学院微电子研究所 | 一种形成复合功能材料结构的方法 |
FR2978604B1 (fr) * | 2011-07-28 | 2018-09-14 | Soitec | Procede de guerison de defauts dans une couche semi-conductrice |
FR2980916B1 (fr) * | 2011-10-03 | 2014-03-28 | Soitec Silicon On Insulator | Procede de fabrication d'une structure de type silicium sur isolant |
FR2982071B1 (fr) | 2011-10-27 | 2014-05-16 | Commissariat Energie Atomique | Procede de lissage d'une surface par traitement thermique |
CN103165511B (zh) * | 2011-12-14 | 2015-07-22 | 中国科学院上海微系统与信息技术研究所 | 一种制备goi的方法 |
CN103165512A (zh) * | 2011-12-14 | 2013-06-19 | 中国科学院上海微系统与信息技术研究所 | 一种超薄绝缘体上半导体材料及其制备方法 |
CN105140171B (zh) * | 2015-08-26 | 2018-06-29 | 中国科学院上海微系统与信息技术研究所 | 一种绝缘体上材料的制备方法 |
CN105957831A (zh) * | 2016-07-06 | 2016-09-21 | 中国科学院上海微系统与信息技术研究所 | 一种用于制造支撑衬底上的单晶材料薄层结构的方法 |
CN107195534B (zh) * | 2017-05-24 | 2021-04-13 | 中国科学院上海微系统与信息技术研究所 | Ge复合衬底、衬底外延结构及其制备方法 |
CN109427538B (zh) * | 2017-08-24 | 2021-04-02 | 中国科学院上海微系统与信息技术研究所 | 一种异质结构的制备方法 |
WO2020138218A1 (fr) | 2018-12-28 | 2020-07-02 | 富士電機株式会社 | Dispositif à semi-conducteur et son procédé de production |
CN111722321A (zh) * | 2020-01-19 | 2020-09-29 | 中国科学院上海微系统与信息技术研究所 | 一种光膜转换器及其制备方法 |
FR3108440A1 (fr) * | 2020-03-23 | 2021-09-24 | Soitec | Procédé de préparation d’une couche mince |
CN111834520B (zh) * | 2020-06-29 | 2021-08-27 | 中国科学院上海微系统与信息技术研究所 | 一种表面均匀性优化的压电单晶薄膜制备方法 |
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US4462847A (en) * | 1982-06-21 | 1984-07-31 | Texas Instruments Incorporated | Fabrication of dielectrically isolated microelectronic semiconductor circuits utilizing selective growth by low pressure vapor deposition |
US4604304A (en) * | 1985-07-03 | 1986-08-05 | Rca Corporation | Process of producing thick layers of silicon dioxide |
US4722912A (en) * | 1986-04-28 | 1988-02-02 | Rca Corporation | Method of forming a semiconductor structure |
FR2681472B1 (fr) * | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
JPH06318588A (ja) | 1993-03-11 | 1994-11-15 | Nec Corp | 半導体装置の製造方法 |
US6155909A (en) * | 1997-05-12 | 2000-12-05 | Silicon Genesis Corporation | Controlled cleavage system using pressurized fluid |
US5882987A (en) * | 1997-08-26 | 1999-03-16 | International Business Machines Corporation | Smart-cut process for the production of thin semiconductor material films |
JP3412470B2 (ja) * | 1997-09-04 | 2003-06-03 | 三菱住友シリコン株式会社 | Soi基板の製造方法 |
FR2773261B1 (fr) * | 1997-12-30 | 2000-01-28 | Commissariat Energie Atomique | Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions |
JP3582566B2 (ja) * | 1997-12-22 | 2004-10-27 | 三菱住友シリコン株式会社 | Soi基板の製造方法 |
FR2774510B1 (fr) * | 1998-02-02 | 2001-10-26 | Soitec Silicon On Insulator | Procede de traitement de substrats, notamment semi-conducteurs |
CN1241803A (zh) * | 1998-05-15 | 2000-01-19 | 佳能株式会社 | 半导体衬底、半导体薄膜以及多层结构的制造工艺 |
JP3697106B2 (ja) * | 1998-05-15 | 2005-09-21 | キヤノン株式会社 | 半導体基板の作製方法及び半導体薄膜の作製方法 |
JP3358550B2 (ja) | 1998-07-07 | 2002-12-24 | 信越半導体株式会社 | Soiウエーハの製造方法ならびにこの方法で製造されるsoiウエーハ |
JP4379943B2 (ja) * | 1999-04-07 | 2009-12-09 | 株式会社デンソー | 半導体基板の製造方法および半導体基板製造装置 |
US6352942B1 (en) * | 1999-06-25 | 2002-03-05 | Massachusetts Institute Of Technology | Oxidation of silicon on germanium |
EP1939932A1 (fr) * | 1999-08-10 | 2008-07-02 | Silicon Genesis Corporation | Substrat avec une couche de séparation contrainte en silicium-germanium |
DE10031388A1 (de) * | 2000-07-03 | 2002-01-17 | Bundesdruckerei Gmbh | Handsensor für die Echtheitserkennung von Signets auf Dokumenten |
DE60125952T2 (de) * | 2000-08-16 | 2007-08-02 | Massachusetts Institute Of Technology, Cambridge | Verfahren für die herstellung eines halbleiterartikels mittels graduellem epitaktischen wachsen |
US6448152B1 (en) * | 2001-02-20 | 2002-09-10 | Silicon Genesis Corporation | Method and system for generating a plurality of donor wafers and handle wafers prior to an order being placed by a customer |
US6603156B2 (en) * | 2001-03-31 | 2003-08-05 | International Business Machines Corporation | Strained silicon on insulator structures |
US7238622B2 (en) * | 2001-04-17 | 2007-07-03 | California Institute Of Technology | Wafer bonded virtual substrate and method for forming the same |
US6593625B2 (en) * | 2001-06-12 | 2003-07-15 | International Business Machines Corporation | Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing |
US6717213B2 (en) * | 2001-06-29 | 2004-04-06 | Intel Corporation | Creation of high mobility channels in thin-body SOI devices |
US6649492B2 (en) * | 2002-02-11 | 2003-11-18 | International Business Machines Corporation | Strained Si based layer made by UHV-CVD, and devices therein |
US6562703B1 (en) * | 2002-03-13 | 2003-05-13 | Sharp Laboratories Of America, Inc. | Molecular hydrogen implantation method for forming a relaxed silicon germanium layer with high germanium content |
FR2839385B1 (fr) | 2002-05-02 | 2004-07-23 | Soitec Silicon On Insulator | Procede de decollement de couches de materiau |
US6995430B2 (en) * | 2002-06-07 | 2006-02-07 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures |
WO2003105189A2 (fr) | 2002-06-07 | 2003-12-18 | Amberwave Systems Corporation | Structures de dispositif a semi-conducteurs contraints sur isolant |
US7307273B2 (en) * | 2002-06-07 | 2007-12-11 | Amberwave Systems Corporation | Control of strain in device layers by selective relaxation |
US7074623B2 (en) * | 2002-06-07 | 2006-07-11 | Amberwave Systems Corporation | Methods of forming strained-semiconductor-on-insulator finFET device structures |
US7335545B2 (en) * | 2002-06-07 | 2008-02-26 | Amberwave Systems Corporation | Control of strain in device layers by prevention of relaxation |
US20030227057A1 (en) * | 2002-06-07 | 2003-12-11 | Lochtefeld Anthony J. | Strained-semiconductor-on-insulator device structures |
US7018910B2 (en) * | 2002-07-09 | 2006-03-28 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Transfer of a thin layer from a wafer comprising a buffer layer |
FR2842349B1 (fr) | 2002-07-09 | 2005-02-18 | Transfert d'une couche mince a partir d'une plaquette comprenant une couche tampon | |
US6953736B2 (en) * | 2002-07-09 | 2005-10-11 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Process for transferring a layer of strained semiconductor material |
FR2842350B1 (fr) | 2002-07-09 | 2005-05-13 | Procede de transfert d'une couche de materiau semiconducteur contraint | |
WO2004009861A2 (fr) | 2002-07-19 | 2004-01-29 | Asm America, Inc. | Procede de formation de couches de compose au silicium de qualite ultra-haute |
AU2003270040A1 (en) * | 2002-08-29 | 2004-03-19 | Massachusetts Institute Of Technology | Fabrication method for a monocrystalline semiconductor layer on a substrate |
FR2844634B1 (fr) | 2002-09-18 | 2005-05-27 | Soitec Silicon On Insulator | Formation d'une couche utile relaxee a partir d'une plaquette sans couche tampon |
US6911379B2 (en) * | 2003-03-05 | 2005-06-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming strained silicon on insulator substrate |
US20060014363A1 (en) * | 2004-03-05 | 2006-01-19 | Nicolas Daval | Thermal treatment of a semiconductor layer |
RU2625370C2 (ru) * | 2011-12-07 | 2017-07-13 | Конинклейке Филипс Н.В. | Способ и устройство для обнаружения движения лифта |
-
2004
- 2004-03-05 FR FR0402340A patent/FR2867307B1/fr not_active Expired - Lifetime
-
2005
- 2005-02-16 US US11/058,992 patent/US7285495B2/en active Active
- 2005-03-07 KR KR1020067020808A patent/KR100910687B1/ko active IP Right Grant
- 2005-03-07 CN CN2005800141634A patent/CN1950937B/zh active Active
- 2005-03-07 WO PCT/FR2005/000543 patent/WO2005086228A1/fr active Application Filing
- 2005-03-07 EP EP05737041A patent/EP1726039A1/fr not_active Withdrawn
- 2005-03-07 JP JP2007501320A patent/JP4876068B2/ja active Active
- 2005-03-07 CN CN200580014164A patent/CN100592493C/zh active Active
- 2005-03-07 CN CNA2005800071260A patent/CN1930674A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
KR100910687B1 (ko) | 2009-08-04 |
CN1930674A (zh) | 2007-03-14 |
KR20070088279A (ko) | 2007-08-29 |
CN1950938A (zh) | 2007-04-18 |
CN1950937A (zh) | 2007-04-18 |
EP1726039A1 (fr) | 2006-11-29 |
CN1950937B (zh) | 2010-06-16 |
JP4876068B2 (ja) | 2012-02-15 |
US7285495B2 (en) | 2007-10-23 |
JP2007526646A (ja) | 2007-09-13 |
WO2005086228A1 (fr) | 2005-09-15 |
CN100592493C (zh) | 2010-02-24 |
US20050196936A1 (en) | 2005-09-08 |
FR2867307A1 (fr) | 2005-09-09 |
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