JP2005033172A - 半導体装置およびその製造方法ならびに電子デバイス - Google Patents
半導体装置およびその製造方法ならびに電子デバイス Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
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- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
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- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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Abstract
【解決手段】 薄膜トランジスタ1において、絶縁性基板2上のゲート電極3の上に、ゲート絶縁層4を介して半導体層5が積層され、その上にソース電極6とドレイン電極7とが形成され、さらにその上を覆う保護層8が形成されて、半導体層5を雰囲気から隔絶している。半導体層5(活性層)は、例えばV族元素が添加されたZnOの多結晶状態の半導体を用いて形成される。ZnOは、保護層8により表面準位が減少し、内部への空乏層が拡がりが解消されるので、本来の抵抗値を示すn型半導体となり、自由電子が過剰な状態になる。添加された元素はZnOに対してアクセプタ不純物として働くので、過剰な自由電子が減少する。これにより、過剰な自由電子を排除するためのゲート電圧が低下するので、しきい値電圧が0V付近となる。
【選択図】 図1
Description
本発明の第1の実施形態について、図1ないし図5に基づいて説明すれば、以下の通りである。
本発明の第2の実施形態について、図6ないし図8に基づいて説明すれば、以下の通りである。
本発明の第3の実施形態について、図9ないし図11に基づいて説明すれば、以下の通りである。
本発明の第4の実施形態について図1、図2、図3、図5、図6、図7、図10、図17および図18に基づいて説明すれば、以下の通りである。なお、本実施の形態において、前述の実施の形態1ないし3における構成要素と同等の機能を有する構成要素については、同じ符号を付記してその説明を省略する。
本発明の第5の実施形態について、図12および図13に基づいて説明すれば、以下の通りである。なお、本実施の形態において、前述の実施の形態1ないし4における構成要素と同等の機能を有する構成要素については、同じ符号を付記してその説明を省略する。
2,12,22 絶縁性基板
3,18,29 ゲート電極
4,17 ゲート絶縁層(隔絶層)
5,16,26 半導体層(活性層)
6,14,24 ソース電極(隔絶層)
7,15,25 ドレイン電極(隔絶層)
8,19 保護層(隔絶層)
13,23 下地絶縁層(隔絶層)
27 第1のゲート絶縁層(隔絶層)
28 第2のゲート絶縁層(隔絶層)
37 絵素
37a 絵素電極
105 半導体層(活性層)
SLj ソースライン
GLi ゲートライン
T トランジスタ(スイッチング素子)
Claims (16)
- ZnOまたはMgxZn1−xOの多結晶状態、アモルファス状態または多結晶状態とアモルファス状態とが混在する状態である半導体から成り、I族、III族、IV族、V族またはVII族の元素が添加されている活性層と、
前記活性層を、前記活性層において可動電荷が移動する領域が雰囲気の影響を受けない範囲で雰囲気から隔絶する隔絶体とを備えていることを特徴とする半導体装置。 - 前記元素が、窒素、リン、砒素、アンチモンまたはこれらのうち2種類以上であることを特徴とする請求項1に記載の半導体装置。
- 前記元素が、窒素、リン、砒素、アンチモンまたはこれらのうち2種類以上と水素とであることを特徴とする請求項1に記載の半導体装置。
- 前記活性層は、窒素、一酸化二窒素、一酸化窒素または二酸化窒素のうち1種類以上と、水蒸気、過酸化水素、アンモニアまたはこれらのうち1種類以上とを含む雰囲気中で形成されたことを特徴とする請求項3に記載の半導体装置。
- 請求項3に記載の半導体装置を製造する製造方法であって、
前記活性層を、窒素、一酸化二窒素、一酸化窒素または二酸化窒素のうち1種類以上と、水蒸気、過酸化水素、アンモニアまたはこれらのうち1種類以上とを含む雰囲気中で形成することを特徴とする半導体装置の製造方法。 - 前記隔絶体が異なる隔絶層から成ることを特徴とする請求項1、2、3または4に記載の半導体装置。
- 前記隔絶層のうち少なくとも1つが、SiO2、Al2O3、AlN、MgO、Ta2O5、TiO2、ZrO2、stab−ZrO2、CeO2、K2O、Li2O、Na2O、Rb2O、In2O3、La2O3、Sc2O3、Y2O3、KNbO3、KTaO3、BaTiO3、CaSnO3、CaZrO3、CdSnO3、SrHfO3、SrSnO3、SrTiO3、YScO3、CaHfO3、MgCeO3、SrCeO3、BaCeO3、SrZrO3、BaZrO3、LiGaO2、LiGaO2の混晶系(Li1−(x+y)NaxKy)(Ga1−zAlz)O2またはこれらのうち少なくとも2つを含む固溶体により形成されていることを特徴とする請求項6に記載の半導体装置。
- 前記活性層に接続される2つの電極以外で前記活性層と界面を形成する前記隔絶層のうち、前記活性層における可動電荷の移動を制御する制御電極と前記活性層との間を絶縁する隔絶層と界面を形成する領域以外で前記活性層と界面を形成する前記隔絶層が、SiO2、Al2O3、AlN、MgO、Ta2O5、TiO2、ZrO2、stab−ZrO2、CeO2、K2O、Li2O、Na2O、Rb2O、In2O3、La2O3、Sc2O3、Y2O3、KNbO3、KTaO3、BaTiO3、CaSnO3、CaZrO3、CdSnO3、SrHfO3、SrSnO3、SrTiO3、YScO3、CaHfO3、MgCeO3、SrCeO3、BaCeO3、SrZrO3、BaZrO3、LiGaO2、LiGaO2の混晶系(Li1−(x+y)NaxKy)(Ga1−zAlz)O2またはこれらのうち少なくとも2つを含む固溶体により形成されていることを特徴とする請求項7に記載の半導体装置。
- 前記隔絶層のうち少なくとも1つが樹脂により形成されていることを特徴とする請求項6に記載の半導体装置。
- 前記活性層に接続される2つの電極以外で前記活性層と界面を形成する前記隔絶層のうち、前記活性層における可動電荷の移動を制御する制御電極と前記活性層との間を絶縁する隔絶層と界面を形成する領域以外で前記活性層と界面を形成する前記隔絶層が樹脂により形成されていることを特徴とする請求項9に記載の半導体装置。
- 前記活性層における可動電荷の移動を制御するゲート電極と、
前記活性層と前記ゲート電極との間を絶縁する前記隔絶層としてのゲート絶縁層と、
前記活性層に接続されるソース電極およびドレイン電極とを備え、
前記隔絶層のうち少なくとも1つが、SiO2、Al2O3、AlN、MgO、Ta2O5、TiO2、ZrO2、stab−ZrO2、CeO2、K2O、Li2O、Na2O、Rb2O、In2O3、La2O3、Sc2O3、Y2O3、KNbO3、KTaO3、BaTiO3、CaSnO3、CaZrO3、CdSnO3、SrHfO3、SrSnO3、SrTiO3、YScO3、CaHfO3、MgCeO3、SrCeO3、BaCeO3、SrZrO3、BaZrO3、LiGaO2、LiGaO2の混晶系(Li1−(x+y)NaxKy)(Ga1−zAlz)O2またはこれらのうち少なくとも2つを含む固溶体により形成されていることを特徴とする請求項6に記載の半導体装置。 - 前記ゲート電極および前記ドレイン電極以外で前記活性層と界面を形成する前記隔絶層のうち、前記ゲート絶縁層と界面を形成する領域以外で前記活性層と界面を形成する前記隔絶層が、SiO2、Al2O3、AlN、MgO、Ta2O5、TiO2、ZrO2、stab−ZrO2、CeO2、K2O、Li2O、Na2O、Rb2O、In2O3、La2O3、Sc2O3、Y2O3、KNbO3、KTaO3、BaTiO3、CaSnO3、CaZrO3、CdSnO3、SrHfO3、SrSnO3、SrTiO3、YScO3、CaHfO3、MgCeO3、SrCeO3、BaCeO3、SrZrO3、BaZrO3、LiGaO2、LiGaO2の混晶系(Li1−(x+y)NaxKy)(Ga1−zAlz)O2またはこれらのうち少なくとも2つを含む固溶体により形成されていることを特徴とする請求項11に記載の半導体装置。
- 前記活性層における可動電荷の移動を制御するゲート電極と、
前記活性層と前記ゲート電極との間を絶縁する前記隔絶層としてのゲート絶縁層と、
前記活性層に接続されるソース電極およびドレイン電極とを備え、
前記隔絶層のうち少なくとも1つが樹脂により形成されていることを特徴とする請求項6に記載の半導体装置。 - 前記ゲート電極および前記ドレイン電極以外で前記活性層と界面を形成する前記隔絶層のうち、前記ゲート絶縁層と界面を形成する領域以外で前記活性層と界面を形成する前記隔絶層が樹脂により形成されていることを特徴とする請求項13に記載の半導体装置。
- 請求項1ないし4および6ないし14のいずれか1項に記載の半導体装置をスイッチング素子として備えた電子デバイス。
- 前記スイッチング素子が、絵素電極への画像信号の書き込みまたは読み出しのために絵素電極に接続されていることを特徴とする請求項15に記載の電子デバイス。
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JP2004079273A JP4108633B2 (ja) | 2003-06-20 | 2004-03-18 | 薄膜トランジスタおよびその製造方法ならびに電子デバイス |
CN201010239835.4A CN101916785B (zh) | 2003-06-20 | 2004-06-14 | 半导体装置及其制造方法以及电子设备 |
PCT/JP2004/008322 WO2004114391A1 (ja) | 2003-06-20 | 2004-06-14 | 半導体装置およびその製造方法ならびに電子デバイス |
KR1020057024366A KR100745254B1 (ko) | 2003-06-20 | 2004-06-14 | 반도체 장치 및 그 제조 방법 및 전자 디바이스 |
US10/560,907 US8093589B2 (en) | 2003-06-20 | 2004-06-14 | Semiconductor device with an active layer containing zinc oxide, manufacturing method, and electronic device |
TW093117707A TWI243480B (en) | 2003-06-20 | 2004-06-18 | Semiconductor device, fabrication method thereof, and electronic device |
US13/072,910 US20110175090A1 (en) | 2003-06-20 | 2011-03-28 | Semiconductor device, manufacturing method thereof, and electronic device |
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US20110175090A1 (en) | 2011-07-21 |
US20060244107A1 (en) | 2006-11-02 |
KR20060073539A (ko) | 2006-06-28 |
US8093589B2 (en) | 2012-01-10 |
KR100745254B1 (ko) | 2007-08-01 |
CN101916785B (zh) | 2015-08-05 |
CN101916785A (zh) | 2010-12-15 |
TWI243480B (en) | 2005-11-11 |
US20120132908A1 (en) | 2012-05-31 |
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