JP2008504745A - Rfフロントエンド集積回路 - Google Patents
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Abstract
Description
図1は、RF電力増幅器(PA)のブロック図である。表されたRF電力増幅器は、ドライバ素子ブロック200でデバイスのバイアスを変化させること、及び/又は他のブロックの細部を変更することにより、図1に表されたRF電力増幅器がA、B、C、E、F級のいずれかのクラスの増幅器、即ち、i級増幅器としてここで更に説明される増幅器で動作することを可能にする点で、極めて一般的である。図2〜5は、夫々、図1で示されるブロックの1つを実施するための例となる回路を示す。
図2は、駆動出力ノード106と回路共通電位104との間の導通を制御するために、図1のRF電力増幅器内のドライバ素子ブロック200に使用されうる積層FET(スタックされたFET)回路の簡単化された回路図である。スタックは、同じ極性の2又はそれ以上のFETを有する。即ち、1つのスタック内の全てのFETはNチャネルFETであり、又は全てのFETはPチャネルFETであり、即ち、1つのスタック内の少なくとも全てのFETは互いに実質的に同じように動作する。
ある実施例で、FETスタックのFETは、全て、例えば、故障電圧VGS(br)、VDS(br)、及びVDG(br)等の実質的に同様の耐圧容量を有しても良い。ある集積回路製造工程に関して、これらの値は、全てのFETで同様である。更に、ある集積回路製造工程に関して、故障電圧VGS(br)、VDS(br)、及びVDG(br)は、互いにほぼ等しくても良い。適切なバイアスは、これらの故障電圧のいずれも回路の通常動作中に超えられないことを有効に確実にしうる。ある実施例では、適切なバイアスにより、VdriveREF202とVdrive204との間の電圧偏位は、スタックの夫々の構成要素であるFETに関してVDS故障電圧の合計に近づくことを可能にされても良い。
RBX(equiv)(CGX+CGPX)=10/fO (式1)
である。
VBX=X(Vpeak)/2N (式2)
である。従って、N=4である場合には、VB2=Vpeal/4、VB3=3(Vpeak)/8、及びVB4=Vpeak/2が得られる。
図2及び7で、夫々のゲートノード(VGX)は、キャパシタCGXを介して基準電圧VdriveREFへ結合されている。夫々のゲートノードは、また、バイアス抵抗を介して直流バイアス電圧へ結合されている。この構成で、FETスタックの夫々のFETMXの実効駆動電圧VGSXは、ソースからゲートノードへの、及びゲートノードから交流接地へのインピーダンスとともに、そのソースの電圧偏位VSXに依存する。これらのインピーダンスは、ゲート−ソース間容量とカップリングキャパシタCGXとによって決定づけられる。CGXの適切な値は、以下で決定されうる。
CGX≦COXX/(X−2) (式3)
が得られる。X=2では、期待されるようにCGX≦無限大となる。また、期待されるように、CGXの過度な値は、過度なゲート−ソース間電圧偏位(ΔVGSX)を引き起こす傾向を有する。式3の不等式は、デバイスのノード間の過電圧を防ぎうる。しかし、CGXは、望ましくは、故障電圧を超えない範囲で最大許容駆動レベルを供給するように可能な限り大きくあるべきである。従って、式3の不等式は、近似等式として扱われても良い。
図4は、図1で表されるようなi級PAで用いられうるシャントフィルタ400を表す。シャントフィルタ400のノード402は、図1の駆動出力ノード106へ接続され、反対のノード404は、図1の回路共通電位104へ接続されうる。シャントフィルタ400は、1又はそれ以上の特定の周波数の夫々で極小インピーダンスを供給しうる。最小インピーダンスは、(例えば、駆動素子200及びRFチョークLS108によって生成される)駆動回路インピーダンスと整合されうる。シャントフィルタ素子は、駆動素子200を有する集積回路の一部として製造されても良く、シャントフィルタ400の素子を流れる電流のループ領域を低減する。
図5は、図1の1つの可能なシャント電力制御回路500の素子を表す。電力制御入力部502は、筐体接地112に対してバイアスを生じうる。(例えば、ボンドワイヤのインダクタンスを反映しうる)誘導性インピーダンスLg1504は、筐体接地112と、電力制御FETMPC506のソースとの間に表されている。接続部508は、図1の回路共通電位104へ結合されても良い。インダクタンスLg2510は、通常、電力制御回路のバイパスキャパシタCPC512に直列に存在する。直流電圧VDDが筐体接地112に対するとすると、CPC512の両端に発生した十分に直流である電圧は、回路共通電位104に対して実効供給電圧を減らしうる。
図6は、多目的なPAアーキテクチャを形成するよう図1のシャントフィルタ400と同様の方法で用いられうるフィルタ回路600の簡単化された回路図である。図1の駆動出力ノード106は、1/4波長伝送線路602と、カップリングCC1612とを介して出力フィルタ部へ結合されても良い。出力フィルタ部は、動作周波数fOで共振するLOF1610及びCOF1608の並列結合を有しうる。シャントフィルタ400の幾つかの実施例とは異なり、図6の出力フィルタ部は、通常、PA集積回路の一部ではなく、従って、回路共通部よりもむしろ筐体接地112を基準とする。接地112に対するこのバイパスフィルタのインピーダンスは、周波数がfOから逸脱するにつれて急速に低下し、従って、動作周波数の高調波は、伝送線路602の出力フィルタ端部へ効果的に短絡される。従って、適切に調整された1/4波長伝送線路の定在波は、Zdriveノードで見られるように、夫々の奇数高調波では高いインピーダンスを、夫々の偶数高調波では低いインピーダンスを供給する。ZOUTノード604は、図1に示されるように、更なる出力フィルタ部116〜118と、RFスイッチ120と、アンテナ110とへ結合されても良い。マッチング回路(図示せず。)が、また、必要とされても良く、これは、カップリングキャパシタCC302が削除される以外は図3で表される回路と同様である。このような更なるフィルタリング及びマッチング回路、又はそれに結合された伝送線路は、動作周波数fOでの抵抗インピーダンスROUTequiv606としてフィルタ回路600に理想的に現れる。
ここで記述されるようなFETスタックの実施例は、そのソースへ結合された基準電圧に対してそのゲートへ結合された駆動信号を受信する単入力FETを有しうる。スタックの残りのFETは、それらが単入力FETでの導通の制御下で導通するように、単入力FETへスレーブされうる。FETスタックの他のFETが単入力FETにスレーブされるところの方法は、FETに適切にバイアスをかけるために用いられる方法と協働する。従って、スレーブ化及びバイアスは、同時に扱われる。
RB1=RB2=...=RB(N−1) (式4)
が得られ、従って:
RBN=(N−1)RB1 (式5)
となる。
(CGX+COXX)=COX(N−1)/(N−2) (式6)
RBX(equiv)=RB1(N−1)/2 (式7)
RB1≧20(N−2)/[COX((N−1)2fO] (式8)
が得られる。従って、N=3に関して、RB1≧5/COX/fOとなり、RB1は、(COX及びfOの所定の値に関して)Nが大きくなるにつれて単調に減少する。
CB≧COX(N−1)/(N−2)/4 (式9)
が得られる。従って、N=3に関して、CB≧COX/2となる。Nが大きくなるにつれて、同じリップル電圧を実現するために必要とされる(COXに対する)CBの値は小さくなる。
図1〜8に関して先に説明されたFETスタックは、NチャネルFET(N−FET)を用いる。PチャネルFET(P−FET)スタックは、夫々の電圧と、スタックに結合された有極部品の極性を反転させることにより、同様に製造されうる。P−FETスタックの基準電圧は、一般的に、第1の単入力FETMP1のソースへ結合されうる。このような逆回路は、上述されたN−FETスタック回路と実質的に同じ原理に従って動作する。例えば、Vdrive818は、全てのFETがPチャネルであって、且つツェナーDZ822接続が反転される(アノードとカソードとが交換される)ならば、図8の基準802に対して負となりうる。
RF送受信機は、例えば図12に表わされたデュアルバンドRF送受信機のように、通常、図12の項目1226又は1256のような受信信号増幅器を有する。このような受信信号増幅器は、通常、低雑音増幅器(LNA)であり、アンテナから受信された信号を調整するために用いられる。RFフロントエンドは、LNAを必ずしも含まないRF送受信機回路と考えられることがある。
集積回路製造の詳細は、上記で示されていない。約2.4GHzで1Wより過度に出力電力を有するものも含め、幾つかの好ましい実施例で、集積回路は、1997年9月2日に公報が発行され、「サファイヤチップ上の単一極薄シリコンにおける高周波無線通信システム(High−Frequency Wireless Communication System on a Single Ultrathin Silicon On Sapphire Chip)」と題された米国特許番号5,663,570号に記載されるようなサファイヤ処理における極薄シリコンに従って作られても良い。他のセミコンダクタ・オン・インシュレータ(SIO)技術は、少なくとも幾つかの周波数帯域及び電力レベルに関して、上述されたデュアルバンド送受信機集積回路を作るために使用されても良い。
上記は、集積回路における一対のノード間の導通を制御するよう積層トランジスタを用いる方法及び装置の実施例及び新規な特徴について説明する。当業者には明らかであるように、表される方法及び装置の形状及び詳細に対する様々な削除、置換及び変更は、本発明の適用範囲から逸脱することなく行われる。多数の代わりの実施例が考えられるが、全ての実施例を明示的に列挙することは実際的ではない。このようにして、先に挙げられ、且つ/あるいは示された装置又は方法の代替案の夫々の実際的な組み合わせは、主たる装置又は方法の明確な代替実施例を構成する。このような装置又は方法の代替案の均等に係る夫々の組み合わせは、また、主たる装置又は方法の明確な代替実施例を構成する。従って、本発明の適用範囲は、添付の特許請求の範囲によってのみ決定されるべきであり、このような制限が添付の特許請求の範囲で挙げられる又は意図的に関係する限りにおいて、先に示された特徴によって制限されるべきではない。
Claims (16)
- モノリシック集積回路上のRFフロントエンド集積回路であって、
a)実質的に送信に適した周波数成分及び位相を有する送信信号を受信し、前記送信信号を増幅して、増幅送信信号を発生させるよう構成されたRF信号増幅器と、
b)前記増幅送信信号から抽出された入力信号へ結合された入力ノードを有し、前記入力信号を増幅して、電力増幅器出力特性インピーダンスを有する電力増幅送信信号を発生させるよう構成され、前記電力増幅送信信号の振幅を制御可能なように抑制するよう構成されたレギュレータ回路を有するRF電力増幅器(PA)と、
c)直流成分を遮断し、前記信号の特性インピーダンスを変更し、不要な周波数を受け入れないことによって前記電力増幅送信信号を調整して、アンテナ整合送信信号を発生させるよう構成されたマッチング、カップリング及びフィルタリング回路と、
d)前記アンテナ整合送信信号をアンテナ接続ノードへ制御可能なように結合するよう、又は前記アンテナ接続ノードを前記送信ノードから切り離し、代わりに前記アンテナ接続ノードを受信信号増幅経路へ結合するよう構成されたアンテナスイッチと、
e)前記アンテナスイッチを介して結合された前記送信信号の少なくとも振幅を反映する送信電力信号を発生させるよう構成された送信信号検知回路と、
f)前記アンテナスイッチにより結合された前記送信信号の振幅が所定の制限を超えることを実質的に防ぐように、前記レギュレータ回路に前記送信電力信号に応答して前記電力増幅送信信号を抑制させるよう構成された制御回路とを有することを特徴とする集積回路。 - 前記増幅送信信号へ結合された入力と、前記RF電力増幅器の前記入力ノードへ結合された出力とを有し、前記増幅送信信号の波形及びデューティーサイクルを調整して、前記入力ノードに実質的に適したデューティーサイクルを有する矩形波を発生させるよう構成された矩形波調整器を更に有する、ことを特徴とする請求項1記載の集積回路。
- 前記矩形波調整器は、前記矩形波調整器へ結合されたデューティーサイクル制御信号の制御下で前記RF電力増幅器へ結合された前記矩形波のデューティーサイクルを調整するよう構成された制御部を有する、ことを特徴とする請求項2記載の集積回路。
- 前記RF電力増幅器は、出力駆動ノードと回路共通部との間に配置され、線形動作を回避して、最小インピーダンス又は最大インピーダンスでのみ実質的に動作するよう構成されたスイッチング回路と、前記出力駆動ノードと前記レギュレータ回路との間に結合された無線周波数チョーク(RFC)とを有する、ことを特徴とする請求項1乃至3のうちいずれか一項記載の集積回路。
- 前記RF電力増幅器の前記スイッチング回路は、共通極性の複数の直列接続されたFETを有し、前記複数の直列接続されたFETは、それらの間でほぼ等しく前記スイッチング回路へ印加された最大電圧ストレスを分割するよう構成される、ことを特徴とする請求項4記載の集積回路。
- 前記複数の直列接続されたFETは、互いに実質的に同時にオン及びオフを切り替えるよう構成された非常に多数の直列接続されたFETである、ことを特徴とする請求項5記載の集積回路。
- 前記RF電力増幅器は、全て実質的に同時に導通する1又はそれ以上のFETから成るスイッチング装置の唯1つのみを有し、前記出力駆動ノード及び回路共通部との間に配置されたシャントフィルタを更に有し、
前記シャントフィルタは、著しい抵抗性を有するインピーダンスを介して動作周波数fOの1又はそれ以上の高調波での前記電力増幅送信信号の信号成分を導き、一方、前記動作周波数fOでの信号成分を実質的に受け入れないよう構成される、ことを特徴とする請求項4記載の集積回路。 - 前記シャントフィルタは、周波数の関数であって、2×fO及び3×fOの周波数で前記電力増幅器出力特性インピーダンスにほぼ等しい極小値を有するインピーダンスを有する、ことを特徴とする請求項7記載の集積回路。
- 前記アンテナ整合送信信号は、少なくとも約900MHzの動作周波数fOを有し、当該RFフロントエンド集積回路は、前記動作周波数fOで前記アンテナ接続ノードへ少なくとも約1Wの電力を供給するよう構成される、ことを特徴とする請求項1乃至8のうちいずれか一項記載の集積回路。
- 請求項1の前記項目(b)に従うが、第2の動作周波数f1での入力信号を受け入れ、前記送信信号検知回路からの信号により制御されるレギュレータ回路を有する第2のRF電力増幅器と、
請求項1の前記項目(c)に従うが、第2のアンテナ整合送信信号を生成するよう構成される第2のマッチング、カップリング及びフィルタリング回路とを更に有し、
前記アンテナスイッチは、更に、前記第2のアンテナ整合送信信号へだけ、又は第2の受信信号増幅経路へだけ前記アンテナ接続ノードを制御可能なように結合するよう構成される、ことを特徴とする請求項1乃至9のうちいずれか一項記載の集積回路。 - 出力駆動ノードで出力信号を生成するよう構成されたRF電力増幅器(PA)であって、
a)動作周波数fOでRF入力信号を受信するよう構成された入力ノードと、
b)線形動作を回避するために、前記RF入力信号の制御下で、オンインピーダンスを介して回路共通部へ前記出力駆動ノードを結合するよう、又は前記回路共通部から前記出力駆動ノードを実質的に切り離すよう構成されたスイッチング回路と、
c)電源VDDと前記出力駆動ノードとの間に結合され、前記スイッチング回路動作の制御下で前記動作周波数fOにおいて実質的に正弦波である波形を有する電流を伝送するよう構成されたRFチョーク(RFC)と、
d)前記出力駆動ノードと前記回路共通部との間に配置され、前記動作周波数fOの整数高調波である周波数を有する出力駆動信号の成分に関して、前記RF電力増幅器の特性出力インピーダンスZ0の抵抗成分にほぼ等しい抵抗成分を有する終端インピーダンスZTを介して電流を導くよう構成されたシャントフィルタとを有する、ことを特徴とするRF電力増幅器。 - 前記シャントフィルタは、前記動作周波数fOでの整数高調波である周波数で極小インピーダンスを有する、ことを特徴とする請求項11記載のRF電力増幅器。
- 前記シャントフィルタは、2×fO及び3×fOで極小インピーダンスを有する、ことを特徴とする請求項12記載のRF電力増幅器。
- 前記シャントフィルタの前記極小インピーダンスは、前記出力駆動ノードで前記特性出力インピーダンスZ0にほぼ等しい、ことを特徴とする請求項12又は13記載のRF電力増幅器。
- 前記入力ノードへ結合され、前記RF入力信号から抽出された信号を供給して、前記スイッチング回路を制御するよう構成された入力調整回路を更に有し、
前記抽出された信号は、前記入力調整回路により制御されるデューティーサイクルを有する実質的に矩形である波形を有する、ことを特徴とする請求項11乃至14のうちいずれか一項記載のRF電力増幅器。 - 単一モノリシック集積回路チップ上にRFフロントエンド回路を作る方法であって、
a)前記チップから離れたアンテナへ前記RFフロントエンドを結合するための1つの単独アンテナ接続ノードを設け、
i)送信信号振幅を反映する信号を発生させるよう構成された送信信号検知回路と、
ii)前記チップ上に配置されたアンテナスイッチの共通接続と
へ前記アンテナ接続ノードを結合するステップと、
b)受信送信信号を増幅するよう構成された送信信号増幅器へ入力信号ノードを結合するステップと、
c)実質的に線形な動作でなければ、出力駆動ノードを回路共通へ切り替えるように、又は実質的に線形な動作であれば、前記増幅された受信送信信号から得られた制御下で、前記出力駆動ノードが動作周波数fOで特性インピーダンスZdriveを有するように、スイッチングモードで動作するよう構成されたスイッチング回路を有する電力増幅器(PA)をレイアウトするステップと、
d)RFチョーク(RFC)の第1の接続へ前記電力増幅器出力駆動ノードを結合し、前記RFCの第2の接続をレギュレータ回路を介して電源へ結合するステップと、
e)前記アンテナ接続ノードへ切替え可能なように結合された送信信号が前記アンテナへの接続の予想インピーダンスに実質的に等しい特性インピーダンスを有するように、マッチング、カップリング及びフィルタリング回路を介して前記アンテナスイッチの入力へ前記電力増幅器出力駆動ノードを結合するステップと、
f)前記アンテナ接続へ、前記アンテナ接続での過電圧を反映する信号を発生させるよう構成された出力信号検知回路を結合するステップと、
g)前記出力駆動信号の振幅が前記アンテナ接続での著しい過電圧の存在を除外するよう制御されるところの前記レギュレータ回路へ前記アンテナ接続での過電圧を反映する前記信号を結合ステップとを有する、ことを特徴とする方法。
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US11070244B2 (en) | 2021-07-20 |
WO2006002347A1 (en) | 2006-01-05 |
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EP1774620A4 (en) | 2009-12-30 |
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US20120252384A1 (en) | 2012-10-04 |
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US10715200B2 (en) | 2020-07-14 |
US8131251B2 (en) | 2012-03-06 |
US20190081655A1 (en) | 2019-03-14 |
US11588513B2 (en) | 2023-02-21 |
US20220006484A1 (en) | 2022-01-06 |
JP4659826B2 (ja) | 2011-03-30 |
US20120007679A1 (en) | 2012-01-12 |
US20140306767A1 (en) | 2014-10-16 |
US20200014417A1 (en) | 2020-01-09 |
US9680416B2 (en) | 2017-06-13 |
EP3570374B1 (en) | 2022-04-20 |
US20200373962A1 (en) | 2020-11-26 |
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