article

Reconfigurable computing: a survey of systems and software

Authors:

Katherine Compton,

Scott HauckAuthors Info & Claims

ACM Computing Surveys (CSUR), Volume 34, Issue 2

Pages 171 - 210

https://doi.org/10.1145/508352.508353

Published: 01 June 2002 Publication History

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Abstract

Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. Its key feature is the ability to perform computations in hardware to increase performance, while retaining much of the flexibility of a software solution. In this survey, we explore the hardware aspects of reconfigurable computing machines, from single chip architectures to multi-chip systems, including internal structures and external coupling. We also focus on the software that targets these machines, such as compilation tools that map high-level algorithms directly to the reconfigurable substrate. Finally, we consider the issues involved in run-time reconfigurable systems, which reuse the configurable hardware during program execution.

References

[1]

Abouzeid, P., Babba, P., De Paulet, M. C., and Saucier, G. 1993. Input-driven partitioning methods and application to synthesis on table-lookup-based FPGA's. IEEE Trans. Comput. Aid. Des. Integ. Circ. Syst. 12, 7, 913--925.

Google Scholar

[2]

Acock, S. J. B. and Dimond, K. R. 1997. Automatic mapping of algorithms onto multiple FPGA-SRAM Modules. Field-Programmable Logic and Applications, W. Luk, P. Y. K. Cheung, and M. Glesner, Eds. Lecture Notes in Computer Science, vol. 1304, Springer-Verlag, Berlin, Germany, 255--264.

Crossref

Google Scholar

[3]

Adaptive Silicon, Inc. 2001. MSA 2500 Programmable Logic Cores. Adaptive Silicon, Inc., Los Gatos, CA.

Google Scholar

[4]

Agarwal, A. 1995. VirtualWires: A Technology for Massive Multi-FPGA Systems. Available online at http://www.ikos.com/products/virtual-wires.ps.

Google Scholar

[5]

Aggarwal, A. and Lewis, D. 1994. Routing architectures for hierarchical field programmable gate arrays. In Proceedings of the IEEE International Conference on Computer Design, 475--478.

Crossref

Google Scholar

[6]

Alexander, M. J. and Robins, G. 1996. New performance-driven FPGA routing algorithms. IEEE Trans. CAD Integ. Circ. Syst. 15, 12, 1505--1517.

Crossref

Google Scholar

[7]

Altera Corporation. 1998. Data Book. Altera Corporation, San Jose, CA.

Google Scholar

[8]

Altera Corporation. 1999. Altera MegaCore Functions. Available online at http://www.altera.com/html/tools/megacore.html. Altera Corporation, San Jose, CA.

Google Scholar

[9]

Altera Corporation. 2001. Press Release: Altera Unveils First Complete System-on-a-Programmable-Chip Solution at Embedded Systems Conference. Altera Corporation, San Jose, CA.

Google Scholar

[10]

Annapolis Microsystems, Inc. 1998. Wildfire Reference Manual. Annapolis Microsystems, Inc, Annapolis, MD.

Google Scholar

[11]

Arnold, J. M., Buell, D. A., and Davis, E. G. 1992. Splash 2. In Proceedings of the ACM Symposium on Parallel Algorithms and Architectures, 316--324.

Crossref

Google Scholar

[12]

Babb, J., Rinard, M., Moritz, C. A., Lee, W., Frank, M., Barua, R., and Amarasinghe, S. 1999. Parallelizing applications into silicon. IEEE Symposium on Field-Programmable Custom Computing Machines, 70--80.

Crossref

Google Scholar

[13]

Babb, J., Tessier, R., and Agarwal, A. 1993. Virtual wires: Overcoming pin limitations in FPGA-based logic emulators. In IEEE Workshop on FPGAs for Custom Computing Machines, 142--151.

Google Scholar

[14]

Bellows, P. and Hutchings, B. 1998. JHDL---An HDL for reconfigurable systems. IEEE Symposium on Field-Programmable Custom Computing Machines, 175--184.

Crossref

Google Scholar

[15]

Betz, V. and Rose, J. 1997. VPR: A new packing, placement and routing tool for FPGA research. Lecture Notes in Computer Science 1304---Field-Programmable Logic and Applications. W. Luk, P. Y. K. Cheung, and M. Glesner, Eds. Springer-Verlag, Berlin, Germany, 213--222.

Crossref

Google Scholar

[16]

Betz, V. and Rose, J. 1999. FPGA routing architecture: Segmentation and buffering to optimize speed and density. ACM/SIGDA International Symposium on FPGAs, 59--68.

Crossref

Google Scholar

[17]

Brasen, D. R., and Saucier, G. 1998. Using cone structures for circuit partitioning into FPGA packages. IEEE Trans. CAD Integ. Circ. Syst. 17, 7, 592--600.

Crossref

Google Scholar

[18]

Brown, S. D., Francis, R. J., Rose, J., and Vranesic, Z. G. 1992a. Field-Programmable Gate Arrays, Kluwer Academic Publishers, Boston, MA.

Crossref

Google Scholar

[19]

Brown, S., Rose, J., and Vranesic, Z. G. 1992b. A detailed router for field-programmable gate arrays. IEEE Trans. Comput. Aid. Desi. 11, 5, 620--628.

Google Scholar

[20]

Budiu, M. and Goldstein, S. C. 1999. Fast compilation for pipelined reconfigurable fabrics. ACM/SIGDA International Symposium on FPGAs, 195--205.

Crossref

Google Scholar

[21]

Buell, D., Arnold, S. M., and Kleinfelder, W. J. 1996. SPLASH 2: FPGAs in a Custom Computing Machine, IEEE Computer Society Press, Los Alamitos, CA.

Google Scholar

[22]

Burns, J., Donlin, A., Hogg, J., Singh, S., and de Wit, M. 1997. A dynamic reconfiguration run-time system. IEEE Symposium on Field-Programmable Custom Computing Machines, 66--75.

Crossref

Google Scholar

[23]

Butts, M. and Batcheller, J. 1991. Method of using electronically reconfigurable logic circuits. US Patent 5,036,473.

Google Scholar

[24]

Cadambi, S. and Goldstein, S. C. 1999. CPR: A configuration profiling tool. IEEE Symposium on Field-Programmable Custom Computing Machines, 104--113.

Crossref

Google Scholar

[25]

Cadambi, S., Weener, J., Goldstein, S. C., Schmit, H., and Thomas, D. E. 1998. Managing pipeline-reconfigurable FPGAs. ACM/SIGDA International Symposium on FPGAs, 55--64.

Crossref

Google Scholar

[26]

Callahan, T. J., Chong, P., Dehon, A., and Wawrzynek, J. 1998. Fast Module Mapping and Placement for Datapaths in FPGAs. ACM/SIGDA International Symposium on FPGAs, 123--132.

Crossref

Google Scholar

[27]

Callahan, T. J., Hauser, J. R., and Wawrzynek, J. 2000. The Garp architecture and C compiler. IEEE Comput. 3, 4, 62--69.

Crossref

Google Scholar

[28]

Cardoso, J. M. P. and Neto, H. C. 1999. Macro-based hardware compilation of JavaTM bytecodes into a dynamic reconfigurable computing system. IEEE Symposium on Field-Programmable Custom Computing Machines, 2--11.

Crossref

Google Scholar

[29]

Chameleon Systems, Inc. 2000. CS2000 Advance Product Specification. Chameleon Systems, Inc., San Jose, CA.

Google Scholar

[30]

Chan, P. K. and Schlag, M. D. F. 1997. Acceleration of an FPGA router. IEEE Symposium on Field-Programmable Custom Computing Machines, 175--181.

Crossref

Google Scholar

[31]

Chang, D. and Marek-Sadowska, M. 1998. Partitioning sequential circuits on dynamically reconfigurable FPGAs. ACM/SIGDA International Symposium on FPGAs, 161--167.

Crossref

Google Scholar

[32]

Chang, S. C., Marek-Sadowska, M., and Hwang, T. T. 1996. Technology mapping for TLU FPGA's based on decomposition of binary decision diagrams. IEEE Trans. CAD Integ. Circ. Syst. 15, 10, 1226--1248.

Crossref

Google Scholar

[33]

Chichkov, A. V. and Almeida, C. B. 1997. An hardware/software partitioning algorithm for custom computing machines. Lecture Notes in Computer Science 1304---Field-Programmable Logic and Applications. W. Luk, P. Y. K. Cheung, and M. Glesner, Eds. Springer-Verlag, Berlin, Germany, 274--283.

Crossref

Google Scholar

[34]

Chien, A. A. and Byun, J. H. 1999. Safe and protected execution for the morph/AMRM reconfigurable processor. IEEE Symposium on Field-Programmable Custom Computing Machines, 209--221.

Crossref

Google Scholar

[35]

Chow, P., Seo, S. O., Rose, J., Chung, K., Páez-Monzón, G., and Rahardja, I. 1999a. The design of an SRAM-based field-programmable Gate Array---Part I: Architecture. IEEE Trans. VLSI Syst. 7, 2, 191--197.

Crossref

Google Scholar

[36]

Chow, P., Seo, S. O., Rose, J., Chung, K., Páez-Monzón, G., and Rahardja, I. 1999b. The design of an SRAM-based field-programmable Gate Array---Part II: Circuit Design and Layout. IEEE Trans. VLSI Syst. 7, 3, 321--330.

Crossref

Google Scholar

[37]

Chowdhary, A. and Hayes, J. P. 1997. General modeling and technology-mapping technique for LUT-based FPGAs. ACM/SIGDA International Symposium on FPGAs, 43--49.

Crossref

Google Scholar

[38]

Chu, M., Weaver, N., Sulimma, K., Dehon, A., and Wawrzynek, J. 1998. Object oriented circuit-generators in Java. IEEE Symposium on Field-Programmable Custom Computing Machines, 158--166.

Crossref

Google Scholar

[39]

Compton, K., Cooley, J., Knol, S., and Hauck, S. 2000. Configuration relocation and defragmentation for FPGAs, Northwestern University Technical Report, Available online at http://www.ece.nwu.edu/~kati/publications.html.

Google Scholar

[40]

Compton, K., Li, Z., Cooley, J., Knol, S., and Hauck, S. 2002. Configuration relocation and defragmentation for run-time reconfigurable computing. IEEE Trans. VLSI Syst., to appear.

Crossref

Google Scholar

[41]

Cong, J. and Hwang, Y. Y. 1998. Boolean matching for complex PLBs in LUT-based FPGAs with application to architecture evaluation. ACM/SIGDA International Symposium on FPGAs, 27--34.

Crossref

Google Scholar

[42]

Cong, J. and Wu, C. 1998. An efficient algorithm for performance-optimal FPGA technology mapping with retiming. IEEE Trans. CAD Integr. Circ. Syst. 17, 9, 738--748.

Crossref

Google Scholar

[43]

Cong, J., Wu, C., and Ding, Y. 1999. Cut ranking and pruning enabling a general and efficient FPGA mapping solution. ACM/SIGDA International Symposium on FPGAs, 29--35.

Crossref

Google Scholar

[44]

Cong, J. and Xu, S. 1998. Technology mapping for FPGAs with embedded memory blocks. ACM/SIGDA International Symposium on FPGAs, 179--188.

Crossref

Google Scholar

[45]

Cronquist, D. C., Franklin, P., Berg, S. G., and Ebeling, C. 1998. Specifying and compiling applications for RaPiD. IEEE Symposium on Field-Programmable Custom Computing Machines, 116--125.

Crossref

Google Scholar

[46]

Dandalis, A. and Prasanna, V. K. 2001. Configuration compression for FPGA-based embedded systems. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 173--182.

Crossref

Google Scholar

[47]

DeHon, A. 1996. DPGA Utilization and Application. ACM/SIGDA International Symposium on FPGAs, 115--121.

Crossref

Google Scholar

[48]

Dehon, A. 1999. Balancing interconnect and computation in a reconfigurable computing array (or, why you don't really want 100&percnt; LUT utilization). ACM/SIGDA International Symposium on FPGAs, 69--78.

Crossref

Google Scholar

[49]

Deshpande, D., Somani, A. K., and Tyagi, A. 1999. Configuration caching vs data caching for striped FPGAs. ACM/SIGDA International Symposium on FPGAs, 206--214.

Crossref

Google Scholar

[50]

Diessel, O. and El Gindy, H. 1997. Run-time compaction of FPGA designs. Lecture Notes in Computer Science 1304---Field-Programmable Logic and Applications. W. Luk, P. Y. K. Cheung, M. Glesner, Eds. Springer-Verlag, Berlin, Germany, 131--140.

Crossref

Google Scholar

[51]

Dollas, A., Sotiriades, E., and Emmanouelides, A. 1998. Architecture and design of GE1, A FCCM for golomb ruler derivation. IEEE Symposium on Field-Programmable Custom Computing Machines, 48--56.

Crossref

Google Scholar

[52]

Ebeling, C., Cronquist, D. C., and Franklin, P. 1996. RaPiD---Reconfigurable pipelined datapath. Lecture Notes in Computer Science 1142---Field-Programmable Logic: Smart Applications, New Paradigms and Compilers. R. W. Hartenstein, M. Glesner, Eds. Springer-Verlag, Berlin, Germany, 126--135.

Crossref

Google Scholar

[53]

Ejnioui, A. and Ranganathan, N. 1999. Multi-terminal net routing for partial crossbar-based multi-FPGA systems. ACM/SIGDA International Symposium on FPGAs, 176--184.

Crossref

Google Scholar

[54]

Elbirt, A. J. and Paar, C. 2000. An FPGA implementation and performance evaluation of the serpent block cipher. ACM/SIGDA International Symposium on FPGAs, 33--40.

Crossref

Google Scholar

[55]

Emmert, J. M. and Bhatia, D. 1999. A methodology for fast FPGA floorplanning. ACM/SIGDA International Symposium on FPGAs, 47--56.

Crossref

Google Scholar

[56]

Estrin, G., Bussel, B., Turn, R., and Bibb, J. 1963. Parallel processing in a restructurable computer system. IEEE Trans. Elect. Comput. 747--755.

Google Scholar

[57]

Galloway, D. 1995. The transmogrifier C hardware description language and compiler for FPGAs. IEEE Symposium on FPGAs for Custom Computing Machines, 136--144.

Crossref

Google Scholar

[58]

Gehring, S. and Ludwig, S. 1996. The trianus system and its application to custom computing. Lecture Notes in Computer Science 1142---Field-Programmable Logic: Smart Applications, New Paradigms and Compilers. R. W. Hartenstein and M. Glesner, Eds. Springer-Verlag, Berlin, Germany, 176--184.

Crossref

Google Scholar

[59]

Gehring, S. W. and Ludwig, S. H. M. 1998. Fast integrated tools for circuit design with FPGAs. ACM/SIGDA International Symposium on FPGAs, 133--139.

Crossref

Google Scholar

[60]

Gokhale, M. B. and Stone, J. M. 1998. NAPA C: Compiling for a hybrid RISC/FPGA architecture. IEEE Symposium on Field-Programmable Custom Computing Machines, 126--135.

Crossref

Google Scholar

[61]

Gokhale, M. B. and Stone, J. M. 1999. Automatic allocation of arrays to memories in FPGA processors with multiple memory banks. IEEE Symposium on Field-Programmable Custom Computing Machines, 63--69.

Crossref

Google Scholar

[62]

Goldstein, S. C., Schmit, H., Budiu, M., Cadambi, S., Moe, M., and Taylor, R. 2000. PipeRench: A Reconfigurable Architecture and Compiler, IEEE Computer, vol. 33, No. 4.

Crossref

Google Scholar

[63]

Graham, P. and Nelson, B. 1996. Genetic algorithms in software and in hardware---A performance analysis of workstations and custom computing machine implementations. IEEE Symposium on FPGAs for Custom Computing Machines, 216--225.

Google Scholar

[64]

Hauck, S. 1995. Multi-FPGA systems. Ph.D. dissertation, Univ. Washington, Dept. of C.S.&E.

Crossref

Google Scholar

[65]

Hauck, S. 1998a. Configuration prefetch for single context reconfigurable coprocessors. ACM/SIGDA International Symposium on FPGAs, 65--74.

Crossref

Google Scholar

[66]

Hauck, S. 1998b. The roles of FPGAs in reprogrammable systems. Proc. IEEE 86, 4, 615--638.

Google Scholar

[67]

Hauck, S. and Agarwal A. 1996. Software technologies for reconfigurable systems. Dept. of ECE Technical Report, Northwestern Univ. Available online at http://www.ee.washington.edu/faculty/hauck/publications.html.

Google Scholar

[68]

Hauck, S. and Borriello, G. 1997. Pin assignment for multi-FPGA systems. IEEE Trans. Comput. Aid. Desi. Integ. Circ. Syst. 16, 9, 956--964.

Crossref

Google Scholar

[69]

Hauck, S., Borriello, G., and Ebeling, C. 1998a. Mesh routing topologies for multi-FPGA systems. IEEE Trans. VLSI Syst. 6, 3, 400--408.

Crossref

Google Scholar

[70]

Hauck, S., Fry, T. W., Hosler, M. M., and Kao, J. P. 1997. The Chimaera reconfigurable functional unit. IEEE Symposium on Field-Programmable Custom Computing Machines, 87--96.

Crossref

Google Scholar

[71]

Hauck, S., Li, Z., and Schwabe, E. 1998b. Configuration compression for the Xilinx XC6200 FPGA. IEEE Symposium on Field-Programmable Custom Computing Machines, 138--146.

Crossref

Google Scholar

[72]

Hauck, S. and Wilson, W. D. 1999. Runlength compression techniques for FPGA configurations. Dept. of ECE Technical Report, Northwestern Univ. Available online at http://www.ee.washington.edu/faculty/hauck/publications. html.

Crossref

Google Scholar

[73]

Hauser, J. R. and Wawrzynek, J. 1997. Garp: A MIPS processor with a reconfigurable coprocessor. IEEE Symposium on Field-Programmable Custom Computing Machines, 12--21.

Crossref

Google Scholar

[74]

Haynes, S. D. and Cheung, P. Y. K. 1998. A reconfigurable multiplier array for video image processing tasks, suitable for embedding in an FPGA structure. IEEE Symposium on Field-Programmable Custom Computing Machines, 226--234.

Crossref

Google Scholar

[75]

Heile, F. and Leaver, A. 1999. Hybrid product term and LUT based architectures using embedded memory blocks. ACM/SIGDA International Symposium on FPGAs, 13--16.

Crossref

Google Scholar

[76]

Huang, W. J., Saxena, N., and McCluskey, E. J. 2000. A reliable LZ data compressor on reconfigurable coprocessors. IEEE Symposium on Field-Programmable Custom Computing Machines, 249--258.

Crossref

Google Scholar

[77]

Huelsbergen, L. 2000. A representation for dynamic graphs in reconfigurable hardware and its application to fundamental graph algorithms. ACM/SIGDA International Symposium on FPGAs, 105--115.

Crossref

Google Scholar

[78]

Hutchings, B. L. 1997. Exploiting reconfigurability through domain-specific systems. Lecture Notes in Computer Science 1304---Field-Programmable Logic and Applications. W. Luk, P. Y. K. Cheung, and M. Glesner, Eds. Springer-Verlag, Berlin, Germany, 193--202.

Crossref

Google Scholar

[79]

Hutchings, B., Bellows, P., Hawkins, J., Hemmert, S., Nelson, B., and Rytting, M. 1999. A CAD suite for high-performance FPGA design. IEEE Symposium on Field-Programmable Custom Computing Machines, 12--24.

Crossref

Google Scholar

[80]

Hwang, T. T., Owens, R. M., Irwin, M. J., and Wang, K. H. 1994. Logic synthesis for field-programmable gate arrays. IEEE Trans. Comput. Aid. Des. Integ. Circ. Syst. 13, 10, 1280--1287.

Google Scholar

[81]

Inuani, M. K. and Saul, J. 1997. Technology mapping of heterogeneous LUT-based FPGAs. Lecture Notes in Computer Science 1304---Field-Programmable Logic and Applications. W. Luk, P. Y. K. Cheung, and M. Glesner, Eds. Springer-Verlag, Berlin, Germany, 223--234.

Crossref

Google Scholar

[82]

Jacob, J. A. and Chow, P. 1999. Memory interfacing and instruction specification for reconfigurable processors. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 145--154.

Crossref

Google Scholar

[83]

Jean, J. S. N., Tomko, K., Yavagal, V., Shah, J., and Cook R. 1999. Dynamic reconfiguration to support concurrent applications. IEEE Trans. Comput. 48, 6, 591--602.

Crossref

Google Scholar

[84]

Kastrup, B., Bink, A., and Hoogerbrugge, J. 1999. ConCISe: A compiler-driven CPLD-based instruction set accelerator. IEEE Symposium on Field-Programmable Custom Computing Machines, 92--101.

Crossref

Google Scholar

[85]

Khalid, M. A. S. 1999. Routing architecture and layout synthesis for multi-FPGA systems. Ph.D. dissertation, Dept. of ECE, Univ. Toronto.

Google Scholar

[86]

Khalid, M. A. S. and Rose, J. 1998. A hybrid complete-graph partial-crossbar routing architecture for multi-FPGA systems. ACM/SIGDA International Symposium on FPGAs, 45--54.

Crossref

Google Scholar

[87]

Kim, H. J. and Mangione-Smith, W. H. 2000. Factoring large numbers with programmable hardware. ACM/SIGDA International Symposium on FPGAs, 41--48.

Crossref

Google Scholar

[88]

Kim, H. S., Somani, A. K., and Tyagi, A. 2000. A reconfigurable multi-function computing cache architecture. ACM/SIGDA International Symposium on FPGAs, 85--94.

Crossref

Google Scholar

[89]

Kress, R., Hartenstein, R. W., and Nageldinger, U. 1997. An operating system for custom computing machines based on the Xputer paradigm. Lecture Notes in Computer Science 1304---Field-Programmable Logic and Applications. W. Luk, P. Y. K. Cheung, and M. Glesner, Eds. Springer-Verlag, Berlin, Germany, 304--313.

Crossref

Google Scholar

[90]

Krupnova, H., Rabedaoro, C., and Saucier, G. 1997. Synthesis and floorplanning for large hierarchical FPGAs. ACM/SIGDA International Symposium on FPGAs, 105--111.

Crossref

Google Scholar

[91]

Lai, Y. T. and Wang, P. T. 1997. Hierarchical interconnection structures for field programmable gate arrays. IEEE Trans. VLSI Syst. 5, 2, 186--196.

Crossref

Google Scholar

[92]

Laufer, R., Taylor, R. R., and Schmit, H. 1999. PCI-PipeRench and the SwordAPI: A system for stream-based reconfigurable computing. IEEE Symposium on Field-Programmable Custom Computing Machines, 200--208.

Crossref

Google Scholar

[93]

Lee, Y. S. and Wu, A. C. H. 1997. A performance and routability-driven router for FPGA's considering path delays. IEEE Trans. CAD Integ. Circ. Syst. 16, 2, 179--185.

Crossref

Google Scholar

[94]

Leonard, J. and Mangione-Smith, W. H. 1997. A case study of partially evaluated hardware circuits: Key-specific DES. Lecture Notes in Computer Science 1304---Field-Programmable Logic and Applications. W. Luk, P. Y. K. Cheung, and M. Glesner, Eds. Springer-Verlag, Berlin, Germany, 151--160.

Crossref

Google Scholar

[95]

Leung, K. H., Ma, K. W., Wong, W. K., and Leong, P. H. W. 2000. FPGA Implementation of a microcoded elliptic curve cryptographic processor. IEEE Symposium on Field-Programmable Custom Computing Machines, 68--76.

Crossref

Google Scholar

[96]

Lewis, D. M., Galloway, D. R., van Ierssel, M., Rose, J., and Chow, P. 1997. The Transmogrifier-2: A 1 million gate rapid prototyping system. ACM/SIGDA International Symposium on FPGAs, 53--61.

Crossref

Google Scholar

[97]

Li, Y., Callahan, T., Darnell, E., Harr, R., Kurkure, U., and Stockwood, J. 2000a. Hardware-software co-design of embedded reconfigurable architectures. Design Automation Conference, 507--512.

Crossref

Google Scholar

[98]

Li, Z., Compton, K., and Hauck, S. 2000b. Configuration caching for FPGAs. IEEE Symposium on Field-Programmable Custom Computing Machines, 22--36.

Crossref

Google Scholar

[99]

Li, Z. and Hauck, S. 1999. Don't care discovery for FPGA configuration compression. ACM/SIGDA International Symposium on FPGAs, 91--98.

Crossref

Google Scholar

[100]

Lin, X., Dagless, E., and Lu, A. 1997. Technology mapping of LUT based FPGAs for delay optimisation. Lecture Notes in Computer Science 1304---Field-Programmable Logic and Applications. W. Luk, P. Y. K. Cheung, and M. Glesner, Eds. Springer-Verlag, Berlin, Germany, 245--254.

Crossref

Google Scholar

[101]

Liu, H. and Wong, D. F. 1999. Circuit partitioning for dynamically reconfigurable FPGAs. ACM/SIGDA International Symposium on FPGAs, 187--194.

Crossref

Google Scholar

[102]

Lucent Technologies, Inc. 1998. FPGA Data Book. Lucent Technologies, Inc., Allentown, PA.

Google Scholar

[103]

Luk, W., Shirazi, N., and Cheung, P. Y. K. 1997a. Compilation tools for run-time reconfigurable designs. IEEE Symposium on Field-Programmable Custom Computing Machines, 56--65.

Crossref

Google Scholar

[104]

Luk, W., Shirazi, N., Guo, S. R., and Cheung, P. Y. K. 1997b. Pipeline morphing and virtual pipelines. Lecture Notes in Computer Science 1304---Field-Programmable Logic and Applications. W. Luk, P. Y. K. Cheung, and M. Glesner, Eds. Springer-Verlag, Berlin, Germany, 111--120.

Crossref

Google Scholar

[105]

Lysaght, P. and Stockwood, J. 1996. A simulation tool for dynamically reconfigurable field programmable gate arrays. IEEE Trans. VLSI Syst. 4, 3, 381--390.

Crossref

Google Scholar

[106]

Mak, W. K. and Wong, D. F. 1997. Board-level multi net routing for FPGA-based logic emulation. ACM Trans. Des. Automat. Elect. Syst. 2, 2, 151--167.

Crossref

Google Scholar

[107]

Mangione-Smith, W. H. 1999. ATR from UCLA. Personal Commun.

Google Scholar

[108]

Mangione-Smith, W. H., Hutchings, B., Andrews, D., Dehon, A., Ebeling, C., Hartenstein, R., Mencer, O., Morris, J., Palem, K., Prasanna, V. K., and Spaanenburg, H. A. E. 1997. Seeking solutions in configurable computing. IEEE Comput. 30, 12, 38--43.

Crossref

Google Scholar

[109]

Marshall, A., Stansfield, T., Kostarnov, I., Vuillemin, J., and Hutchings, B. 1999. A reconfigurable arithmetic array for multimedia applications. ACM/SIGDA International Symposium on FPGAs, 135--143.

Crossref

Google Scholar

[110]

Mckay, N. and Singh, S. 1999. Debugging techniques for dynamically reconfigurable hardware. IEEE Symposium on Field-Programmable Custom Computing Machines, 114--122.

Crossref

Google Scholar

[111]

McMurchie, L. and Ebeling, C. 1995. Pathfinder: A negotiation-based performance-driven router for FPGAs. ACM/SIGDA International Symposium on FPGAs, 111--117.

Crossref

Google Scholar

[112]

Mencer, O., Morf, M., and Flynn, M. J. 1998. PAM-blox: High performance FPGA design for adaptive computing. IEEE Symposium on Field-Programmable Custom Computing Machines, 167--174.

Crossref

Google Scholar

[113]

Miyamori, T. and Olukotun, K. 1998. A quantitative analysis of reconfigurable coprocessors for multimedia applications. IEEE Symposium on Field-Programmable Custom Computing Machines, 2--11.

Crossref

Google Scholar

[114]

Moritz, C. A., Yeung, D., and Agarwal, A. 1998. Exploring optimal cost performance designs for Raw microprocessors. IEEE Symposium on Field-Programmable Custom Computing Machines, 12--27.

Crossref

Google Scholar

[115]

Nam, G. J., Sakallah, K. A., and Rutenbar, R. A. 1999. Satisfiability-based layout revisited: detailed routing of complex FPGAs via search-based boolean SAT. ACM/SIDGA International Symposium on FPGAs, 167--175.

Crossref

Google Scholar

[116]

Pan, P. and Lin, C. C. 1998. A new retiming-based technology mapping algorithm for LUT-based FPGAs. ACM/SIGDA International Symposium on FPGAs, 35--42.

Crossref

Google Scholar

[117]

Payne, R. 1997. Run-time parameterised circuits for the Xilinx XC6200. Lecture Notes in Computer Science 1304---Field-Programmable Logic and Applications. W. Luk, P. Y. K. Cheung, and M. Glesner, Eds. Springer-Verlag, Berlin, Germany, 161--172.

Crossref

Google Scholar

[118]

Purna, K. M. G. and Bhatia, D. 1999. Temporal partitioning and scheduling data flow graphs for reconfigurable computers. IEEE Trans. Comput. 48, 6, 579--590.

Crossref

Google Scholar

[119]

Quickturn, A Cadence Company. 1999a. System RealizerTM. Available online at http://www.quickturn.com/products/systemrealizer.htm. Quickturn, A Cadence Company, San Jose, CA.

Google Scholar

[120]

Quickturn, A Cadence Company. 1999b. MercuryTM Design Verification System Technology Backgrounder. Available online at http://www.quickturn.com/products/mercury_backgrounder.htm. Quickturn, A Cadence Company, San Jose, CA, 1999.

Google Scholar

[121]

Razdan, R. and Smith, M. D. 1994. A high-performance microarchitecture with hardware-programmable functional units. International Symposium on Microarchitecture, 172--180.

Crossref

Google Scholar

[122]

Rencher, M. and Hutchings, B. L. 1997. Automated target recognition on SPLASH2. IEEE Symposium on Field-Programmable Custom Computing Machines, 192--200.

Crossref

Google Scholar

[123]

Rose, J., El Gamal, A., and Sangiovanni-Vincentelli, A. 1993. Architecture of field-programmable gate arrays. Proc. IEEE 81, 7, 1013--1029.

Google Scholar

[124]

Rupp, C. R., Landguth, M., Garverick, T., Gomersall, E., Holt, H., Arnold, J. M., and Gokhale, M. 1998. The NAPA adaptive processing architecture. IEEE Symposium on Field-Programmable Custom Computing Machines, 28--37.

Crossref

Google Scholar

[125]

Sangiovanni-Vincentelli, A., El Gamal, A., and Rose, J. 1993. Synthesis methods for field programmable gate arrays. Proc. IEEE 81, 7, 1057--1083.

Google Scholar

[126]

Sankar, Y. and Rose, J. 1999. Trading quality for compile time: Ultra-fast placement for FPGAs. ACM/SIGDA International Symposium on FPGAs, 157--166.

Crossref

Google Scholar

[127]

Scalera, S. M. and Vazquez, J. R. 1998. The design and implementation of a context switching FPGA. IEEE Symposium on Field-Programmable Custom Computing Machines, 78--85.

Crossref

Google Scholar

[128]

Selvidge, C., Agarwal, A., Dahl, M., and Babb J. 1995. TIERS: Topology IndependEnt Pipelined Routing and Scheduling for VirtualWireTM Compilation. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 25--31.

Crossref

Google Scholar

[129]

Senouci, S. A., Amoura, A., Krupnova, H., and Saucier, G. 1998. Timing driven floorplanning on programmable hierarchical targets. ACM/SIGDA International Symposium on FPGAs, 85--92.

Crossref

Google Scholar

[130]

Shahookar, K. and Mazumder, P. 1991. VLSI cell placement techniques. ACM Comput. Surv. 23, 2, 145--220.

Crossref

Google Scholar

[131]

Shi, J. and Bhatia, D. 1997. Performance driven floorplanning for FPGA based designs. ACM/SIGDA International Symposium on FPGAs, 112--118.

Crossref

Google Scholar

[132]

Shirazi, N., Luk, W., and Cheung, P. Y. K. 1998. Automating production of run-time reconfigurable designs. IEEE Symposium on Field-Programmable Custom Computing Machines, 147--156.

Crossref

Google Scholar

[133]

Slimane-Kadi, M., Brasen, D., and Saucier, G. 1994. A fast-FPGA prototyping system that uses inexpensive high-performance FPIC. ACM/SIGDA Workshop on Field-Programmable Gate Arrays.

Google Scholar

[134]

Sotiriades, E., Dollas, A., and Athanas, P. 2000. Hardware-software codesign and parallel implementation of a Golomb ruler derivation engine. IEEE Symposium on Field-Programmable Custom Computing Machines, 227--235.

Crossref

Google Scholar

[135]

Stohmann, J. and Barke, E. 1996. An universal CLA adder generator for SRAM-based FPGAs. Lecture Notes in Computer Science 1142---Field-Programmable Logic: Smart Applications, New Paradigms and Compilers. R. W. Hartenstein and M. Glesner, Eds. Springer-Verlag, Berlin, Germany, 44--54.

Crossref

Google Scholar

[136]

Swartz, J. S., Betz, V., and Rose, J. 1998. A fast routability-driven router for FPGAs. ACM/SIGDA International Symposium on FPGAs, 140--149.

Crossref

Google Scholar

[137]

Synopsys, Inc. 2000. CoCentric System C Compiler. Synopsys, Inc., Mountain View, CA.

Google Scholar

[138]

Synplicity, Inc. 1999. Synplify User Guide Release 5.1. Synplicity, Inc., Sunnyvale, CA.

Google Scholar

[139]

Takahara, A., Miyazaki, T., Murooka, T., Katayama, M., Hayashi, K., Tsutsui, A., Ichimori, T., and Fukami, K. 1998. More wires and fewer LUTs: A design methodology for FPGAs. ACM/SIGDA International Symposium on FPGAs, 12--19.

Crossref

Google Scholar

[140]

Thakur, S., Chang, Y. W., Wong, D. F., and Muthukrishnan, S. 1997. Algorithms for an FPGA switch module routing problem with application to global routing. IEEE Trans. CAD Integ. Circ. Syst. 16, 1, 32--46.

Crossref

Google Scholar

[141]

Togawa, N., Yanagisawa, M., and Ohtsuki, T. 1998. Maple-OPT: A performance-oriented simultaneous technology mapping, placement, and global gouting algorithm for FPGA's. IEEE Trans. CAD Integ. Circ. Syst. 17, 9, 803--818.

Crossref

Google Scholar

[142]

Trimberger, S. 1998. Scheduling designs into a time-multiplexed FPGA. ACM/SIGDA International Symposium on FPGAs, 153--160.

Crossref

Google Scholar

[143]

Trimberger, S., Carberry, D., Johnson, A., and Wong, J. 1997a. A time-multiplexed FPGA. IEEE Symposium on Field-Programmable Custom Computing Machines, 22--28.

Crossref

Google Scholar

[144]

Trimberger, S., Duong, K., and Conn, B. 1997b. Architecture issues and solutions for a high-capacity FPGA. ACM/SIGDA International Symposium on FPGAs, 3--9.

Crossref

Google Scholar

[145]

Tsu, W., Macy, K., Joshi, A., Huang, R., Walker, N., Tung, T., Rowhani, O., George, V., Wawrzynek, J., and Dehon, A. 1999. HSRA: High-speed, hierarchical synchronous reconfigurable array. ACM/SIGDA International Symposium on FPGAs, 125--134.

Crossref

Google Scholar

[146]

Vahid, F. 1997. I/O and performance tradeoffs with the FunctionBus during multi-FPGA partitioning. ACM/SIGDA International Symposium on FPGAs, 27--34.

Crossref

Google Scholar

[147]

Varghese, J., Butts, M., and Batcheller, J. 1993. An efficient logic emulation system. IEEE Trans. VLSI Syst. 1, 2, 171--174.

Google Scholar

[148]

Vasilko, M. and Cabanis, D. 1999. Improving simulation accuracy in design methodologies for dynamically reconfigurable logic systems. IEEE Sympos. Field-Prog. Cust. Comput. Mach. 123--133.

Crossref

Google Scholar

[149]

Vuillemin, J., Bertin, P., Roncin, D., Shand, M., Touati, H., and Boucard, P. 1996. Programmable active memories: Reconfigurable systems come of age. IEEE Trans. VLSI Syst. 4, 1, 56--69.

Crossref

Google Scholar

[150]

Wang, Q. and Lewis, D. M. 1997. Automated field-programmable compute accelerator design using partial evaluation. IEEE Symposium on Field-Programmable Custom Computing Machines, 145--154.

Crossref

Google Scholar

[151]

Weinhardt, M. and Luk, W. 1999. Pipeline vectorization for reconfigurable systems. IEEE Symposium on Field-Programmable Custom Computing Machines, 52--62.

Crossref

Google Scholar

[152]

Wilton, S. J. E. 1998. SMAP: Heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays. ACM/SIGDA International Symposium on FPGAs, 171--178.

Crossref

Google Scholar

[153]

Wirthlin, M. J. and Hutchings, B. L. 1995. A dynamic instruction set computer. IEEE Symposium on FPGAs for Custom Computing Machines, 99--107.

Crossref

Google Scholar

[154]

Wirthlin, M. J. and Hutchings, B. L. 1996. Sequencing run-time reconfigured hardware with software. ACM/SIGDA International Symposium on FPGAs, 122--128.

Crossref

Google Scholar

[155]

Wirthlin, M. J. and Hutchings, B. L. 1997. Improving functional density through run-time constant propagation. ACM/SIGDA International Symposium on FPGAs, 86--92.

Crossref

Google Scholar

[156]

Wittig, R. D. and Chow, P. 1996. OneChip: An FPGA processor with reconfigurable logic. IEEE Symposium on FPGAs for Custom Computing Machines, 126--135.

Google Scholar

[157]

Wood, R. G. and Rutenbar, R. A. 1997. FPGA routing and routability estimation via Boolean satisfiability. ACM/SIGDA International Symposium on FPGAs, 119--125.

Crossref

Google Scholar

[158]

Wu, Y. L. and Marek-Sadowska, M. 1997. Routing for array-type FPGA's. IEEE Trans. CAD Integ. Circ. Syst. 16, 5, 506--518.

Crossref

Google Scholar

[159]

Xilinx, Inc. 1994. The Programmable Logic Data Book. Xilinx, Inc., San Jose, CA.

Google Scholar

[160]

Xilinx, Inc. 1996. XC6200: Advance Product Specification. Xilinx, Inc., San Jose, CA.

Google Scholar

[161]

Xilinx, Inc. 1997. LogiBLOX: Product Specification. Xilinx, Inc., San Jose, CA.

Google Scholar

[162]

Xilinx, Inc. 1999. VirtexTM 2.5 V Field Programmable Gate Arrays: Advance Product Specification. Xilinx, Inc., San Jose, CA.

Google Scholar

[163]

Xilinx, Inc. 2000. Press Release: IBM and Xilinx Team to Create New Generation of Integrated Circuits. Xilinx, Inc., San Jose, CA.

Google Scholar

[164]

Xilinx, Inc. 2001. Virtex-II 1.5V Field Programmable Gate Arrays: Advance Product Specification. Xilinx, Inc., San Jose, CA.

Google Scholar

[165]

Yasar, G., Devins, J., Tsyrkina, Y., Stadtlander, G., and Millham, E. 1996. Growable FPGA macro generator. Lecture Notes in Computer Science 1142---Field-Programmable Logic: Smart Applications, New Paradigms and Compilers. R. W. Hartenstein and M. Glesner, Eds. Springer-Verlag, Berlin, Germany, 307--326.

Crossref

Google Scholar

[166]

Yi, K. and Jhon, C. S. 1996. A new FPGA technology mapping approach by cluster merging. Lecture Notes in Computer Science 1142---Field-Programmable Logic: Smart Applications, New Paradigms and Compilers. R. W. Hartenstein and M. Glesner, Eds. Springer-Verlag, Berlin, Germany, 366--370.

Crossref

Google Scholar

[167]

Zhong, P., Martinosi, M., Ashar, P., and Malik, S. 1998. Accelerating Boolean satisfiability with configurable hardware. IEEE Symposium on Field-Programmable Custom Computing Machines, 186--195.

Crossref

Google Scholar

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Reviewer: Marlin W Thomas

Computer science can be seen as a tension between hardware and software, which alternate in ascendancy within the field. In the early days of computing, hardware was central to the computer science curriculum. More recently, software has been central. Algorithms coded in hardware are fast and efficient, but expensive and difficult to modify. Software is inexpensive, and easily modified, but slow to execute. Computer scientists tend to concentrate on one area of the field at the expense of the other. Reconfigurable computing codes algorithms in hardware that can be modified nearly as easily as software. This promises to reduce the tension between hardware and software, and to increase the efficiency of computer systems, especially if computationally complex algorithms are coded onto reconfigurable hardware. This paper provides a succinct, yet thorough, survey of the basic concepts of reconfigurable computing, and of work done in this area over the past five years. The authors are careful to explain key terms and concepts and to illustrate them graphically where appropriate. Their treatment of the field will be especially useful to software developers who have weak hardware backgrounds. Particular attention is paid to the coupling of reconfigurable hardware, such as field-programmable gate arrays (FPGAs), and commonly available microprocessors. It is especially strong in its treatment of the logic blocks associated with FPGAs, and in its detailed discussion of run-time reconfiguration. The extensive reference list provides a starting point for those wanting more details. I highly recommend this paper to anyone new to the field. Online Computing Reviews Service

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Published In

ACM Computing Surveys Volume 34, Issue 2

June 2002

141 pages

ISSN:0360-0300

EISSN:1557-7341

DOI:10.1145/508352

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 2002

Published in CSUR Volume 34, Issue 2

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