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Configuration caching vs data caching for striped FPGAs

Published: 01 February 1999 Publication History
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References

[1]
H. Schmit, "Incremental Reconfiguration for Pipelined Applications," in Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, pp. 47- 55, 1997.
[2]
J. D. Hadley and B. L. Hutchings, "Design Methodologies for Partially Reconfigured Systems," in Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, pp. 78-84 April 1995.
[3]
J. G. Eldredge and B.L. Hutchings, "Density Enhancement of a Neural Network Using FPGAs and Run- Time Reconfiguration," in Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, pp. 180-188 April 1994.
[4]
J. E. Vuillemin, Patrice Bertin, Didier Roncin, Mark Shand, Herv~ H. Touati, and Philippe Boucard, "Programmable Active Memories: Reconfigurable Systems Come of Age," IEEE Transactions on VLSI, Vol 4, No. 1, March 1996.
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J. Hauser and J. Wawrzynek, "Garp: A MIPS Processor with a Reconfigurable Coprocessor," in Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, April 1997.
[6]
N. Shirazi, P. Athanas, and L. Abbott, "Implementation of a 2-D Fast Fourier Transform on a FPGA-based Custom Computing Machine," The 5th International Workshop on Field Programmable Logic and Applications, September 1995.
[7]
R. Bittner, P. Athanas, and M. Musgrove, "Colt: An Experiment in Wormhole Run-time Reconfiguration," presented at SPIE Photonics East '96, November 1996.
[8]
S. Cadambi, J. Weener, S. C. Goldstein, H. Schmit, and D. E. Thomas, "Managing Pipeline- Reconfigurable FPGAs," in Proceedings A CM/SiGDA Sixth International Symposium on Field Programmable Gate Arrays, February 1998.

Cited By

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  • (2017)Pipeline Reconfigurable DSP for Dynamically Reconfigurable ArchitecturesCircuits, Systems, and Signal Processing10.1007/s00034-017-0493-x36:9(3799-3824)Online publication date: 1-Sep-2017
  • (2016)Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable SystemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.241759524:2(530-543)Online publication date: Feb-2016
  • (2012)Embedded Systems Start-Up Under Timing Constraints on Modern FPGAsEmbedded Systems Design with FPGAs10.1007/978-1-4614-1362-2_7(149-172)Online publication date: 1-Nov-2012
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cover image ACM Conferences
FPGA '99: Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
February 1999
257 pages
ISBN:1581130880
DOI:10.1145/296399
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 February 1999

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FPGA99: ACM/SIGDA Symposium on Field Programmable Gate Arrays
February 21 - 23, 1999
California, Monterey, USA

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Cited By

View all
  • (2017)Pipeline Reconfigurable DSP for Dynamically Reconfigurable ArchitecturesCircuits, Systems, and Signal Processing10.1007/s00034-017-0493-x36:9(3799-3824)Online publication date: 1-Sep-2017
  • (2016)Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable SystemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.241759524:2(530-543)Online publication date: Feb-2016
  • (2012)Embedded Systems Start-Up Under Timing Constraints on Modern FPGAsEmbedded Systems Design with FPGAs10.1007/978-1-4614-1362-2_7(149-172)Online publication date: 1-Nov-2012
  • (2012)Embedded Computing Systems on FPGAsEmbedded Systems10.1002/9781118468654.ch5(127-138)Online publication date: 6-Nov-2012
  • (2011)Embedded Systems Start-Up under Timing Constraints on Modern FPGAsProceedings of the 2011 21st International Conference on Field Programmable Logic and Applications10.1109/FPL.2011.28(103-109)Online publication date: 5-Sep-2011
  • (2005)Quick Reconfiguration in Clustered Micro-SequencerProceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 0410.1109/IPDPS.2005.370Online publication date: 4-Apr-2005
  • (2003)Performance modeling of reconfigurable SoC architectures and energy-efficient mapping of a class of application11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003.10.1109/FPGA.2003.1227259(241-250)Online publication date: 2003
  • (2001)A Reconfigurable multifunction computing cache architectureIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/92.9312289:4(509-523)Online publication date: 1-Aug-2001
  • (2000)A reconfigurable multi-function computing cache architectureProceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays10.1145/329166.329185(85-94)Online publication date: 1-Feb-2000
  • (1999)Hybrid Data/Configuration Caching for Striped FPGAsProceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines10.5555/795658.795863Online publication date: 21-Apr-1999
  • Show More Cited By

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