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Fully Homomorphic Encryption (FHE) is an attractive privacy-preserving technique that allows computation directly on encrypted data without decryption. However, it incurs significant performance and memory costs due to intensive computations. In this ...

Whilst Field-Programmable Gate Arrays (FPGAs) have been popular in accelerating high-frequency financial workload for many years, their application in quantitative finance, the utilisation of mathematical models to analyse financial markets and ...

This paper investigates intelligent reconfigurable surface‐assisted non‐orthogonal multiple access (NOMA) networks for short packet communications where the source with multiple antennas utilizes beamforming technology to serve two end users ...

This paper investigates intelligent reconfigurable surface‐assisted non‐orthogonal multiple access networks for short packet communications where the source with multiple antennas utilizes beamforming technology to serve two end users including a near ...

This paper studies the problem of spatially correlated channel estimation for reconfigurable intelligent surface (RIS)‐assisted multiple‐input multiple‐output (MIMO) systems with arbitrarily correlated Gaussian perturbation. In particular, ...

In this paper we examine the downlink channel estimation in a narrow‐band RIS‐ assisted MIMO communication system that is composed of one base station (BS) with M antennas, one RIS with N reflective elements or unit cells, and one user equipment (UE) with ...

Genomics is playing an important role in transforming healthcare. Genetic data, however, is being produced at a rate that far outpaces Moore's Law. Many efforts have been made to accelerate genomics kernels on modern commodity hardware such as CPUs ...

In avionics system networking, mixed‐critical networks are commonly used to integrate system applications with different levels of guarantees for various traffic classes on a shared resource platform, effectively addressing issues such as cabling, ...

We propose JTTPS, a networking approach that considers network component overhead minimization, TT flow schedulability, and RC flow scheduling quality while balancing the trade‐off between them and demonstrating the positive impact of FRER redundancy ...

Using reconfigurable intelligent surfaces (RISs) to improve the coverage and the data rate of future wireless networks is a viable option. These surfaces are constituted of a significant number of passive and nearly passive components that ...

This article provides a general survey of the state of the art reconfigurable intelligent reflecting surfaces (RIS) research. It discusses the principle of RIS in terms of design and operations. image image

FPGAs have been proven to be powerful computational accelerators across many types of workloads. The mainstream programming approach is high level synthesis (HLS), which maps high-level languages (e.g. C + #pragmas) to hardware. Unfortunately, HLS ...

Quantitative finance is the use of mathematical models to analyse financial markets and securities. Typically requiring significant amounts of computation, an important question is the role that novel architectures can play in accelerating these ...

Coarse-grained reconfigurable arrays (CGRAs) have gained traction over the years as a low-power accelerator due to the efficient mapping of the compute-intensive loops onto the 2-D array by the CGRA compiler. When encountering a mapping failure for a ...

A composable design scheme is presented for the development of hybrid quantum/classical algorithms and workflows for applications of quantum simulation. The proposed object‐oriented approach is based on constructing an expressive set of common ...

Coarse-grain reconfigurable arrays (CGRAs) can achieve much higher performance and efficiency than general-purpose cores, approaching the performance of a specialized design while retaining programmability. Unfortunately, CGRAs have so far only been ...

Electronic structure calculations based on density-functional theory (DFT) represent a significant part of today's HPC workloads and pose high demands on high-performance computing resources. To perform these quantum-mechanical DFT calculations on ...

While the Fat-Tree network topology represents the dominant state-of-art solution for large-scale HPC networks, its scalability in terms of power, latency, complexity, and cost is significantly challenged by the ever-increasing communication bandwidth ...

With the end of Dennard scaling and Moore's law, it is becoming increasingly difficult to build hardware for emerging applications that meet power and performance targets, while remaining flexible and programmable for end users. This is particularly ...

In this article, we present a novel type of medium-grained reconfigurable architecture that we term the Field Programmable Operation Array (FPOA). This device has been designed specifically for the implementation of HLS-generated circuitry. At the core ...

Field Programmable Gate Arrays (FPGAs), due to their programmability, have become a popular design choice for control and processing blocks of modern-day digital design. However, this flexibility makes them larger, slower, and less power-efficient when ...

Recent years have seen the increased adoption of Coarse-Grained Reconfigurable Architectures (CGRAs) as flexible, energy-efficient compute accelerators. Obtaining performance using spatial architectures while supporting diverse applications requires a ...

Coarse-grained reconfigurable architectures and other exposed datapath architectures such as transport-triggered architectures come with a high energy efficiency promise for accelerating data oriented workloads. Their main drawback results from the push ...

High Performance Computing, data analytics, and machine learning are often considered three separate and different approaches. Applications, software and now hardware stacks are typically designed to only address one of the areas at a time. This creates ...