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Hybrid product term and LUT based architectures using embedded memory blocks

Authors:

Frank Heile,

Andrew LeaverAuthors Info & Claims

FPGA '99: Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays

Pages 13 - 16

https://doi.org/10.1145/296399.296415

Published: 01 February 1999 Publication History

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Cited By

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Paul SBhunia SPaul SBhunia S(2013)PLA Based Application Mapping in MBCComputing with Memory for Energy-Efficient Robust Systems10.1007/978-1-4614-7798-3_14(137-143)Online publication date: 8-Aug-2013
https://doi.org/10.1007/978-1-4614-7798-3_14
Paul SBhunia SFix L(2008)Reconfigurable computing using content addressable memory for improved performance and resource usageProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391670(786-791)Online publication date: 8-Jun-2008
https://dl.acm.org/doi/10.1145/1391469.1391670
Chiu GSingh DManohararajah VBrown SHassoun S(2006)Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAsProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233530(135-142)Online publication date: 5-Nov-2006
https://dl.acm.org/doi/10.1145/1233501.1233530
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Index Terms

Hybrid product term and LUT based architectures using embedded memory blocks
1. Hardware
  1. Integrated circuits
    1. Logic circuits
      1. Combinational circuits
    2. Semiconductor memory

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Abstract
The large area and high power consumption are the two main bottlenecks in the conventional SRAM-based Field Programmable Gate Arrays (FPGAs). In recent works, resistive Non-Volatile Memories (NVMs) have been widely proposed to tackle the above ...
Highlights
- A hybrid LUT with one non-volatile input and multiple volatile inputs.
- The computation and storage are integrated in the non-volatile input.
- The hybrid LUT reduces the area and leakage power with extra reconfigurable resource.
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N-port memory mapping for LUT-based FPGAs
FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays

As current FPGAs grow in logic capacity, they are widely used to implement entire systems. In some specific applications, such as our embedded multi-core processor TriBA[1],user memory models are not limited to single-port or dual-port. Thus, we need a ...
Product-term-based synthesizable embedded programmable logic cores

As integrated circuits become increasingly complex, the ability to make post-fabrication changes will become more important and attractive. This capability can be realized by using programmable logic cores. Currently, such cores are available from ...

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Published In

FPGA '99: Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays

February 1999

257 pages

ISBN:1581130880

DOI:10.1145/296399

Chairmen:
Sinan Kaptanoglu
Actel Corporation
,
Steve Trimberger
Xilinx

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Association for Computing Machinery

New York, NY, United States

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Published: 01 February 1999

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FPGA99

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SIGDA

FPGA99: ACM/SIGDA Symposium on Field Programmable Gate Arrays

February 21 - 23, 1999

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

View all

Paul SBhunia SPaul SBhunia S(2013)PLA Based Application Mapping in MBCComputing with Memory for Energy-Efficient Robust Systems10.1007/978-1-4614-7798-3_14(137-143)Online publication date: 8-Aug-2013
https://doi.org/10.1007/978-1-4614-7798-3_14
Paul SBhunia SFix L(2008)Reconfigurable computing using content addressable memory for improved performance and resource usageProceedings of the 45th annual Design Automation Conference10.1145/1391469.1391670(786-791)Online publication date: 8-Jun-2008
https://dl.acm.org/doi/10.1145/1391469.1391670
Chiu GSingh DManohararajah VBrown SHassoun S(2006)Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAsProceedings of the 2006 IEEE/ACM international conference on Computer-aided design10.1145/1233501.1233530(135-142)Online publication date: 5-Nov-2006
https://dl.acm.org/doi/10.1145/1233501.1233530
Krishnamoorthy STessier R(2006)Technology mapping algorithms for hybrid FPGAs containing lookup tables and PLAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2003.81074322:5(545-559)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2003.810743
Chiu GSingh DManohararajah VBrown S(2006)Mapping Arbitrary Logic Functions into Synchronous Embedded Memories For Area Reduction on FPGAs2006 IEEE/ACM International Conference on Computer Aided Design10.1109/ICCAD.2006.320077(135-142)Online publication date: Nov-2006
https://doi.org/10.1109/ICCAD.2006.320077
Stansfield T(2003)Using Multiplexers for Control and Data in D-FabrixField Programmable Logic and Application10.1007/978-3-540-45234-8_41(416-425)Online publication date: 2003
https://doi.org/10.1007/978-3-540-45234-8_41
Hutton MChan VKazarian PMaruri VNgai TPark JPatel RPedersen BSchleicher JShumarayev SSchlag MTrimberger S(2002)Interconnect enhancements for a high-speed PLD architectureProceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays10.1145/503048.503050(3-10)Online publication date: 24-Feb-2002
https://dl.acm.org/doi/10.1145/503048.503050
Lin EWilton S(2002)The architecture of dual-mode FPGA embedded system blocksProceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)10.1109/CICC.2002.1012768(67-70)Online publication date: 2002
https://doi.org/10.1109/CICC.2002.1012768
Krishnamoorthy SSwaminathan STessier R(2002)Area-Optimized Technology Mapping for Hybrid FPGAsField-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing10.1007/3-540-44614-1_21(181-190)Online publication date: 12-Apr-2002
https://doi.org/10.1007/3-540-44614-1_21
Yan KGoto S(2001)Practical logic synthesis for CPLDs and FPGAs with PLA-style logic blocksProceedings of the 2001 Asia and South Pacific Design Automation Conference10.1145/370155.370330(231-234)Online publication date: 30-Jan-2001
https://dl.acm.org/doi/10.1145/370155.370330
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