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Performance driven floorplanning for FPGA based designs

Authors:

Jianzhong Shi,

Dinesh BhatiaAuthors Info & Claims

FPGA '97: Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays

Pages 112 - 118

https://doi.org/10.1145/258305.258321

Published: 09 February 1997 Publication History

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Abstract

Increasing design densities on large FPGAs and greater demand for performance, has calledfor special purpose tools like floorplanner, performance driven router, and more. In this paper we present a floorplanning based design mapping solution that is capable of mapping macro cell based designs as well as hierarchicaldesigns on FPGAs. The mapping solution has been tested extensively on a large collection of designs. We not only outperform state of the art CAE tools from industry in terms of execution time but also achieve much better performance in terms of timing. These methods are especially suitable for mapping designs on very large FPGAs.

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Cited By

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Ahmadinia AAngermeier JFekete SKamphans TKoch DMajer MSchweer NTeich JTessars Cvan der Veen J(2010)ReCoNodes—Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware DevicesDynamically Reconfigurable Systems10.1007/978-90-481-3485-4_10(199-221)Online publication date: 10-Feb-2010
https://doi.org/10.1007/978-90-481-3485-4_10
Fekete SVan Der Veen JMajer MTeich J(2006)Minimizing Communication Cost for Reconfigurable Slot Modules2006 International Conference on Field Programmable Logic and Applications10.1109/FPL.2006.311263(1-6)Online publication date: Aug-2006
https://doi.org/10.1109/FPL.2006.311263
Nag SRutenbar R(2006)Performance-driven simultaneous placement and routing for FPGA'sIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.70383117:6(499-518)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.703831
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Index Terms

Performance driven floorplanning for FPGA based designs
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware

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Information

Published In

FPGA '97: Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays

February 1997

174 pages

ISBN:0897918010

DOI:10.1145/258305

Chairman:
Carl Ebeling
Univ. of Washington

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 09 February 1997

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FPGA97

Sponsor:

SIGDA

FPGA97: 1997 ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 9 - 11, 1997

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

View all

Ahmadinia AAngermeier JFekete SKamphans TKoch DMajer MSchweer NTeich JTessars Cvan der Veen J(2010)ReCoNodes—Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware DevicesDynamically Reconfigurable Systems10.1007/978-90-481-3485-4_10(199-221)Online publication date: 10-Feb-2010
https://doi.org/10.1007/978-90-481-3485-4_10
Fekete SVan Der Veen JMajer MTeich J(2006)Minimizing Communication Cost for Reconfigurable Slot Modules2006 International Conference on Field Programmable Logic and Applications10.1109/FPL.2006.311263(1-6)Online publication date: Aug-2006
https://doi.org/10.1109/FPL.2006.311263
Nag SRutenbar R(2006)Performance-driven simultaneous placement and routing for FPGA'sIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.70383117:6(499-518)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.703831
Emmert JRandhar ABhatia D(2006)Fast floorplanning for FPGAsField-Programmable Logic and Applications From FPGAs to Computing Paradigm10.1007/BFb0055240(129-138)Online publication date: 27-May-2006
https://doi.org/10.1007/BFb0055240
Stohmann JHarbich KOlbrich MBarke E(2006)An optimized design flow for fast FPGA-based rapid prototypingField-Programmable Logic and Applications From FPGAs to Computing Paradigm10.1007/BFb0055235(79-88)Online publication date: 27-May-2006
https://doi.org/10.1007/BFb0055235
Malhotra SBorer TSingh DBrown S(2004)The Quartus University Interface Program: enabling advanced FPGA researchProceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921)10.1109/FPT.2004.1393272(225-230)Online publication date: 2004
https://doi.org/10.1109/FPT.2004.1393272
Emmert JLodha SBhatia D(2003)On Using Tabu Search for Design Automation of VLSI SystemsJournal of Heuristics10.1023/A:10218937121459:1(75-90)Online publication date: 1-Jan-2003
https://dl.acm.org/doi/10.1023/A%3A1021893712145
Bazargan KKastner RSarrafzadeh M(2000)Fast Template Placement for Reconfigurable Computing SystemsIEEE Design & Test10.1109/54.82567817:1(68-83)Online publication date: 1-Jan-2000
https://dl.acm.org/doi/10.1109/54.825678
Barzagan KSarrafzadeh M(1999)Fast Online Placement for Reconfigurable ComputingProceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines10.5555/795658.795862Online publication date: 21-Apr-1999
https://dl.acm.org/doi/10.5555/795658.795862
Emmert JBhatia DKaptanoglu STrimberger S(1999)A methodology for fast FPGA floorplanningProceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays10.1145/296399.296427(47-56)Online publication date: 1-Feb-1999
https://dl.acm.org/doi/10.1145/296399.296427
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