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Balancing interconnect and computation in a reconfigurable computing array (or, why you don't really want 100% LUT utilization)

Published: 01 February 1999 Publication History
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References

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cover image ACM Conferences
FPGA '99: Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
February 1999
257 pages
ISBN:1581130880
DOI:10.1145/296399
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 February 1999

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FPGA99: ACM/SIGDA Symposium on Field Programmable Gate Arrays
February 21 - 23, 1999
California, Monterey, USA

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Cited By

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  • (2024)VIPER: A VTR Interface for Placement with Error ResilienceProceedings of the 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies10.1145/3665283.3665300(99-108)Online publication date: 19-Jun-2024
  • (2023)On the Interconnection Complexity vs Size Trade-off in Circuit GraphsProceedings of the 2023 ACM International Workshop on System-Level Interconnect Pathfinding10.1145/3632409.3632838(1-7)Online publication date: 2-Nov-2023
  • (2023)Asymmetry in Butterfly Fat Tree FPGA NoC2023 International Conference on Field Programmable Technology (ICFPT)10.1109/ICFPT59805.2023.00030(227-231)Online publication date: 12-Dec-2023
  • (2023)Meltrix: A RRAM-Based Polymorphic Architecture Enhanced by Function Synthesis2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323544(1-9)Online publication date: 28-Oct-2023
  • (2023)Field‐programmable Gate ArraysDesign for Embedded Image Processing on FPGAs10.1002/9781119819820.ch2(19-44)Online publication date: 5-Sep-2023
  • (2020)VTR 8ACM Transactions on Reconfigurable Technology and Systems10.1145/338861713:2(1-55)Online publication date: 1-Jun-2020
  • (2020)Enabling Dynamic System Integration on Maxeler HLS PlatformsJournal of Signal Processing Systems10.1007/s11265-020-01545-yOnline publication date: 9-Aug-2020
  • (2019)Application-Dependent Testing of FPGA Interconnect NetworkIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.292593227:10(2296-2304)Online publication date: Oct-2019
  • (2019)A Dynamic Reconfigurable Super-VLIW Architecture for a Fault Tolerant Nanoscale Design10.1007/978-3-662-58834-5_7(121-139)Online publication date: 23-Feb-2019
  • (2018)Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology: This Paper Reflects on How Moore's Law Has Driven the Design of FPGAs Through Three Epochs: the Age of Invention, the Age of Expansion, and the Age of AccumulationIEEE Solid-State Circuits Magazine10.1109/MSSC.2018.282286210:2(16-29)Online publication date: Sep-2019
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