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Dynamic and Partial Reconfiguration of FPGAs

  • Living reference work entry
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Handbook of Computer Architecture

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Abstract

The reconfigurability of FPGAs is a unique capability that can be exploited beyond just repurposing or modifying hardware designs. Static reconfiguration, where a single monolithic hardware design is replaced by another, allows for in-field upgradability and enhancements, de-risks hardware deployment, and enables their function as off-the-shelf programmable devices. However, this configurability, through modification of configuration memory contents, also opens the door to dynamic reconfiguration, where hardware designs are changed at runtime to serve different purposes. More advanced still is the ability to modify only portions of the hardware architecture, while the rest remains functional. By closing the loop, wherein the static part of the hardware is responsible for controlling the reconfiguration of the dynamic part, self-reconfiguring systems are possible. This chapter explores the dynamic and partial reconfiguration capabilities of FPGAs from the perspectives of the architecture, the programming model, and the applications that can leverage these unique capabilities.

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Authors and Affiliations

  1. Computer Science, King Abdullah University of Science and Technology, Thuwal, Saudi Arabia

    Suhaib A. Fahmy & Krishnan B. Iyer

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  1. Suhaib A. Fahmy
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  2. Krishnan B. Iyer
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Correspondence to Suhaib A. Fahmy .

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Editors and Affiliations

  1. Sch of Computer Science & Engineering, Nanyang Technological University, Singapore, Singapore

    Anupam Chattopadhyay

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  1. Computer Science, King Abdullah University of Science and Technology, Thuwal, Saudi Arabia

    Suhaib A. Fahmy

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Fahmy, S.A., Iyer, K.B. (2024). Dynamic and Partial Reconfiguration of FPGAs. In: Chattopadhyay, A. (eds) Handbook of Computer Architecture. Springer, Singapore. https://doi.org/10.1007/978-981-15-6401-7_51-1

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  • DOI: https://doi.org/10.1007/978-981-15-6401-7_51-1

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  • Online ISBN: 978-981-15-6401-7

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