JP4418250B2 - 高周波回路モジュール - Google Patents
高周波回路モジュール Download PDFInfo
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- JP4418250B2 JP4418250B2 JP2004029111A JP2004029111A JP4418250B2 JP 4418250 B2 JP4418250 B2 JP 4418250B2 JP 2004029111 A JP2004029111 A JP 2004029111A JP 2004029111 A JP2004029111 A JP 2004029111A JP 4418250 B2 JP4418250 B2 JP 4418250B2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15182—Fan-in arrangement of the internal vias
- H01L2924/15184—Fan-in arrangement of the internal vias in different layers of the multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
- H01L2924/30111—Impedance matching
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/0929—Conductive planes
- H05K2201/093—Layout of power planes, ground planes or power supply conductors, e.g. having special clearance holes therein
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09663—Divided layout, i.e. conductors divided in two or more parts
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09972—Partitioned, e.g. portions of a PCB dedicated to different functions; Boundary lines therefore; Portions of a PCB being processed separately or differently
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Transceivers (AREA)
- Structure Of Printed Boards (AREA)
Description
Claims (5)
- モジュール基板と、
第1の信号を入力して上記第1の信号よりも周波数が高い第2の信号を出力し、更に、第3の信号を入力して上記第3の信号よりも周波数が低い第4の信号を出力する第1の回路と、
上記第2の信号を電力増幅する第2の回路と、
上記第1の回路の第1の接地面と、
上記第1の接地面とは互いに高周波的に分離された上記第2の回路の第2の接地面と、
上記第1及び第2の接地面とは高周波的に分離された共通接地面と、
上記第1の接地面と高周波的に分離された第3の接地面と、
第4の接地面と、
上記第2の信号を外部のアンテナに供給し、かつ、上記アンテナからの第3の信号を上記第4の回路に供給するためのアンテナ共用回路と、
上記アンテナ共用回路と上記電力増幅回路が有する最終段増幅素子部との間のインピーダンス整合を行なう出力整合回路と
を具備し、
上記第1の回路と上記第2の回路とが上記モジュール基板の上面に搭載され、
上記第1及び第2の接地面と上記共通接地面とが上記モジュール基板の導体層に設けられており、
上記第1及び第2の接地面と上記共通接地面とが高周波的抵抗体により接続され、
上記共通接地面は、上記第1及び第2の接地面が設けられた導体層よりも上記モジュール基板の裏面に近い方の別の導体層に設けられ、上記第1及び第2の接地面が上記共通接地面にそれぞれ高周波的抵抗体により接続され、
上記第1の回路は上記第3の信号を入力して上記第4の信号を出力する第4の回路を含んで構成され、更に、
上記第2の回路は電力増幅回路を含んで構成され、
上記最終段増幅素子部の接地端子が上記第2の接地面に接続され、上記アンテナ共用回路の接地端子が上記第3の接地面に接続され、上記出力整合回路の接地端子が上記第4の接地面に接続され、上記第4の接地面が上記第1〜第3の接地面の内の少なくともいずれかと高周波的に分離されている
ことを特徴とする高周波回路モジュール。 - 上記出力整合回路は、上記第4の接地面を接地面に持つ伝送線路と複数の容量素子とを含む
ことを特徴とする請求項1に記載の高周波回路モジュール。 - 上記第4の接地面は、上記第1〜第3の接地面の中で上記第4の接地面と高周波的に分離されている接地面よりも下方の導体層に設けられている
ことを特徴とする請求項2に記載の高周波回路モジュール。 - 上記第4の接地面が上記共通接地面である
ことを特徴とする請求項3に記載の高周波回路モジュール。 - 上記第2の接地面、上記第3の接地面及び上記第4の接地面と上記共通接地面との間に中間接地面を有し、上記第2の接地面、上記第3の接地面及び上記第4の接地面がそれぞれ高周波的抵抗体により上記中間接地面に接続され、上記中間接地面が高周波的抵抗体により上記共通接地面に接続される
ことを特徴とする請求項1に記載の高周波回路モジュール。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004029111A JP4418250B2 (ja) | 2004-02-05 | 2004-02-05 | 高周波回路モジュール |
TW093132595A TWI334744B (en) | 2004-02-05 | 2004-10-27 | Radio frequency circuit module |
US11/013,337 US7515879B2 (en) | 2004-02-05 | 2004-12-17 | Radio frequency circuit module |
CN2004101021317A CN1652333B (zh) | 2004-02-05 | 2004-12-20 | 高频电路模块 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004029111A JP4418250B2 (ja) | 2004-02-05 | 2004-02-05 | 高周波回路モジュール |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009218806A Division JP4542194B2 (ja) | 2009-09-24 | 2009-09-24 | 高周波回路モジュール |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2005223582A JP2005223582A (ja) | 2005-08-18 |
JP2005223582A5 JP2005223582A5 (ja) | 2008-04-24 |
JP4418250B2 true JP4418250B2 (ja) | 2010-02-17 |
Family
ID=34824077
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004029111A Expired - Fee Related JP4418250B2 (ja) | 2004-02-05 | 2004-02-05 | 高周波回路モジュール |
Country Status (4)
Country | Link |
---|---|
US (1) | US7515879B2 (ja) |
JP (1) | JP4418250B2 (ja) |
CN (1) | CN1652333B (ja) |
TW (1) | TWI334744B (ja) |
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2004
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- 2004-10-27 TW TW093132595A patent/TWI334744B/zh not_active IP Right Cessation
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US7515879B2 (en) | 2009-04-07 |
JP2005223582A (ja) | 2005-08-18 |
US20050176380A1 (en) | 2005-08-11 |
CN1652333B (zh) | 2010-05-12 |
TWI334744B (en) | 2010-12-11 |
TW200537993A (en) | 2005-11-16 |
CN1652333A (zh) | 2005-08-10 |
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