IEEE Transactions on Very Large Scale Integration (VLSI) Systems

First Page of the Article

During the past five years numerous mixed signal integrated circuits (IC's) have been designed, processed, and characterized based on our 0.2 µm gate length AlGaAs/GaAs quantum well HEMT technology. Utilizing the inherent advantages of the AlGaAs/GaAs ...

In this paper, the architecture and the implementation of a complex fast Fourier transform (CFFT) processor using 0.6 µm gallium arsenide (GaAs) technology are presented. This processor computes a 1024-point FFT of 16 bit complex data in less than 8 µs, ...

The continuing development of smaller electronic devices into the nanoelectronic regime offers great possibilities for the construction of highly parallel computers. This paper describes work designed to discover the best ways to take advantage of this ...

A novel sampling phase detector (SPD) using a resonant-tunneling high electron mobility transistor (RTHEMT), which features strong nonlinear characteristics, is proposed and demonstrated as a means of achieving a simple, low-powerconsumption SPD. We ...

An 8:1 multiplexer (MUX) and a 1:8 demultiplexer (DEMUX) for 2.4-Gb/s optical communication systems have been developed using 0.35-µm GaAs heterojunction fieldeffect transistors (FET's). To ensure timing margins, a new timing generator with latches and ...

A self-aligned complementary GaAs (CGaAs) technology (developed at Motorola) for low-power, portable, digital and mixed-mode circuits is being extended to address high-speed VLSI circuit applications. The process supports full complementary, unipolar (...

A digital voltage-controlled oscillator (VCO) is described which uses frequency multiplication and division to achieve very wide bandwidth. The VCO uses current-mode logic and does not require reactive elements such as inductors, capacitors or ...

This paper presents an architectural optimization for low-power asynchronous systems. The optimization is targeted to nonpipelined computation. In particular, two new sequencing controllers are introduced, which significantly increase the throughput of ...

In this paper, we present a new statistical technique for estimation of average power dissipation in digital circuits. The present parametric statistical technique estimates the average power based on the assumption that the power distribution can be ...

Retiming, introduced by Leiserson and Saxe, is a powerful transformation of circuits that preserves functionality and improves performance. The ASTRA algorithm proposed an alternative view of retiming using the equivalence between retiming and clock ...

System-level design issues are gaining increasing attention, as behavioral synthesis tools and methodologies mature. We present the SpecSyn system-level design environment, which supports the new specify-explore-refine (SER) design paradigm. This three-...

Finite fields have been used for numerous applications including error-control coding and cryptography. The design of efficient multipliers, dividers, and exponentiators for finite field arithmetic is of great practical concern. In this paper, we ...

In this paper, we investigate the design of macrocell generators of division and square root floating-point operators. The number representation used in our operators is the IEEE- 754-1985 standard for binary floating-point numbers. The design and ...

Test generation algorithms may be classified by the level of circuit description they utilize. Algorithms based on a logic-gate level description of the circuit under test (CUT) are the most common. Functional algorithms utilize a functional description ...

Excessive instantaneous power consumption may reduce the reliability and performance of VLSI chips. Hence, to synthesize circuits with high reliability, it is imperative to efficiently obtain a precise estimation of the maximum power dissipation. ...

This paper presents an analysis of the complexity of quotient-digit selection tables in SRT division implementations. SRT dividers are widely used in VLSI systems to compute floating-point quotients. These dividers use a fixed number of partial ...

Reconfigurability of processor arrays is important due to two reasons 1) to efficiently execute different algorithms and 2) to isolate faulty processors. An array processor that is reconfigurable by the user any number of times to yield a different ...

In this paper, behavioral-level synthesis techniques are presented for the design of reconfigurable hardware. The techniques are applicable for synthesis of several classes of designs, including 1) design for fault tolerance against permanent faults, 2) ...

In this paper, we present a method for efficiently obtaining area and delay estimates from RTL descriptions of a logic design. The estimates are obtained through fast compiler-type optimizations on the RTL descriptions followed by application of best-...

This paper presents a new design for two operand normalization. The two operand normalization operation involves the normalization of at least one of two operands by left shifting both by the same amount. Our design performs the computation of the shift ...

This paper presents dynamic two-stage fault isolation for sequential random logic very large scale integrated (VLSI) circuits, and introduces limited and dynamic fault dictionaries. In the first stage of the dynamic process, a limited fault dictionary ...