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A CORDIC processor for FFT computation and its implementation using gallium arsenide technology

Authors:

Roberto Sarmiento,

Félix Tobajas,

Valentín de Armas,

Roberto Esper-Chaín,

José F. López,

Juan A. Montiel-Nelson,

Antonio NúñezAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 6, Issue 1

Pages 18 - 30

https://doi.org/10.1109/92.661241

Published: 01 March 1998 Publication History

Abstract

In this paper, the architecture and the implementation of a complex fast Fourier transform (CFFT) processor using 0.6 µm gallium arsenide (GaAs) technology are presented. This processor computes a 1024-point FFT of 16 bit complex data in less than 8 µs, working at a frequency beyond 700 MHz, with a power consumption of 12.5 W. The architecture of the processor is based on the COordinate Rotation DIgital Computer (CORDIC) algorithm, which avoids the use of conventional multiplication and accumulation (MAC) units, but evaluates the trigonometric functions using only add and shift operations. Improvements to the basic CORDIC architecture are introduced in order to reduce the area and power of the processor. This together with the use of pipelining and carry save adders produces a very regular and fast processor. The CORDIC units were fabricated and tested in order to anticipate the final performance of the processor. This work also demonstrates the maturity of GaAs technology for implementing ultrahigh-performance signal processors.

References

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M. A. Bayoumi and E. E. Swartzlander, Eds., VLSI Signal Processing Technology. Boston, MA: Kluwer Academic, 1994.

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R. Sarmiento, P. P. Carballo, and A. Nú~nez, "High speed primitives of hardware accelerators for DSP in GaAs technology," in Inst. Elec. Eng. Proc.--G, Apr. 1992, vol. 139, no. 2, pp. 205-216.

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Y. H. Hu, "CORDIC based VLSI architecture for digital signal processing," IEEE Signal Processing Mag., pp. 16-35, July 1992.

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A. M. Despain, "Fourier transform computers using CORDIC iterations," IEEE Transactions on Computers, vol. c-23, no. 10, pp. 993-1001, Oct. 1974.

Digital Library

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K. Eshraghian, A. Blanksby, R. Sarmiento, and C. C. Lim, "Gallium arsenide design methodology & performance estimates for very high speed circuits using normally-off classes of logic," in Gallium Arsenide Applications Symp., IEEE-MTT Society, Torino, Italy, Apr. 1994, pp. 203-206.

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F. Tobajas, "Application specific processor for FFT computation in GaAs technology," Master thesis, Centre for Appl. Microelectron., Univ. Las Palmas de Gran Canaria, Spain, May 1996, in Spanish.

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T. G. Noll, "Carry-save architectures for high-speed digital signal processing," J. VLSI Signal Processing, 3, pp. 121-140, 1991.

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L. Hernández, F. Tobajas, J. F. López, R. Sarmiento, and A. Núñez, "Current mode techniques for embedded gallium arsenide ROM's," in Proc. XI Design Integrated Circuits Syst. Conf. DCIS'96, CPDA Publishers, Diagonal 647, 08028, Nov. 1996, pp. 87-92.

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Cited By

Chirkov GWentzlaff DGallivan KNikolopoulos DBeivide RGallopoulos E(2023)Seizing the Bandwidth Scaling of On-Package Interconnect in a Post-Moore's Law WorldProceedings of the 37th International Conference on Supercomputing10.1145/3577193.3593702(410-422)Online publication date: 21-Jun-2023
https://dl.acm.org/doi/10.1145/3577193.3593702
Saha PBanerjee ADandapat ABhattacharyya P(2011)ASIC implementation of high speed processor for calculating discrete Fourier transformation using circular convolution techniqueWSEAS Transactions on Circuits and Systems10.5555/2189899.218990210:8(278-288)Online publication date: 1-Aug-2011
https://dl.acm.org/doi/10.5555/2189899.2189902
Miyamoto NKarnan LMaruo KKotani KOhmi TImai M(2004)A small-area high-performance 512-point 2-dimensional FFT single-chip processorProceedings of the 2004 Asia and South Pacific Design Automation Conference10.5555/1015090.1015227(537-538)Online publication date: 27-Jan-2004
https://dl.acm.org/doi/10.5555/1015090.1015227
Show More Cited By

A CORDIC processor for FFT computation and its implementation using gallium arsenide technology
1. Hardware
2. Mathematics of computing
  1. Mathematical analysis
    1. Numerical analysis

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Information

Published In

cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 6, Issue 1

March 1998

179 pages

ISSN:1063-8210

Issue’s Table of Contents

Copyright © 1998.

Publisher

IEEE Educational Activities Department

United States

Publication History

Published: 01 March 1998

Received: 03 February 1997

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Cited By

Chirkov GWentzlaff DGallivan KNikolopoulos DBeivide RGallopoulos E(2023)Seizing the Bandwidth Scaling of On-Package Interconnect in a Post-Moore's Law WorldProceedings of the 37th International Conference on Supercomputing10.1145/3577193.3593702(410-422)Online publication date: 21-Jun-2023
https://dl.acm.org/doi/10.1145/3577193.3593702
Saha PBanerjee ADandapat ABhattacharyya P(2011)ASIC implementation of high speed processor for calculating discrete Fourier transformation using circular convolution techniqueWSEAS Transactions on Circuits and Systems10.5555/2189899.218990210:8(278-288)Online publication date: 1-Aug-2011
https://dl.acm.org/doi/10.5555/2189899.2189902
Miyamoto NKarnan LMaruo KKotani KOhmi TImai M(2004)A small-area high-performance 512-point 2-dimensional FFT single-chip processorProceedings of the 2004 Asia and South Pacific Design Automation Conference10.5555/1015090.1015227(537-538)Online publication date: 27-Jan-2004
https://dl.acm.org/doi/10.5555/1015090.1015227
Kuo JWen CLin CWu A(2003)VLSI design of a variable-length FFT/IFFT processor for OFDM-based communication systemsEURASIP Journal on Advances in Signal Processing10.1155/S11108657033090602003(1306-1316)Online publication date: 1-Jan-2003
https://dl.acm.org/doi/10.1155/S1110865703309060

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