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research-article

The use of nanoelectronic devices in highly parallel computing systems

Authors:

Terry J. Fountain,

Michael J. B. Duff,

David G. Crawley,

Chris D. Tomlinson,

Colin D. MoffatAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 6, Issue 1

Pages 31 - 38

https://doi.org/10.1109/92.661242

Published: 01 March 1998 Publication History

Abstract

The continuing development of smaller electronic devices into the nanoelectronic regime offers great possibilities for the construction of highly parallel computers. This paper describes work designed to discover the best ways to take advantage of this opportunity. Simulated results are presented which indicate that improvements in clock rates of two orders of magnitude, and in packing density of three orders of magnitude, over the best current systems, should be attainable. These results apply to the class of data-parallel computers, and their attainment demands modifications to the design which are also described. Evaluation of the requirements of alternative classes of parallel architecture is currently under way, together with a study of the vitally important area of fault-tolerance.

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Cited By

Ghadamgahi SSabbaghi-Nadooshan RNavi K(2022)Novel single-trit comparator circuits in ternary quantum-dot cellular automataAnalog Integrated Circuits and Signal Processing10.1007/s10470-022-02030-1111:3(353-370)Online publication date: 1-Jun-2022
https://dl.acm.org/doi/10.1007/s10470-022-02030-1
Wang SWang LJain F(2009)Towards achieving reliable and high-performance nanocomputing via dynamic redundancy allocationACM Journal on Emerging Technologies in Computing Systems10.1145/1482613.14826155:1(1-21)Online publication date: 3-Feb-2009
https://dl.acm.org/doi/10.1145/1482613.1482615
Shuo Wang Lei Wang Faquir Jain (2007)Dynamic redundancy allocation for reliable and high-performance nanocomputingProceedings of the 2007 IEEE International Symposium on Nanoscale Architectures10.1109/NANOARCH.2007.4400850(1-6)Online publication date: 21-Oct-2007
https://dl.acm.org/doi/10.1109/NANOARCH.2007.4400850
Show More Cited By

The use of nanoelectronic devices in highly parallel computing systems
1. Theory of computation
  1. Models of computation
    1. Concurrency

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Information

Published In

cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 6, Issue 1

March 1998

179 pages

ISSN:1063-8210

Issue’s Table of Contents

Copyright © 1998.

Publisher

IEEE Educational Activities Department

United States

Publication History

Published: 01 March 1998

Received: 29 January 1997

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Cited By

Ghadamgahi SSabbaghi-Nadooshan RNavi K(2022)Novel single-trit comparator circuits in ternary quantum-dot cellular automataAnalog Integrated Circuits and Signal Processing10.1007/s10470-022-02030-1111:3(353-370)Online publication date: 1-Jun-2022
https://dl.acm.org/doi/10.1007/s10470-022-02030-1
Wang SWang LJain F(2009)Towards achieving reliable and high-performance nanocomputing via dynamic redundancy allocationACM Journal on Emerging Technologies in Computing Systems10.1145/1482613.14826155:1(1-21)Online publication date: 3-Feb-2009
https://dl.acm.org/doi/10.1145/1482613.1482615
Shuo Wang Lei Wang Faquir Jain (2007)Dynamic redundancy allocation for reliable and high-performance nanocomputingProceedings of the 2007 IEEE International Symposium on Nanoscale Architectures10.1109/NANOARCH.2007.4400850(1-6)Online publication date: 21-Oct-2007
https://dl.acm.org/doi/10.1109/NANOARCH.2007.4400850
Patwardhan JDwyer CLebeck ASorin D(2006)NANAACM Journal on Emerging Technologies in Computing Systems10.1145/1126257.11262582:1(1-30)Online publication date: 1-Jan-2006
https://dl.acm.org/doi/10.1145/1126257.1126258
Beckett PJennings A(2002)Towards nanocomputer architectureAustralian Computer Science Communications10.5555/563952.56395024:3(141-150)Online publication date: 1-Jan-2002
https://dl.acm.org/doi/10.5555/563952.563950
Beckett PJennings ALai FMorris JPose R(2002)Towards nanocomputer architectureProceedings of the seventh Asia-Pacific conference on Computer systems architecture10.5555/563933.563950(141-150)Online publication date: 1-Jan-2002
https://dl.acm.org/doi/10.5555/563933.563950
Glösekötter PPacha CGoser K(1999)Associative Matrix for Nano-Scale Integrated CircuitsProceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems10.5555/823462.824254Online publication date: 7-Apr-1999
https://dl.acm.org/doi/10.5555/823462.824254

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