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research-article

Accurate area and delay estimation from RTL descriptions

Authors:

Arvind Srinivasan,

David P. LaPotinAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 6, Issue 1

Pages 168 - 172

https://doi.org/10.1109/92.661259

Published: 01 March 1998 Publication History

Abstract

In this paper, we present a method for efficiently obtaining area and delay estimates from RTL descriptions of a logic design. The estimates are obtained through fast compiler-type optimizations on the RTL descriptions followed by application of best-fit polynomial area and delay models on the resulting technology-independent representation. The estimation techniques were incorporated into a tool called QUEST. QUEST was used by designers of a large commercial CPU to obtain quick feedback on the area and delay impact of behavioral modifications, resulting in significant savings in design schedule.

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Cited By

Strauch T(2023)MRPHS: A Verilog RTL to C++ Model Compiler Using Intermediate Representations for Object-oriented Model-driven PrototypingProceedings of the 34th International Workshop on Rapid System Prototyping10.1145/3625223.3649276(1-7)Online publication date: 21-Sep-2023
https://dl.acm.org/doi/10.1145/3625223.3649276
Sengupta PTyagi AChen YHu JMitra TYoung EXiong J(2022)How Good Is Your Verilog RTL Code?Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design10.1145/3508352.3549375(1-9)Online publication date: 30-Oct-2022
https://dl.acm.org/doi/10.1145/3508352.3549375
Büyükşahin KNajm FDe VIrwin MVerbauwhede IPiguet C(2002)High-level area estimationProceedings of the 2002 international symposium on Low power electronics and design10.1145/566408.566479(271-274)Online publication date: 12-Aug-2002
https://dl.acm.org/doi/10.1145/566408.566479
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Published In

cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 6, Issue 1

March 1998

179 pages

ISSN:1063-8210

Issue’s Table of Contents

Copyright © 1998.

Publisher

IEEE Educational Activities Department

United States

Publication History

Published: 01 March 1998

Revised: 19 December 1995

Received: 03 August 1994

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Cited By

Strauch T(2023)MRPHS: A Verilog RTL to C++ Model Compiler Using Intermediate Representations for Object-oriented Model-driven PrototypingProceedings of the 34th International Workshop on Rapid System Prototyping10.1145/3625223.3649276(1-7)Online publication date: 21-Sep-2023
https://dl.acm.org/doi/10.1145/3625223.3649276
Sengupta PTyagi AChen YHu JMitra TYoung EXiong J(2022)How Good Is Your Verilog RTL Code?Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design10.1145/3508352.3549375(1-9)Online publication date: 30-Oct-2022
https://dl.acm.org/doi/10.1145/3508352.3549375
Büyükşahin KNajm FDe VIrwin MVerbauwhede IPiguet C(2002)High-level area estimationProceedings of the 2002 international symposium on Low power electronics and design10.1145/566408.566479(271-274)Online publication date: 12-Aug-2002
https://dl.acm.org/doi/10.1145/566408.566479
Kao PHsieh CWu AGoto S(2001)An RTL design-space exploration method for high-level applicationsProceedings of the 2001 Asia and South Pacific Design Automation Conference10.1145/370155.370313(162-168)Online publication date: 30-Jan-2001
https://dl.acm.org/doi/10.1145/370155.370313
Nemani MNajm FChawla BBryant RRabaey J(1998)Delay estimation VLSI circuits from a high-level viewProceedings of the 35th annual Design Automation Conference10.1145/277044.277199(591-594)Online publication date: 1-May-1998
https://dl.acm.org/doi/10.1145/277044.277199

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