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Architectural optimization for low-power nonpipelined asynchronous systems

Authors:

Steven M. NowickAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 6, Issue 1

Pages 56 - 65

https://doi.org/10.1109/92.661247

Published: 01 March 1998 Publication History

Abstract

This paper presents an architectural optimization for low-power asynchronous systems. The optimization is targeted to nonpipelined computation. In particular, two new sequencing controllers are introduced, which significantly increase the throughput of the entire system. Data hazards may result in existing datapaths, when the new sequencers are used. To insure correct operation, new interlock mechanisms are introduced, for both dual-rail and single-rail implementations. The resulting increase in throughput can be traded for substantial system-wide power savings through application of voltage scaling. SPICE simulations show energy reduction by up to a factor of 2.4.

References

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Cited By

Taylor SEdwards DPlana LTarazona D(2010)Asynchronous data-driven circuit synthesisIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202016818:7(1093-1106)Online publication date: 1-Jul-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2020168
Plana LTaylor SEdwards D(2005)Attacking Control Overhead to Improve Synthesised Asynchronous Circuit PerformanceProceedings of the 2005 International Conference on Computer Design10.1109/ICCD.2005.31(703-710)Online publication date: 2-Oct-2005
https://dl.acm.org/doi/10.1109/ICCD.2005.31
Chelcea TNowick SAckland B(2002)Resynthesis and peephole transformations for the optimization of large-scale asynchronous systemsProceedings of the 39th annual Design Automation Conference10.1145/513918.514023(405-410)Online publication date: 10-Jun-2002
https://dl.acm.org/doi/10.1145/513918.514023

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Information

Published In

cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 6, Issue 1

March 1998

179 pages

ISSN:1063-8210

Issue’s Table of Contents

Copyright © 1998.

Publisher

IEEE Educational Activities Department

United States

Publication History

Published: 01 March 1998

Revised: 20 March 1997

Received: 04 September 1996

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Cited By

Taylor SEdwards DPlana LTarazona D(2010)Asynchronous data-driven circuit synthesisIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202016818:7(1093-1106)Online publication date: 1-Jul-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2020168
Plana LTaylor SEdwards D(2005)Attacking Control Overhead to Improve Synthesised Asynchronous Circuit PerformanceProceedings of the 2005 International Conference on Computer Design10.1109/ICCD.2005.31(703-710)Online publication date: 2-Oct-2005
https://dl.acm.org/doi/10.1109/ICCD.2005.31
Chelcea TNowick SAckland B(2002)Resynthesis and peephole transformations for the optimization of large-scale asynchronous systemsProceedings of the 39th annual Design Automation Conference10.1145/513918.514023(405-410)Online publication date: 10-Jun-2002
https://dl.acm.org/doi/10.1145/513918.514023

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