Cited By
View all- Sun DVinnakota BJiang WChawla BBryant RRabaey J(1998)Fast state verificationProceedings of the 35th annual Design Automation Conference10.1145/277044.277205(619-624)Online publication date: 1-May-1998
Fast fault translation
Pages 122 - 133
Abstract
Test generation algorithms may be classified by the level of circuit description they utilize. Algorithms based on a logic-gate level description of the circuit under test (CUT) are the most common. Functional algorithms utilize a functional description of the CUT. Functional test generation techniques may provide better defect coverages than do purely logic-level techniques. Multilevel test generation algorithms attempt to realize the advantages of both approaches by utilizing fault translation. Here, gate-level faults are translated to functional faults and test generation is performed at the functional level. In this paper, we develop and present new techniques for fast efficient fault translation from the logic to the functional level. These techniques are implemented in a multilevel sequential circuit test generation system. The performance of the system is investigated on benchmark circuits.
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- Fast fault translation
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Copyright © 1998.
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IEEE Educational Activities Department
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Publication History
Published: 01 March 1998
Revised: 15 December 1996
Received: 15 July 1995
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View all- Sun DVinnakota BJiang WChawla BBryant RRabaey J(1998)Fast state verificationProceedings of the 35th annual Design Automation Conference10.1145/277044.277205(619-624)Online publication date: 1-May-1998