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28th ASP-DAC 2023: Tokyo, Japan
- Atsushi Takahashi
:
Proceedings of the 28th Asia and South Pacific Design Automation Conference, ASPDAC 2023, Tokyo, Japan, January 16-19, 2023. ACM 2023, ISBN 978-1-4503-9783-4
Technical Program: Reliability Considerations for Emerging Computing and Memory Architectures
- Pavlos Stoikos, George Floros
A Fast Semi-Analytical Approach for Transient Electromigration Analysis of Interconnect Trees Using Matrix Exponential. 1-6 - Hong-Wen Chiou, Jia-Hao Jiang, Yu-Teng Chang, Yu-Min Lee, Chi-Wen Pan:
Chiplet Placement for 2.5D IC with Sequence Pair Based Tree and Thermal Consideration. 7-12 - Yu-Guang Chen, Po-Yeh Huang, Jin-Fu Li:
An On-Line Aging Detection and Tolerance Framework for Improving Reliability of STT-MRAMs. 13-18
Technical Program: Accelerators and Equivalence Checking
- Arighna Deb, Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh, Rolf Drechsler
Automated Equivalence Checking Method for Majority Based In-Memory Computing on ReRAM Crossbars. 19-25 - Yanzhao Wang
An Equivalence Checking Framework for Agile Hardware Design. 26-32 - Bowen Liu, Dajiang Liu:
Towards High-Bandwidth-Utilization SpMV on FPGAs via Partial Vector Duplication. 33-38
Technical Program: New Frontiers in Cyber-Physical and Autonomous Systems
- Xiangguo Liu, Ruochen Jiao, Bowen Zheng, Dave Liang, Qi Zhu:
Safety-Driven Interactive Planning for Neural Network-Based Lane Changing. 39-45 - Shengjie Xu
Safety-Aware Flexible Schedule Synthesis for Cyber-Physical Systems Using Weakly-Hard Constraints. 46-51 - Pin-Chun Chen, Xiangguo Liu, Chung-Wei Lin, Chao Huang, Qi Zhu:
Mixed-Traffic Intersection Management Utilizing Connected and Autonomous Vehicles as Traffic Regulators. 52-57
Technical Program: Machine Learning Assisted Optimization Techniques for Analog Circuits
- Chen-Chia Chang, Jingyu Pan, Zhiyao Xie, Yaguang Li, Yishuang Lin, Jiang Hu, Yiran Chen:
Fully Automated Machine Learning Model Development for Analog Placement Quality Prediction. 58-63 - Fábio Passos
Efficient Hierarchical mm-Wave System Synthesis with Embedded Accurate Transformer and Balun Machine Learning Models. 64-69 - Ahmet Faruk Budak, David Smart, Brian Swahn, David Z. Pan:
APOSTLE: Asynchronously Parallel Optimization for Sizing Analog Transistors Using DNN Learning. 70-75
Technical Program: Machine Learning for Reliable, Secure, and Cool Chips: A Journey from Transistors to Systems
- Hussam Amrouch, Florian Klemme:
ML to the Rescue: Reliability Estimation from Self-Heating and Aging in Transistors All the Way up Processors. 76-82 - Lilas Alrahis, Johann Knechtel, Ozgur Sinanoglu:
Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs. 83-90 - Jayeeta Chaudhuri, Krishnendu Chakrabarty:
Detection and Classification of Malicious Bitstreams for FPGAs in Cloud Computing. 91-97 - Jincong Lu
Learning Based Spatial Power Characterization and Full-Chip Power Estimation for Commercial TPUs. 98-103
Technical Program: High Performance Memory for Storage and Computing
- Yunpeng Song, Yina Lv, Liang Shi:
DECC: Differential ECC for Read Performance Optimization on High-Density NAND Flash Memory. 104-109 - Peng Hui, Edwin H.-M. Sha, Qingfeng Zhuge, Rui Xu, Han Wang:
Optimizing Data Layout for Racetrack Memory in Embedded Systems. 110-115 - Yanpeng Hu, Qisheng Jiang
Exploring Architectural Implications to Boost Performance for in-NVM B+-Tree. 116-121 - Yuqing Yang, Weidong Yang
An Efficient near-Bank Processing Architecture for Personalized Recommendation System. 122-127
Technical Program: Cool and Efficient Approximation
- Shuyuan Yu, Sheldon X.-D. Tan:
PAALM: Power Density Aware Approximate Logarithmic Multiplier Design. 128-133 - Chenyi Wen, Ying Wu, Xunzhao Yin, Cheng Zhuo:
Approximate Floating-Point FFT Design with Wide Precision-Range and High Energy Efficiency. 134-139 - Jingxiao Ma, Sherief Reda:
RUCA: RUntime Configurable Approximate Circuits with Self-Correcting Capability. 140-145 - Chun-Ting Lee, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang:
Approximate Logic Synthesis by Genetic Algorithm with an Error Rate Guarantee. 146-151
Technical Program: Logic Synthesis for AQFP, Quantum Logic, AI Driven and Efficient Data Layout for HBM
- Alessandro Tempia Calvino, Giovanni De Micheli:
Depth-Optimal Buffer and Splitter Insertion and Optimization in AQFP Circuits. 152-158 - Guanglei Zhou, Jason Helge Anderson:
Area-Driven FPGA Logic Synthesis Using Reinforcement Learning. 159-165 - Yung-Chih Chen, Feng-Jie Chao:
Optimization of Reversible Logic Networks with Gate Sharing. 166-171 - Stephanie Soldavini, Donatella Sciuto, Christian Pilato:
Iris: Automatic Generation of Efficient Data Layouts for High Bandwidth Utilization. 172-177
Technical Program: University Design Contest
- Yu Zhang, Gang Chen, Tao He, Qian Huang, Kai Huang:
ViraEye: An Energy-Efficient Stereo Vision Accelerator with Binary Neural Network in 55 nm CMOS. 178-179 - Rei Sumikawa, Kota Shiba, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda:
A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-Linear Function Blocks in 0.18μm CMOS. 180-181 - Yao-Chung Hsu, Atsutake Kosuge, Rei Sumikawa, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda:
A Fully Synthesized 13.7μJ/Prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network. 182-183 - Kamel-Eddine Harabi, Clement Türck, Marie Drouhin, Adrien Renaudineau, Thomas Bersani-Veroni, Damien Querlioz, Tifenn Hirtzlin, Elisa Vianello, Marc Bocquet, Jean-Michel Portal:
A Multimode Hybrid Memristor-CMOS Prototyping Platform Supporting Digital and Analog Projects. 184-185 - Shun Yamaguchi, Mahfuzul Islam
A Fully Synchronous Digital LDO with Built-in Adaptive Frequency Modulation and Implicit Dead-Zone Control. 186-187 - Mahfuzul Islam
Demonstration of Order Statistics Based Flash ADC in a 65nm Process. 188-189
Technical Program: Synthesis of Quantum Circuits and Systems
- Sarah Schneider, Lukas Burgholzer
A SAT Encoding for Optimal Clifford Circuit Synthesis. 190-195 - Kyohei Seino, Shigeru Yamashita:
An SMT-Solver-Based Synthesis of NNA-Compliant Quantum Circuits Consisting of CNOT, H and T Gates. 196-201 - Kevin Mato, Martin Ringbauer
Compilation of Entangling Gates for High-Dimensional Quantum Systems. 202-208 - Wang Liao, Yasunari Suzuki, Teruo Tanimoto, Yosuke Ueno
WIT-Greedy: Hardware System Design of Weighted ITerative Greedy Decoder for Surface Code. 209-215 - Daniel Volya
Quantum Data Compression for Efficient Generation of Control Pulses. 216-221
Technical Program: In-Memory/Near-Memory Computing for Neural Networks
- Yueting Li, He Zhang, Xueyan Wang, Hao Cai, Yundong Zhang, Shuqin Lv, Renguang Liu, Weisheng Zhao:
Toward Energy-Efficient Sparse Matrix-Vector Multiplication with near STT-MRAM Computing Architecture. 222-227 - Peiyu Chen, Meng Wu, Yufei Ma, Le Ye, Ru Huang:
RIMAC: An Array-Level ADC/DAC-Free ReRAM-Based in-Memory DNN Processor with Analog Cache and Computation. 228-233 - Shuo Huai
Crossbar-Aligned & Integer-Only Neural Network Compression for Efficient in-Memory Acceleration. 234-239 - Muhammad Rashedul Haq Rashed
Discovering the in-Memory Kernels of 3D Dot-Product Engines. 240-245 - Jingyu He, Yucong Huang, Miguel Angel Lastras-Montaño, Terry Tao Ye
RVComp: Analog Variation Compensation for RRAM-Based in-Memory Computing. 246-251
Technical Program: Machine Learning-Based Design Automation
- Chen-Chia Chang, Jingyu Pan, Zhiyao Xie, Jiang Hu, Yiran Chen:
Rethink before Releasing Your Model: ML Model Extraction Attack in EDA. 252-257 - Yifan Chen, Jing Mai, Xiaohan Gao, Muhan Zhang, Yibo Lin:
MacroRank: Ranking Macro Placement Solutions Leveraging Translation Equivariancy. 258-263 - Rongjian Liang
BufFormer: A Generative ML Framework for Scalable Buffering. 264-270 - Daijoon Hyun, Younggwang Jung, Insu Cho, Youngsoo Shin:
Decoupling Capacitor Insertion Minimizing IR-Drop Violations and Routing DRVs. 271-276 - Yeu-Haw Yeh, Simon Yi-Hung Chen, Hung-Ming Chen, Deng-Yao Tu, Guan-Qi Fang, Yun-Chih Kuo, Po-Yang Chen:
DPRoute: Deep Learning Framework for Package Routing. 277-282
Technical Program: Advanced Techniques for Yields, Low Power and Reliability
- Shuo Yin, Guohao Dai, Wei W. Xing
High-Dimensional Yield Estimation Using Shrinkage Deep Features and Maximization of Integral Entropy Reduction. 283-289 - Hung-Chun Lin, Shao-Yun Fang:
MIA-Aware Detailed Placement and VT Reassignment for Leakage Power Optimization. 290-295 - Junchi Ma
SLOGAN: SDC Probability Estimation Using Structured Graph Attention Network. 296-301
Technical Program: Microarchitectural Design and Neural Networks
- Jianwang Zhai, Yici Cai, Bei Yu:
Microarchitecture Power Modeling via Artificial Neural Network and Transfer Learning. 302-307 - Hui Chen, Di Liu, Shiqing Li, Shuo Huai
MUGNoC: A Software-Configured Multicast-Unicast-Gather NoC for Accelerating CNN Dataflows. 308-313 - Bo-Wun Cheng, En-Ming Huang
COLAB: Collaborative and Efficient Processing of Replicated Cache Requests in GPU. 314-319
Technical Program: Novel Techniques for Scheduling and Memory Optimizations in Embedded Software
- Federico Reghenzani
Mixed-Criticality with Integer Multiple WCETs and Dropping Relations: New Scheduling Challenges. 320-325 - Thilanka Thilakasiri
An Exact Schedulability Analysis for Global Fixed-Priority Scheduling of the AER Task Model. 326-332 - Syue-Wei Lu, Shuo-Han Chen, Yu-Pei Liang, Yuan-Hao Chang, Kang Wang, Tseng-Yi Chen, Wei-Kuan Shih:
Skyrmion Vault: Maximizing Skyrmion Lifespan for Enabling Low-Power Skyrmion Racetrack Memory. 333-338
Technical Program: Efficient Circuit Simulation and Synthesis for Analog Designs
- Lingjie Li
Parallel Incomplete LU Factorization Based Iterative Solver for Fixed-Structure Linear Equations in Circuit Simulation. 339-345 - Jiechen Huang
Accelerated Capacitance Simulation of 3-D Structures with Considerable Amounts of General Floating Metals. 346-351 - Cheng-Yu Chiang, Chia-Lin Hu, Mark Po-Hung Lin
On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC. 352-357
Technical Program: Security of Heterogeneous Systems Containing FPGAs
- Mathieu Gross, Jonas Krautter, Dennis Gnad, Michael Gruber, Georg Sigl, Mehdi B. Tahoori:
FPGANeedle: Precise Remote Fault Attacks from FPGA to CPU. 358-364 - Darshana Jayasinghe, Brian Udugama, Sri Parameswaran:
FPGA Based Countermeasures against Side Channel Attacks on Block Ciphers. 365-371
Technical Program: Novel Application & Architecture-Specific Quantization Techniques
- Ruoyang Liu, Chenhan Wei
Block-Wise Dynamic-Precision Neural Network Training Acceleration via Online Quantization Sensitivity Analytics. 372-377 - Qing Lu, Weiwen Jiang, Xiaowei Xu, Jingtong Hu, Yiyu Shi:
Quantization through Search: A Novel Scheme to Quantize Convolutional Neural Networks in Finite Weight Space. 378-383 - Ying Zhu, Min Liu, Lu Xu, Lei Wang, Xi Xiao, Shaohua Yu:
Multi-Wavelength Parallel Training and Quantization-Aware Tuning for WDM-Based Optical Convolutional Neural Networks Considering Wavelength-Relative Deviations. 384-389 - Xiaoyu Feng, Chen Tang, Zongkai Zhang, Wenyu Sun, Yongpan Liu:
Semantic Guided Fine-Grained Point Cloud Quantization Framework for 3D Object Detection. 390-395
Technical Program: Approximate Brain-Inspired Architectures for Efficient Learning
- Ali BanaGozar, Seyed Hossein Hashemi Shadmehri, Sander Stuijk
ReMeCo: Reliable Memristor-Based in-Memory Neuromorphic Computation. 396-401 - Rohit Ranjan, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar:
SyFAxO-GeN: Synthesizing FPGA-Based Approximate Operators with Generative Networks. 402-409 - Prattay Chowdhury, Jorge Castro-Godínez, Benjamin Carrion Schafer:
Approximating HW Accelerators through Partial Extractions onto Shared Artificial Neural Networks. 410-415 - Dehua Liang
DependableHD: A Hyperdimensional Learning Framework for Edge-Oriented Voltage-Scaled Circuits. 416-422
Technical Program: Retrospect and Prospect of Verifiation and Test Technologies
- Rune Krauss
EDDY: A Multi-Core BDD Package with Dynamic Memory Management and Reduced Fragmentation. 423-428 - Lukas Burgholzer
Exploiting Reversible Computing for Verification: Potential, Possible Paths, and Consequences. 429-435 - Dina A. Moussa, Michael Hefenbrock, Christopher Münch, Mehdi B. Tahoori:
Automatic Test Pattern Generation and Compaction for Deep Neural Networks. 436-441 - Takuma Nagao, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki, Michiko Inoue, Michihiro Shintani:
Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects. 442-448
Technical Program: Computing, Erasing, and Protecting: The Security Challenges for the Next Generation of Memories
- Simranjeet Singh
Hardware Security Primitives Using Passive RRAM Crossbar Array: Novel TRNG and PUF Designs. 449-454 - Aya Fukami, Francesco Regazzoni
Data Sanitization on eMMCs. 455-460 - Onur Mutlu, Ataberk Olgun, Abdullah Giray Yaglikçi:
Fundamentally Understanding and Solving RowHammer. 461-468
Technical Program: System-Level Codesign in DNN Accelerators
- Tom Glint
Hardware-Software Codesign of DNN Accelerators Using Approximate Posit Multipliers. 469-474 - Susmita Dey Manasi, Suvadeep Banerjee, Abhijit Davare, Anton A. Sorokin, Steven M. Burns, Desmond A. Kirkpatrick, Sachin S. Sapatnekar:
Reusing GEMM Hardware for Efficient Execution of Depthwise Separable Convolution on ASIC-Based DNN Accelerators. 475-482 - Mohammadhossein Askarihemmat, Sean Wagner, Olexa Bilaniuk, Yassine Hariri, Yvon Savaria, Jean-Pierre David:
BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU. 483-489 - Zicheng He
Agile Hardware and Software Co-Design for RISC-V-Based Multi-Precision Deep Learning Microprocessor. 490-495
Technical Program: New Advances in Hardware Trojan Detection
- Zhixin Pan, Prabhat Mishra
Hardware Trojan Detection Using Shapley Ensemble Boosting. 496-503 - Guangxin Guo
ASSURER: A PPA-friendly Security Closure Framework for Physical Design. 504-509 - Haoyi Wang, Qiang Zhou, Yici Cai:
Static Probability Analysis Guided RTL Hardware Trojan Test Generation. 510-515 - Haoyu Wang
Hardware Trojan Detection and High-Precision Localization in NoC-Based MPSoC Using Machine Learning. 516-521
Technical Program: Advances in Physical Design and Timing Analysis
- Dan Zheng, Evangeline F. Y. Young:
An Integrated Circuit Partitioning and TDM Assignment Optimization Framework for Multi-FPGA Systems. 522-528 - Jiarui Wang, Jing Mai, Zhixiong Di, Yibo Lin:
A Robust FPGA Router with Concurrent Intra-CLB Rerouting. 529-534 - Chuandong Chen, Dishi Lin, Rongshan Wei, Qinghai Liu, Ziran Zhu, Jianli Chen:
Efficient Global Optimization for Large Scaled Ordered Escape Routing. 535-540 - Shengkun Wu, Biwei Xie, Xingquan Li
An Adaptive Partition Strategy of Galerkin Boundary Element Method for Capacitance Extraction. 541-546 - Yuyang Ye
Graph-Learning-Driven Path-Based Timing Analysis Results Predictor from Graph-Based Timing Analysis. 547-552
Technical Program: Brain-Inspired Hyperdimensional Computing to the Rescue for Beyond von Neumann Era
- Hussam Amrouch, Paul R. Genssler, Mohsen Imani, Mariam Issa, Xun Jiao, Wegdan Mohammad, Gloria Sepanta, Ruixuan Wang:
Beyond von Neumann Era: Brain-Inspired Hyperdimensional Computing to the Rescue. 553-560
Technical Program: System Level Design Space Exploration
- Rafael Medina
System-Level Exploration of In-Package Wireless Communication for Multi-Chiplet Platforms. 561-566 - Yuchao Liao
Efficient System-Level Design Space Exploration for High-Level Synthesis Using Pareto-Optimal Subspace Pruning. 567-572 - Bryce Orloski, Samuel Coward, Theo Drane:
Automatic Generation of Complete Polynomial Interpolation Design Space for Hardware Architectures. 573-578
Technical Program: Security Assurance and Acceleration
- Hasan Al Shaikh, Arash Vafaei, Mridha Md Mashahedur Rahman, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor:
SHarPen: SoC Security Verification by Hardware Penetration Test. 579-584 - Shang Shi, Nitin Pundir
SecHLS: Enabling Security Awareness in High-Level Synthesis. 585-590 - Francesco Antognazza
A Flexible ASIC-Oriented Design for a Full NTRU Accelerator. 591-597
Technical Program: Hardware and Software Co-Design of Emerging Machine Learning Algorithms
- Dongning Ma, Sizhe Zhang, Xun Jiao:
Robust Hyperdimensional Computing against Cyber Attacks and Hardware Errors: A Survey. 598-605 - Dayane Reis
In-Memory Computing Accelerators for Emerging Learning Paradigms. 606-611 - Yi Sheng, Junhuan Yang, Weiwen Jiang, Lei Yang:
Toward Fair and Efficient Hyperdimensional Computing. 612-617
Technical Program: Full-Stack Co-Design for on-Chip Learning in AI Systems
- Xiaoxuan Yang
Improving the Robustness and Efficiency of PIM-Based Architecture by SW/HW Co-Design. 618-623 - M. Lakshmi Varshika, Abhishek Kumar Mishra, Nagarajan Kandasamy, Anup Das:
Hardware-Software Co-Design for On-Chip Learning in AI Systems. 624-631 - Vito Giovanni Castellana, Nicolas Bohm Agostini
Towards On-Chip Learning for Low Latency Reasoning with End-to-End Synthesis. 632-638
Technical Program: Energy-Efficient Computing for Emerging Applications
- Mahabubul Alam, Satwik Kundu, Swaroop Ghosh:
Knowledge Distillation in Quantum Neural Network Using Approximate Synthesis. 639-644 - Wentao Hou, Kai Zhong, Shulin Zeng, Guohao Dai, Huazhong Yang, Yu Wang:
NTGAT: A Graph Attention Network Accelerator with Runtime Node Tailoring. 645-650 - Pai-Yu Tan
A Low-Bitwidth Integer-STBP Algorithm for Efficient Training and Inference of Spiking Neural Networks. 651-656 - Alireza Amirshahi, Joshua Alexander Harrison Klein, Giovanni Ansaloni, David Atienza:
TiC-SAT: Tightly-Coupled Systolic Accelerator for Transformers. 657-663
Technical Program: Side-Channel Attacks and RISC-V Security
- Pengfei Qiu, Qiang Gao, Dongsheng Wang, Yongqiang Lyu, Chunlu Wang, Chang Liu, Rihui Sun, Gang Qu:
PMU-Leaker: Performance Monitor Unit-Based Realization of Cache Side-Channel Attacks. 664-669 - Ya Gao, Qizhi Zhang, Haocheng Ma, Jiaji He, Yiqiang Zhao:
EO-Shield: A Multi-Function Protection Scheme against Side Channel and Focused Ion Beam Attacks. 670-675 - Johannes Geier
CompaSeC: A Compiler-Assisted Security Countermeasure to Address Instruction Skip Fault Attacks on RISC-V. 676-682 - Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler
Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - A RISC-V Case Study. 683-689
Technical Program: Simulation and Verification of Quantum Circuits
- Jaekyung Im, Seokhyeong Kang:
Graph Partitioning Approach for Fast Quantum Circuit Simulation. 690-695 - Hsiao-Lun Liu, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang:
A Robust Approach to Detecting Non-Equivalent Quantum Circuits Using Specially Designed Stimuli. 696-701 - Tom Peham
Equivalence Checking of Parameterized Quantum Circuits: Verifying the Compilation of Variational Quantum Algorithms. 702-708 - Lucas Berent
Software Tools for Decoding Quantum Low-Density Parity-Check Codes. 709-714
Technical Program: Learning x Security in DFM
- Haoyu Yang, Haoxing Ren:
Enabling Scalable AI Computational Lithography with Physics-Inspired Models. 715-720 - Hao-Chiang Shao
Data-Driven Approaches for Process Simulation and Optical Proximity Correction. 721-726 - Hao Geng, Qi Sun, Tinghuan Chen, Qi Xu, Tsung-Yi Ho, Bei Yu:
Mixed-Type Wafer Failure Pattern Recognition. 727-732
Technical Program: Lightweight Models for Edge AI
- Bosheng Liu, Hongyi Liang, Jigang Wu, Xiaoming Chen, Peng Liu, Yinhe Han:
Accelerating Convolutional Neural Networks in Frequency Domain via Kernel-Sharing Approach. 733-738 - Yunhung Gao, Hongyan Li, Kevin Zhang, Xueru Yu, Hang Lu:
Mortar: Morphing the Bit Level Sparsity for General Purpose Deep Learning Acceleration. 739-744 - Yimeng Zhang
Data-Model-Circuit Tri-Design for Ultra-Light Video Intelligence on Edge Devices. 745-750 - Tianen Chen, Noah Anderson, Younghyun Kim:
Latent Weight-Based Pruning for Small Binary Neural Networks. 751-756
Technical Program: Design Automation for Emerging Devices
- Tianliang Ma, Zhihui Deng, Leilai Shao:
AutoFlex: Unified Evaluation and Design Framework for Flexible Hybrid Electronics. 757-762 - Chenlin Shi
CNFET7: An Open Source Cell Library for 7-nm CNFET Technology. 763-768 - Rongliang Fu, Mengmeng Wang, Yirong Kan, Nobuyuki Yoshikawa, Tsung-Yi Ho, Olivia Chen
A Global Optimization Algorithm for Buffer and Splitter Insertion in Adiabatic Quantum-Flux-Parametron Circuits. 769-774 - Sven Thijssen, Sumit Kumar Jha, Rickard Ewetz:
FLOW-3D: Flow-Based Computing on 3D Nanoscale Crossbars with Minimal Semiperimeter. 775-780
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