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Decoupling Capacitor Insertion Minimizing IR-Drop Violations and Routing DRVs

Authors:

Younggwang Jung,

Youngsoo ShinAuthors Info & Claims

ASPDAC '23: Proceedings of the 28th Asia and South Pacific Design Automation Conference

Pages 271 - 276

https://doi.org/10.1145/3566097.3567905

Published: 31 January 2023 Publication History

Abstract

Decoupling capacitor (decap) cells are inserted near function cells of high switching activities so that their IR-drop can be suppressed. Their design becomes more complex and uses higher metal layers, thereby starting to manifest themselves as routing blockage. Post-placement decap insertion, with a goal of minimizing both IR-drop violations and routing design rule violations (DRVs), is addressed for the first time. U-Net with graph convolutional network is introduced to predict routing DRV penalty. The decap insertion problem is formulated and a heuristic algorithm is presented. Experiments with a few test circuits demonstrate that DRVs are reduced by 16% on average with no IR-drop violations, compared to a conventional method which does not explicitly consider DRVs. This results in 48% reduction in routing runtime and 23% improvement in total negative slack.

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Cited By

Chai ZZhao YLiu WLin YWang RHuang R(2023)CircuitNet: An Open-Source Dataset for Machine Learning in VLSI CAD Applications With Improved Domain-Specific Evaluation Metric and Learning StrategiesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.328797042:12(5034-5047)Online publication date: Dec-2023
https://doi.org/10.1109/TCAD.2023.3287970
Jung YHyun DChoi SShin Y(2023)Power Distribution Network Optimization Using HLA-GCN for Routability Enhancement2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323833(1-8)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323833

Index Terms

Decoupling Capacitor Insertion Minimizing IR-Drop Violations and Routing DRVs
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Wire routing
  2. Power and energy
    1. Power estimation and optimization
      1. Circuits power issues

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cover image ACM Conferences

ASPDAC '23: Proceedings of the 28th Asia and South Pacific Design Automation Conference

January 2023

807 pages

ISBN:9781450397834

DOI:10.1145/3566097

General Chair:
Atsushi Takahashi
Tokyo Institute of Technology

Copyright © 2023 ACM.

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 31 January 2023

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This work was supported in part by the Institute of Information and communications Technology Planning and Evaluation (IITP) grant funded by the Korea Government (MSIT) through Software Systems for AI Semiconductor Design under Grant 2021-0-00754, and in part by Synopsys. The EDA tool was supported by the IC Design Education Center (IDEC), Korea.

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ASPDAC '23

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SIGDA

ASPDAC '23: 28th Asia and South Pacific Design Automation Conference

January 16 - 19, 2023

Tokyo, Japan

Acceptance Rates

ASPDAC '23 Paper Acceptance Rate 102 of 328 submissions, 31%;

Overall Acceptance Rate 466 of 1,454 submissions, 32%

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ASPDAC '25

Sponsor:
sigda

30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

Tokyo , Japan

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Cited By

Chai ZZhao YLiu WLin YWang RHuang R(2023)CircuitNet: An Open-Source Dataset for Machine Learning in VLSI CAD Applications With Improved Domain-Specific Evaluation Metric and Learning StrategiesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.328797042:12(5034-5047)Online publication date: Dec-2023
https://doi.org/10.1109/TCAD.2023.3287970
Jung YHyun DChoi SShin Y(2023)Power Distribution Network Optimization Using HLA-GCN for Routability Enhancement2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323833(1-8)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323833

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