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Fully Automated Machine Learning Model Development for Analog Placement Quality Prediction

Authors:

Chen-Chia Chang,

Yiran ChenAuthors Info & Claims

ASPDAC '23: Proceedings of the 28th Asia and South Pacific Design Automation Conference

Pages 58 - 63

https://doi.org/10.1145/3566097.3567881

Published: 31 January 2023 Publication History

Abstract

Analog integrated circuit (IC) placement is a heavily manual and time-consuming task that has a significant impact on chip quality. Several recent studies apply machine learning (ML) techniques to directly predict the impact of placement on circuit performance or even guide the placement process. However, the significant diversity in analog design topologies can lead to different impacts on performance metrics (e.g., common-mode rejection ratio (CMRR) or offset voltage). Thus, it is unlikely that the same ML model structure will achieve the best performance for all designs and metrics. In addition, customizing ML models for different designs require more tremendous engineering efforts and longer development cycles. In this work, we leverage Neural Architecture Search (NAS) to automatically develop customized neural architectures for different analog circuit designs and metrics. Our proposed NAS methodology supports an unconstrained DAG-based search space containing a wide range of ML operations and topological connections. Our search strategy can efficiently explore this flexible search space and provide every design with the best-customized model to boost the model performance. We make unprejudiced comparisons with the claimed performance of the previous representative work on exactly the same dataset. After fully automated development within only 0.5 days, generated models give 3.61% superior accuracy than the prior art.

References

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Cited By

Martins R(2024)Closing the Gap between Electrical and Physical Design Steps with an Analog IC Placement Optimizer Enhanced with Machine-Learning-Based Post-Layout Performance RegressorsElectronics10.3390/electronics1322436013:22(4360)Online publication date: 6-Nov-2024
https://doi.org/10.3390/electronics13224360
Martins RGusmão AVieira RPassos FLourenço NHorta N(2024)Ponderous: A Performance-driven Analog IC Placement Optimizer Leveraged by a ML Pipeline2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)10.1109/SMACD61181.2024.10745469(1-4)Online publication date: 2-Jul-2024
https://doi.org/10.1109/SMACD61181.2024.10745469

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Fully Automated Machine Learning Model Development for Analog Placement Quality Prediction

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cover image ACM Conferences

ASPDAC '23: Proceedings of the 28th Asia and South Pacific Design Automation Conference

January 2023

807 pages

ISBN:9781450397834

DOI:10.1145/3566097

General Chair:
Atsushi Takahashi
Tokyo Institute of Technology

Copyright © 2023 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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New York, NY, United States

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Published: 31 January 2023

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ASPDAC '23

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SIGDA

ASPDAC '23: 28th Asia and South Pacific Design Automation Conference

January 16 - 19, 2023

Tokyo, Japan

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ASPDAC '23 Paper Acceptance Rate 102 of 328 submissions, 31%;

Overall Acceptance Rate 466 of 1,454 submissions, 32%

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ASPDAC '25

Sponsor:
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30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

Tokyo , Japan

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Cited By

Martins R(2024)Closing the Gap between Electrical and Physical Design Steps with an Analog IC Placement Optimizer Enhanced with Machine-Learning-Based Post-Layout Performance RegressorsElectronics10.3390/electronics1322436013:22(4360)Online publication date: 6-Nov-2024
https://doi.org/10.3390/electronics13224360
Martins RGusmão AVieira RPassos FLourenço NHorta N(2024)Ponderous: A Performance-driven Analog IC Placement Optimizer Leveraged by a ML Pipeline2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)10.1109/SMACD61181.2024.10745469(1-4)Online publication date: 2-Jul-2024
https://doi.org/10.1109/SMACD61181.2024.10745469

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