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Rethink before Releasing Your Model: ML Model Extraction Attack in EDA

Published: 31 January 2023 Publication History

Abstract

Machine learning (ML)-based techniques for electronic design automation (EDA) have boosted the performance of modern integrated circuits (ICs). Such achievement makes ML model to be of importance for the EDA industry. In addition, ML models for EDA are widely considered having high development cost because of the time-consuming and complicated training data generation process. Thus, confidentiality protection for EDA models is a critical issue. However, an adversary could apply model extraction attacks to steal the model in the sense of achieving the comparable performance to the victim's model. As model extraction attacks have posed great threats to other application domains, e.g., computer vision and natural language process, in this paper, we study model extraction attacks for EDA models under two real-world scenarios. It is the first work that (1) introduces model extraction attacks on EDA models and (2) proposes two attack methods against the unlimited and limited query budget scenarios. Our results show that our approach can achieve competitive performance with the well-trained victim model without any performance degradation. Based on the results, we demonstrate that model extraction attacks truly threaten the EDA model privacy and hope to raise concerns about ML security issues in EDA.

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Cited By

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  • (2023)Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLsElectronics10.3390/electronics1220434012:20(4340)Online publication date: 19-Oct-2023
  • (2023)Security and Reliability Challenges in Machine Learning for EDA: Latest Advances2023 24th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED57927.2023.10129359(1-6)Online publication date: 5-Apr-2023
  • (2023)Extracting Knowledge from Incompletely Known ModelsIntelligent Data Engineering and Automated Learning – IDEAL 202310.1007/978-3-031-48232-8_24(257-268)Online publication date: 22-Nov-2023

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          cover image ACM Conferences
          ASPDAC '23: Proceedings of the 28th Asia and South Pacific Design Automation Conference
          January 2023
          807 pages
          ISBN:9781450397834
          DOI:10.1145/3566097
          Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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          Published: 31 January 2023

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          ASPDAC '23 Paper Acceptance Rate 102 of 328 submissions, 31%;
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          View all
          • (2023)Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLsElectronics10.3390/electronics1220434012:20(4340)Online publication date: 19-Oct-2023
          • (2023)Security and Reliability Challenges in Machine Learning for EDA: Latest Advances2023 24th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED57927.2023.10129359(1-6)Online publication date: 5-Apr-2023
          • (2023)Extracting Knowledge from Incompletely Known ModelsIntelligent Data Engineering and Automated Learning – IDEAL 202310.1007/978-3-031-48232-8_24(257-268)Online publication date: 22-Nov-2023

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