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Hui Chen 0016
Person information
- affiliation: Nanyang Technological University, HP-NTU Digital Manufacturing Corporate Lab, Singapore
Other persons with the same name
- Hui Chen — disambiguation page
- Hui Chen 0001
— City University of New York, Brooklyn College, Department of Computer and Information Science, NY, USA (and 3 more)
- Hui Chen 0002
- Hui Chen 0003
- Hui Chen 0004
- Hui Chen 0005 — Huazhong University of Science and Technology, Department of Control Science and Engineering, Wuhan, China
- Hui Chen 0006
- Hui Chen 0007
- Hui Chen 0008
- Hui Chen 0009
- Hui Chen 0010
- Hui Chen 0011 — Chinese University of Hong Kong
- Hui Chen 0012 — Hong Kong Polytechnic University, Department of Computing, China (and 1 more)
- Hui Chen 0013
- Hui Chen 0014
- Hui Chen 0015
- Hui Chen 0017
- Hui Chen 0018 — Alibaba Group, Hangzhou, China
- Hui Chen 0019 — University of California, Riverside, CA, USA
- Hui Chen 0020
- Hui Chen 0021
- Hui Chen 0022
- Hui Chen 0023 — Singapore University of Technology and Design, Singapore
- Hui Chen 0024
- Hui Chen 0025
- Hui Chen 0026
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2020 – today
- 2024
- [j11]Peng Chen
DAG-Order: An Order-Based Dynamic DAG Scheduling for Real-Time Networks-on-Chip. ACM Trans. Archit. Code Optim. 21(1): 2:1-2:24 (2024) - [c9]Xiangzhong Luo, Di Liu, Hao Kong, Shuo Huai, Hui Chen, Shiqing Li, Guochu Xiong, Weichen Liu:
Pearls Hide Behind Linearity: Simplifying Deep Convolutional Networks for Embedded Hardware Systems via Linearity Grafting. ASPDAC 2024: 250-255 - [i4]Xiangzhong Luo, Di Liu, Hao Kong, Shuo Huai, Hui Chen, Guochu Xiong, Weichen Liu:
Efficient Deep Learning Infrastructures for Embedded Computing Systems: A Comprehensive Survey and Future Envision. CoRR abs/2411.01431 (2024) - 2023
- [j10]Xiangzhong Luo
SurgeNAS: A Comprehensive Surgery on Hardware-Aware Differentiable Neural Architecture Search. IEEE Trans. Computers 72(4): 1081-1094 (2023) - [j9]Shien Zhu
FAT: An In-Memory Accelerator With Fast Addition for Ternary Weight Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(3): 781-794 (2023) - [j8]Xiangzhong Luo
LightNAS: On Lightweight and Scalable Neural Architecture Search for Embedded Platforms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(6): 1784-1797 (2023) - [c8]Shuo Huai
Crossbar-Aligned & Integer-Only Neural Network Compression for Efficient in-Memory Acceleration. ASP-DAC 2023: 234-239 - [c7]Hui Chen, Di Liu, Shiqing Li, Shuo Huai
MUGNoC: A Software-Configured Multicast-Unicast-Gather NoC for Accelerating CNN Dataflows. ASP-DAC 2023: 308-313 - [c6]Hui Chen, Xiaoqiang Wu, Lei Dai, Yang Liu:
Brief Industry Paper: Latency-Driven Optimization of Instruction Blocks Orchestration on Memory. RTSS 2023: 463-467 - 2022
- [b1]Hui Chen:
Hardware-software co-design and optimization for point-to-point network-on-chip based many-core systems. Nanyang Technological University, Singapore, 2022 - [j7]Hao Kong
EDLAB: A Benchmark for Edge Deep Learning Accelerators. IEEE Des. Test 39(3): 8-17 (2022) - [j6]Peng Chen
Contention Minimization in Emerging SMART NoC via Direct and Indirect Routes. IEEE Trans. Computers 71(8): 1874-1888 (2022) - [j5]Hui Chen
ArSMART: An Improved SMART NoC Design Supporting Arbitrary-Turn Transmission. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1316-1329 (2022) - [j4]Xiangzhong Luo
Designing Efficient DNNs via Hardware-Aware Neural Architecture Search and Beyond. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(6): 1799-1812 (2022) - [j3]Hui Chen
LAMP: Load-Balanced Multipath Parallel Transmission in Point-to-Point NoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5232-5245 (2022) - [c5]Xiangzhong Luo, Di Liu, Hao Kong, Shuo Huai, Hui Chen, Weichen Liu:
Work-in-Progress: What to Expect of Early Training Statistics? An Investigation on Hardware-Aware Neural Architecture Search. CODES+ISSS 2022: 1-2 - [c4]Xiangzhong Luo, Di Liu, Hao Kong, Shuo Huai, Hui Chen, Weichen Liu:
You only search once: on lightweight differentiable architecture search for resource-constrained embedded platforms. DAC 2022: 475-480 - [c3]Jiale Chen, Xiaoqiang Wu, Debayan Roy, Hui Chen, Ping Xiang, Wenzhuo Zhang, Yuhong Feng, Wanli Chang:
Latency-driven Optimization of Switching Pipeline Design in Network Chips. RTSS 2022: 344-355 - [i3]Shien Zhu, Luan H. K. Duong, Hui Chen, Di Liu, Weichen Liu:
FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks. CoRR abs/2201.07634 (2022) - [i2]Xiangzhong Luo, Di Liu, Hao Kong, Shuo Huai, Hui Chen, Weichen Liu:
You Only Search Once: On Lightweight Differentiable Architecture Search for Resource-Constrained Embedded Platforms. CoRR abs/2208.14446 (2022) - 2021
- [j2]Peng Chen
Reduced Worst-Case Communication Latency Using Single-Cycle Multihop Traversal Network-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(7): 1381-1394 (2021) - [j1]Hui Chen, Zihao Zhang, Peng Chen, Xiangzhong Luo, Shiqing Li, Weichen Liu:
MARCO: A High-performance Task Mapping and Routing Co-optimization Framework for Point-to-Point NoC-based Heterogeneous Computing Systems. ACM Trans. Embed. Comput. Syst. 20(5s): 54:1-54:21 (2021) - [c2]Hui Chen, Zihao Zhang, Peng Chen, Shien Zhu
Parallel Multipath Transmission for Burst Traffic Optimization in Point-to-Point NoCs. ACM Great Lakes Symposium on VLSI 2021: 289-294 - [c1]Peng Chen, Hui Chen, Jun Zhou, Di Liu, Shiqing Li, Weichen Liu, Wanli Chang, Nan Guan
Partial order based non-preemptive communication scheduling towards real-time networks-on-chip. SAC 2021: 145-154 - 2020
- [i1]Hui Chen, Peng Chen, Jun Zhou, Luan H. K. Duong, Weichen Liu:
ArSMART: An Improved SMART NoC Design Supporting Arbitrary-Turn Transmission. CoRR abs/2011.09261 (2020)
Coauthor Index
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