[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ skip to main content
10.1145/3566097.3568345acmconferencesArticle/Chapter ViewAbstractPublication PagesaspdacConference Proceedingsconference-collections
invited-talk

Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs

Published: 31 January 2023 Publication History

Abstract

Graph neural networks (GNNs) have pushed the state-of-the-art (SOTA) for performance in learning and predicting on large-scale data present in social networks, biology, etc. Since integrated circuits (ICs) can naturally be represented as graphs, there has been a tremendous surge in employing GNNs for machine learning (ML)-based methods for various aspects of IC design. Given this trajectory, there is a timely need to review and discuss some powerful and versatile GNN approaches for advancing IC design.
In this paper, we propose a generic pipeline for tailoring GNN models toward solving challenging problems for IC design. We outline promising options for each pipeline element, and we discuss selected and promising works, like leveraging GNNs to break SOTA logic obfuscation. Our comprehensive overview of GNNs frameworks covers (i) electronic design automation (EDA) and IC design in general, (ii) design of reliable ICs, and (iii) design as well as analysis of secure ICs. We provide our overview and related resources also in the GNN4IC hub at https://github.com/DfX-NYUAD/GNN4IC. Finally, we discuss interesting open problems for future research.

References

[1]
Anthony Agnesina et al. 2020. A General Framework For VLSI Tool Parameter Optimization with Deep Reinforcement Learning. In NeurIPS.
[2]
Anthony Agnesina, Kyungwook Chang, and Sung Kyu Lim. 2020. VLSI Placement Parameter Optimization using Deep Reinforcement Learning. In ICCAD.
[3]
Abdulrahman Alaql, Md Moshiur Rahman, and Swarup Bhunia. 2021. SCOPE: Synthesis-Based Constant Propagation Attack on Logic Locking. TVLSI (2021).
[4]
Yousra Alkabani et al. 2007. Remote activation of ICs for piracy prevention and digital right management. In ICCAD. 674--677.
[5]
Lilas Alrahis et al. 2019. Functional Reverse Engineering on SAT-Attack Resilient Logic Locking. In ISCAS. 1--5.
[6]
Lilas Alrahis et al. 2021. GNNUnlock+: A Systematic Methodology for Designing Graph Neural Networks-based Oracle-less Unlocking Schemes for Provably Secure Logic Locking. TETC (2021).
[7]
Lilas Alrahis et al. 2021. GNNUnlock: Graph Neural Networks-based Oracle-less Unlocking Scheme for Provably Secure Logic Locking. In DATE. 780--785.
[8]
Lilas Alrahis et al. 2022. GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists. TCAD 41, 8 (2022), 2435--2448.
[9]
Lilas Alrahis et al. 2022. OMLA: An Oracle-Less Machine Learning-Based Attack on Logic Locking. TCAS-II 69, 3 (2022), 1602--1606.
[10]
Lilas Alrahis, Johann Knechtel, Florian Klemme, Hussam Amrouch, and Ozgur Sinanoglu. 2022. GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation. TCAD 41, 11 (2022), 3826--3837.
[11]
Lilas Alrahis, Satwik Patnaik, Muhammad Abdullah Hanif, Muhammad Shafique, and Ozgur Sinanoglu. 2021. UNTANGLE: Unlocking Routing and Logic Obfuscation Using Graph Neural Networks-based Link Prediction. In ICCAD. 1--9.
[12]
Lilas Alrahis, Satwik Patnaik, Johann Knechtel, Hani Saleh, Baker Mohammad, Mahmoud Al-Qutayri, and Ozgur Sinanoglu. 2021. UNSAIL: Thwarting Oracle-Less Machine Learning Attacks on Logic Locking. TIFS 16 (2021), 2508--2523.
[13]
Lilas Alrahis, Satwik Patnaik, Muhammad Shafique, and Ozgur Sinanoglu. 2022. Embracing Graph Neural Networks for Hardware Security. In ICCAD.
[14]
Lilas Alrahis, Satwik Patnaik, Muhammad Shafique, and Ozgur Sinanoglu. 2022. MuxLink: Circumventing Learning-Resilient MUX-Locking Using Graph Neural Network-based Link Prediction. In DATE. 694--699.
[15]
Lilas Alrahis, Muhammad Yasin, Nimisha Limaye, Hani Saleh, Baker Mohammad, Mahmoud Alqutayri, and Ozgur Sinanoglu. 2019. ScanSAT: Unlocking Static and Dynamic Scan Obfuscation. TETC (2019), 1--1.
[16]
Lilas Alrahis, Muhammad Yasin, Hani Saleh, Baker Mohammad, Mahmoud Al-Qutayri, and Ozgur Sinanoglu. 2019. ScanSAT: Unlocking Obfuscated Scan Chains. In ASP-DAC. 352--357.
[17]
Hussam Amrouch, Behnam Khaleghi, Andreas Gerstlauer, and Jorg Henkel. 2016. Reliability-aware design to suppress aging. In DAC. 1--6.
[18]
Kyeonghyeon Baek, Hyunbum Park, Suwan Kim, Kyumyung Choi, and Taewhan Kim. 2022. Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction using Graph Neural Network and U-Net. In ICCAD.
[19]
Tim Bucher, Lilas Alrahis, Guilherme Paim, Sergio Bampi, Ozgur Sinanoglu, and Hussam Amrouch. 2022. AppGNN: Approximation-Aware Functional Reverse Engineering using Graph Neural Networks. ICCAD (2022), 1--6.
[20]
Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, and David Z. Pan. 2021. Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks. In DAC. 1243--1248.
[21]
Tinghuan Chen et al. 2021. Analog IC Aging-Induced Degradation Estimation via Heterogeneous Graph Convolutional Networks. In ACP-DAC. 898--903.
[22]
Tinghuan Chen et al. 2022. Deep H-GCN: Fast Analog IC Aging-Induced Degradation Estimation. TCAD 41, 7 (2022), 1990--2003.
[23]
Zhiqian Chen, Gaurav Kolhe, Setareh Rafatirad, Chang-Tien Lu, Sai Manoj PD, Houman Homayoun, and Liang Zhao. 2020. Estimating the circuit de-obfuscation runtime based on graph deep learning. In DATE. IEEE, 358--363.
[24]
Ruoyu Cheng and Junchi Yan. 2021. On Joint Learning for Solving Placement and Routing in Chip Design. NeurIPS 34 (2021), 16508--16519.
[25]
Subhajit Dutta Chowdhury et al. 2021. ReIGNN: State Register Identification Using Graph Neural Networks for Circuit Reverse Engineering. In ICCAD. 1--9.
[26]
Gabriele Corso et al. 2020. Principal neighbourhood aggregation for graph nets. NeurIPS 33 (2020), 13260--13271.
[27]
Aijiao Cui, Gang Qu, and Yan Zhang. 2015. Ultra-low overhead dynamic water-marking on scan design for hard IP protection. TIFS 10, 11 (2015), 2298--2313.
[28]
Amur Ghose et al. 2021. Generalizable Cross-Graph Embedding for GNN-Based Congestion Prediction. In ICCAD.
[29]
Justin Gilmer, Samuel S. Schoenholz, Patrick F. Riley, Oriol Vinyals, and George E. Dahl. 2017. Neural Message Passing for Quantum Chemistry. In ICML. 1263--1272.
[30]
Zizheng Guo et al. 2022. A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction. In DAC. 1207--1212.
[31]
Will Hamilton, Zhitao Ying, and Jure Leskovec. 2017. Inductive Representation Learning on Large Graphs. In NIPS. 1025--1035.
[32]
Zhuolun He, Ziyi Wang, Chen Bail, Haoyu Yang, and Bei Yu. 2021. Graph Learning-Based Arithmetic Block Identification. In ICCAD. IEEE, 1--8.
[33]
Guyue Huang et al. 2021. Machine Learning for Electronic Design Automation: A Survey. TODAES 26, 5, Article 40 (2021).
[34]
Ahmed Hussein, Mohamed Medhat Gaber, Eyad Elyan, and Chrisina Jayne. 2017. Imitation Learning: A Survey of Learning Methods. 50, 2, Article 21 (2017).
[35]
H. M. Kamali, K. Z. Azar, H. Homayoun, and A. Sasan. 2020. InterLock: An Intercorrelated Logic and Routing Locking. In ICCAD. 1--9.
[36]
Brucek Khailany et al. 2020. Accelerating Chip Design With Machine Learning. Micro 40, 6 (2020), 23--32.
[37]
Thomas N. Kipf and Max Welling. 2017. Semi-Supervised Classification with Graph Convolutional Networks. In ICLR.
[38]
Robert Kirby et al. 2019. CongestionNet: Routing congestion prediction using deep graph neural networks. In VLSI-SoC. 217--222.
[39]
Johann Knechtel. 2020. Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges. In ISPD. 75--86.
[40]
Johann Knechtel et al. 2020. Towards secure composition of integrated circuits and electronic systems: On the role of EDA. In DATE. 508--513.
[41]
Johann Knechtel, Satwik Patnaik, and Ozgur Sinanoglu. 2019. Protect your chip design intellectual property: An overview. In IOLTS. 211--216.
[42]
Kishor Kunal et al. 2020. GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. In DATE. 55--60.
[43]
Leon Li and Alex Orailoglu. 2019. Piercing Logic Locking Keys through Redundancy Identification. In DATE. 540--545.
[44]
Nimisha Limaye, Satwik Patnaik, and Ozgur Sinanoglu. 2022. Valkyrie: Vulnerability Assessment Tool and Attack for Provably-Secure Logic Locking Techniques. TIFS 17 (2022), 744--759.
[45]
Mingjie Liu, Walker J. Turner, George F. Kokai, Brucek Khailany, David Z. Pan, and Haoxing Ren. 2021. Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization. In DATE. 1372--1377.
[46]
Wenye Liu, Chip-Hong Chang, Xueyang Wang, Chen Liu, Jason M. Fung, Mohammad Ebrahimabadi, Naghmeh Karimi, Xingyu Meng, and Kanad Basu. 2021. Two Sides of the Same Coin: Boons and Banes of Machine Learning in Hardware Security. JETCAS 11, 2 (2021), 228--251.
[47]
Daniela Sánchez Lopera et al. 2022. A Comprehensive Survey on Electronic Design Automation and Graph Neural Networks: Theory and Applications. TODAES (2022).
[48]
Daniela Sánchez Lopera and Wolfgang Ecker. 2022. Applying GNNs to Timing Estimation at RTL (Invited Paper). In ICCAD.
[49]
Daniela Sánchez Lopera, Lorenzo Servadei, Gamze Naz Kiprit, Souvik Hazra, Robert Wille, and Wolfgang Ecker. 2021. A Survey of Graph Neural Networks for Electronic Design Automation. In MLCAD. 1--6.
[50]
Yi-Chen Lu, Sai Surya Kiran Pentapati, Lingjun Zhu, Kambiz Samadi, and Sung Kyu Lim. 2020. TP-GNN: A Graph Neural Network Framework for Tier Partitioning in Monolithic 3D ICs. In DAC. 1--6.
[51]
Yi-Chen Lu and Sung Kyu Lim.2022. On Advancing Physical Design using Graph Neural Networks (Invited Paper). In ICCAD.
[52]
Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, and Sung Kyu Lim. 2021. Doomed Run Prediction in Physical Design by Exploiting Sequential Flow and Graph Learning. In ICCAD. 1--9.
[53]
Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, and Sung Kyu Lim. 2021. RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning. In DAC. 733--738.
[54]
Yi-Chen Lu, Sai Pentapati, and Sung Kyu Lim. 2020. VLSI placement optimization using graph neural networks. In NeurIPS.
[55]
Yi-Chen Lu, Sai Pentapati, and Sung Kyu Lim. 2021. The Law of Attraction: Affinity-Aware Placement Optimization Using Graph Neural Networks. In ISPD.
[56]
Yuzhe Ma, Zhuolun He, Wei Li, Lu Zhang, and Bei Yu. 2020. Understanding graphs in EDA: From shallow to deep learning. In ISPD. 119--126.
[57]
Yuzhe Ma, Haoxing Ren, Brucek Khailany, Harbinder Sikka, Lijuan Luo, Karthikeyan Natarajan, and Bei Yu. 2019. High Performance Graph Convolutional Networks with Applications in Testability Analysis. In DAC. 1--6.
[58]
Likhitha Mankali, Lilas Alrahis, Satwik Patnaik, Johann Knechtel, and Ozgur Sinanoglu. 2022. Titan: Security Analysis of Large-Scale Hardware Obfuscation Using Graph Neural Networks. TIFS (2022).
[59]
Ian McLoughlin. 2011. Reverse engineering of embedded consumer electronic systems. In ISCE. 352--356.
[60]
Azalia Mirhoseini et al. 2021. A graph placement methodology for fast chip design. Nature 594, 7862 (2021), 207--212.
[61]
Nikhil Muralidhar, Abdullah Zubair, Nathanael Weidler, Ryan Gerdes, and Naren Ramakrishnan. 2021. Contrastive Graph Convolutional Networks for Hardware Trojan Detection in Third Party IP Cores. In HOST.
[62]
Satwik Patnaik, Mohammed Ashraf, Ozgur Sinanoglu, and Johann Knechtel. 2020. Obfuscating the interconnects: Low-cost and resilient full-chip layout camouflaging. TCAD 39, 12 (2020), 4466--4481.
[63]
Satwik Patnaik, Nikhil Rangarajan, Johann Knechtel, Ozgur Sinanoglu, and Shaloo Rakheja. 2018. Advancing hardware security using polymorphic and stochastic spin-hall effect devices. In DATE. 97--102.
[64]
Jeyavijayan Rajendran, Michael Sam, Ozgur Sinanoglu, and Ramesh Karri. 2013. Security analysis of integrated circuit camouflaging. In CCS. 709--720.
[65]
Jeyavijayan Rajendran, Ozgur Sinanoglu, and Ramesh Karri. 2014. Regaining Trust in VLSI Design: Design-for-Trust Techniques. Proc. IEEE 102, 8 (2014).
[66]
Martin Rapp et al. 2022. MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper. TCAD 41, 10 (2022), 3162--3181.
[67]
Haoxing Ren et al. 2020. ParaGraph: Layout parasitics and device parameter prediction using graph neural networks. In DAC.
[68]
Haoxing Ren et al. 2022. Why are Graph Neural Networks Effective for EDA Problems? (Invited Paper). In ICCAD.
[69]
Masoud Rostami, Farinaz Koushanfar, and Ramesh Karri. 2014. A Primer on Hardware Security: Models, Methods, and Metrics. Proc. IEEE 102, 8 (2014).
[70]
Debasri Saha and Susmita Sur-Kolay. 2011. SoC: a real platform for IP reuse, IP infringement, and IP protection. VLSI Design (2011).
[71]
Dominik Sisejkovic, Farhad Merchant, Lennart M Reimann, and Rainer Leupers. 2021. Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks. TCAD (2021).
[72]
Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Harshit Srivastava, Ahmed Hallawa, and Rainer Leupers. 2021. Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach. JETC 17, 3, Article 30 (2021).
[73]
Dominik Sisejkovic, Lennart M. Reimann, Elmira Moussavi, Farhad Merchant, and Rainer Leupers. 2021. Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities. In VLSI-SoC. 1--6.
[74]
P. Subramanyan, S. Ray, and S. Malik. 2015. Evaluating the Security of Logic Encryption Algorithms. In HOST. 137--143.
[75]
Ecenur Ustun et al. 2020. Accurate operation delay prediction for FPGA HLS using graph neural networks. In ICCAD. 1--9.
[76]
Petar Veličković, Guillem Cucurull, Arantxa Casanova, Adriana Romero, Pietro Lio, and Yoshua Bengio. 2018. Graph attention networks. In ICLR.
[77]
Hanrui Wang, Kuan Wang, Jiacheng Yang, Linxiao Shen, Nan Sun, Hae-Seung Lee, and Song Han. 2020. GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning. In DAC.
[78]
Ziyi Wang, Chen Bai, Zhuolun He, Guangliang Zhang, Qiang Xu, Tsung-Yi Ho, Bei Yu, and Yu Huang. 2022. Functionality Matters in Netlist Representation Learning. In DAC. 1--6.
[79]
Nan Wu, Jiwon Lee, Yuan Xie, and Cong Hao. 2022. LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models. In ASAP. 11--18.
[80]
Nan Wu, Yuan Xie, and Cong Hao. 2021. Ironman: Gnn-assisted design space exploration in high-level synthesis via reinforcement learning. In GLVLSI. 39--44.
[81]
Nan Wu, Yuan Xie, and Cong Hao. 2022. IronMan-Pro: Multi-objective Design Space Exploration in HLS via Reinforcement Learning and Graph Neural Network based Modeling. TCAD (2022), 1--1.
[82]
Nan Wu, Hang Yang, Yuan Xie, Pan Li, and Cong Hao. 2022. High-Level Synthesis Performance Prediction Using GNNs: Benchmarking, Modeling, and Advancing. In DAC. 49--54.
[83]
Zhiyao Xie, Rongjian Liang, Xiaoqing Xu, Jiang Hu, Yixiao Duan, and Yiran Chen. 2021. Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation. In ASP-DAC. 671--677.
[84]
Keyulu Xu, Weihua Hu, Jure Leskovec, and Stefanie Jegelka. 2019. How powerful are graph neural networks?. In ICLR.
[85]
Rozhin Yasaei, Luke Chen, Shih-Yuan Yu, and Mohammad Abdullah Al Faruque. 2022. Hardware Trojan Detection using Graph Neural Networks. TCAD (2022).
[86]
Rozhin Yasaei, Sina Faezi, and Mohammad Abdullah Al Faruque. 2022. Golden Reference-Free Hardware Trojan Localization Using Graph Convolutional Network. TVLSI 30, 10 (2022), 1401--1411.
[87]
Rozhin Yasaei, Shih-Yuan Yu, and Mohammad Abdullah Al Faruque. 2021. GNN4TJ: Graph Neural Networks for Hardware Trojan Detection at Register Transfer Level. In DATE. 1504--1509.
[88]
Rozhin Yasaei, Shih-Yuan Yu, Emad Kasaeyan Naeini, and Mohammad Abdullah Al Faruque. 2021. GNN4IP: Graph Neural Network for Hardware Intellectual Property Piracy Detection. In DAC. 217--222.
[89]
Muhammad Yasin, Bodhisatwa Mazumdar, Ozgur Sinanoglu, and Jeyavijayan Rajendran. 2020. Removal Attacks on Logic Locking and Camouflaging Techniques. IEEE TETC 8, 2 (2020), 517--532.
[90]
Shih-Yuan Yu, Rozhin Yasaei, Qingrong Zhou, Tommy Nguyen, and Mohammad Abdullah Al Faruque. 2021. HW2VEC: A Graph Learning Tool for Automating Hardware Security. In HOST. 13--23.
[91]
Hanqing Zeng et al. 2019. GraphSAINT: Graph Sampling Based Inductive Learning Method. In ICLR.
[92]
Guo Zhang, Hao He, and Dina Katabi. 2019. Circuit-GNN: Graph neural networks for distributed circuit design. In ICML. 7364--7373.
[93]
Muhan Zhang and Yixin Chen. 2018. Link Prediction Based on Graph Neural Networks. In NIPS. 5171--5181.
[94]
Muhan Zhang, Zhicheng Cui, Marion Neumann, and Yixin Chen. 2018. An end-to-end deep learning architecture for graph classification. In AAAI.
[95]
Yanqing Zhang, Haoxing Ren, and Brucek Khailany. 2020. GRANNITE: Graph Neural Network Inference for Transferable Power Estimation. In DAC. 1--6.
[96]
Zhe Zhang et al. 2018. Extraction of process variation parameters in FinFET technology based on compact modeling and characterization. TED 65, 3 (2018).
[97]
Guangwei Zhao and Kaveh Shamsi. 2022. Graph Neural Network based Netlist Operator Detection under Circuit Rewriting. In GLSVLSI. 53--58.
[98]
Xinyi Zhou et al. 2022. Heterogeneous Graph Neural Network-based Imitation Learning for Gate Sizing Acceleration. In ICCAD.

Cited By

View all
  • (2024)HDCircuit: Brain-Inspired HyperDimensional Computing for Circuit Recognition2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546587(1-2)Online publication date: 25-Mar-2024
  • (2024)Automated Physical Design Watermarking Leveraging Graph Neural NetworksProceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD10.1145/3670474.3685951(1-10)Online publication date: 9-Sep-2024
  • (2024)Automated Physical Design Watermarking Leveraging Graph Neural Networks2024 ACM/IEEE 6th Symposium on Machine Learning for CAD (MLCAD)10.1109/MLCAD62225.2024.10740234(1-10)Online publication date: 9-Sep-2024
  • Show More Cited By

Index Terms

  1. Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs
        Index terms have been assigned to the content through auto-classification.

        Recommendations

        Comments

        Please enable JavaScript to view thecomments powered by Disqus.

        Information & Contributors

        Information

        Published In

        cover image ACM Conferences
        ASPDAC '23: Proceedings of the 28th Asia and South Pacific Design Automation Conference
        January 2023
        807 pages
        ISBN:9781450397834
        DOI:10.1145/3566097
        Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

        Sponsors

        In-Cooperation

        • IPSJ
        • IEEE CAS
        • IEEE CEDA
        • IEICE

        Publisher

        Association for Computing Machinery

        New York, NY, United States

        Publication History

        Published: 31 January 2023

        Check for updates

        Qualifiers

        • Invited-talk

        Conference

        ASPDAC '23
        Sponsor:

        Acceptance Rates

        ASPDAC '23 Paper Acceptance Rate 102 of 328 submissions, 31%;
        Overall Acceptance Rate 466 of 1,454 submissions, 32%

        Upcoming Conference

        ASPDAC '25

        Contributors

        Other Metrics

        Bibliometrics & Citations

        Bibliometrics

        Article Metrics

        • Downloads (Last 12 months)262
        • Downloads (Last 6 weeks)15
        Reflects downloads up to 13 Dec 2024

        Other Metrics

        Citations

        Cited By

        View all
        • (2024)HDCircuit: Brain-Inspired HyperDimensional Computing for Circuit Recognition2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546587(1-2)Online publication date: 25-Mar-2024
        • (2024)Automated Physical Design Watermarking Leveraging Graph Neural NetworksProceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD10.1145/3670474.3685951(1-10)Online publication date: 9-Sep-2024
        • (2024)Automated Physical Design Watermarking Leveraging Graph Neural Networks2024 ACM/IEEE 6th Symposium on Machine Learning for CAD (MLCAD)10.1109/MLCAD62225.2024.10740234(1-10)Online publication date: 9-Sep-2024
        • (2024)CeConP: Exploring Node Centrality for Early Routing Congestion Prediction2024 IEEE 15th Latin America Symposium on Circuits and Systems (LASCAS)10.1109/LASCAS60203.2024.10506148(1-5)Online publication date: 27-Feb-2024
        • (2024)GAN4IP: A unified GAN and logic locking-based pipeline for hardware IP securitySādhanā10.1007/s12046-024-02461-849:2Online publication date: 5-May-2024
        • (2023)Systematic Trojan Detection in Crypto-Systems Using the Model CheckerJournal of Circuits, Systems and Computers10.1142/S021812662450045233:03Online publication date: 5-Oct-2023
        • (2023)Graph Neural Networks for Hardware Vulnerability Analysis— Can you Trust your GNN?2023 IEEE 41st VLSI Test Symposium (VTS)10.1109/VTS56346.2023.10140095(1-4)Online publication date: 24-Apr-2023
        • (2023)On the Prediction of Hardware Security Properties of HLS Designs Using Graph Neural Networks2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)10.1109/DFT59622.2023.10313544(1-6)Online publication date: 3-Oct-2023
        • (2023)A Portable Hardware Trojan Detection Using Graph Attention Networks2023 IEEE 32nd Asian Test Symposium (ATS)10.1109/ATS59501.2023.10317998(1-6)Online publication date: 14-Oct-2023
        • (2023)From Graph Theory to Graph Neural Networks (GNNs): The Opportunities of GNNs in Power ElectronicsIEEE Access10.1109/ACCESS.2023.334579511(145067-145084)Online publication date: 2023

        View Options

        Login options

        View options

        PDF

        View or Download as a PDF file.

        PDF

        eReader

        View online with eReader.

        eReader

        Media

        Figures

        Other

        Tables

        Share

        Share

        Share this Publication link

        Share on social media