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BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU

Authors:

Mohammadhossein Askarihemmat,

Olexa Bilaniuk,

Yassine Hariri,

Jean-Pierre DavidAuthors Info & Claims

ASPDAC '23: Proceedings of the 28th Asia and South Pacific Design Automation Conference

Pages 483 - 489

https://doi.org/10.1145/3566097.3567872

Published: 31 January 2023 Publication History

Abstract

We present a DNN accelerator that allows inference at arbitrary precision with dedicated processing elements that are configurable at the bit level. Our DNN accelerator has 8 Processing Elements controlled by a RISC-V controller with a combined 8.2 TMACs of computational power when implemented with the recent Alveo U250 FPGA platform. We develop a code generator tool that ingests CNN models in ONNX format and generates an executable command stream for the RISC-V controller. We demonstrate the scalable throughput of our accelerator by running different DNN kernels and models when different quantization levels are selected. Compared to other low precision accelerators, our accelerator provides run time programmability without hardware reconfiguration and can accelerate DNNs with multiple quantization levels, regardless of the target FPGA size. BARVINN is an open source project and it is available at https://github.com/hossein1387/BARVINN.

References

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MohammadHossein AskariHemmat, Olexa Bilaniuk, Sean Wagner, Yvon Savaria, and Jean-Pierre David. 2021. RISC-V Barrel Processor for Deep Neural Network Acceleration. In 2021 IEEE International Symposium on Circuits and Systems (ISCAS). 1--5.

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Olexa Bilaniuk, Sean Wagner, Yvon Savaria, and Jean-Pierre David. 2019. Bit-Slicing FPGA Accelerator for Quantized Neural Networks. In 2019 IEEE International Symposium on Circuits and Systems (ISCAS). 1--5.

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Sungju Ryu, Hyungjun Kim, Wooseok Yi, and Jae-Joon Kim. 2019. Bitblade: Area and energy-efficient precision-scalable neural network accelerator with bitwise summation. In Proceedings of the 56th Annual Design Automation Conference 2019. 1--6.

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Cited By

AskariHemmat MDupuis TFournier YEl Zarif NCavalcante MPerotti MGürkaynak FBenini LLeduc-Primeau FSavaria YDavid J(2023)Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference2023 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS46773.2023.10181985(1-5)Online publication date: 21-May-2023
https://doi.org/10.1109/ISCAS46773.2023.10181985
Mariscal-Melgar JMoritz MRedlich TWulfsberg J(2023)Sustainable Computing Through Open Standard ISAs: Leveraging Tailor-Fit Hardware Designs for Circular EconomiesProduction at the Leading Edge of Technology10.1007/978-3-031-47394-4_46(469-480)Online publication date: 18-Nov-2023
https://doi.org/10.1007/978-3-031-47394-4_46

Index Terms

BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU
1. Hardware
  1. Integrated circuits
  2. Very large scale integration design

Index terms have been assigned to the content through auto-classification.

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Published In

cover image ACM Conferences

ASPDAC '23: Proceedings of the 28th Asia and South Pacific Design Automation Conference

January 2023

807 pages

ISBN:9781450397834

DOI:10.1145/3566097

General Chair:
Atsushi Takahashi
Tokyo Institute of Technology

Copyright © 2023 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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IPSJ
IEEE CAS
IEEE CEDA
IEICE

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 31 January 2023

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Research-article

Funding Sources

Fonds de recherche du Québec – Nature et technologies
NSERC COHESA
Mitacs

Conference

ASPDAC '23

Sponsor:

SIGDA

ASPDAC '23: 28th Asia and South Pacific Design Automation Conference

January 16 - 19, 2023

Tokyo, Japan

Acceptance Rates

ASPDAC '23 Paper Acceptance Rate 102 of 328 submissions, 31%;

Overall Acceptance Rate 466 of 1,454 submissions, 32%

Upcoming Conference

ASPDAC '25

Sponsor:
sigda

30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

Tokyo , Japan

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Cited By

AskariHemmat MDupuis TFournier YEl Zarif NCavalcante MPerotti MGürkaynak FBenini LLeduc-Primeau FSavaria YDavid J(2023)Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference2023 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS46773.2023.10181985(1-5)Online publication date: 21-May-2023
https://doi.org/10.1109/ISCAS46773.2023.10181985
Mariscal-Melgar JMoritz MRedlich TWulfsberg J(2023)Sustainable Computing Through Open Standard ISAs: Leveraging Tailor-Fit Hardware Designs for Circular EconomiesProduction at the Leading Edge of Technology10.1007/978-3-031-47394-4_46(469-480)Online publication date: 18-Nov-2023
https://doi.org/10.1007/978-3-031-47394-4_46

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