RU2109330C1 - Способ управления работой порта последовательного доступа к видеопамяти - Google Patents

Способ управления работой порта последовательного доступа к видеопамяти Download PDF

Info

Publication number: RU2109330C1
Authority: RU; Russia
Prior art keywords: port; access memory; data; mode; sam
Prior art date: 1990-05-04

Application number

SU4830360A

Other languages

English (en)

Russian (ru)

Inventor

Ли Янг-Кю

Original Assignee

Самсунг Электроникс Ко., Лтд.

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1990-05-04

Filing date

1990-06-22

Publication date

1998-04-20

1990-06-22 Application filed by Самсунг Электроникс Ко., Лтд. filed Critical Самсунг Электроникс Ко., Лтд.

1998-04-20 Application granted granted Critical

1998-04-20 Publication of RU2109330C1 publication Critical patent/RU2109330C1/ru

Images

Classifications

- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/30—Accessing single arrays
- G11C29/32—Serial access; Scan testing

Landscapes

Engineering & Computer Science (AREA)
Theoretical Computer Science (AREA)
Physics & Mathematics (AREA)
General Engineering & Computer Science (AREA)
General Physics & Mathematics (AREA)
Multimedia (AREA)
Dram (AREA)
For Increasing The Reliability Of Semiconductor Memories (AREA)
Transceivers (AREA)

SU4830360A 1990-05-04 1990-06-22 Способ управления работой порта последовательного доступа к видеопамяти RU2109330C1 (ru)

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
KR90-6350		1990-05-04
KR1019900006350A KR920003269B1 (ko)	1990-05-04	1990-05-04	듀얼 포트 메모리소자의 모우드 전환방법

Related Parent Applications (1)

Application Number	Title	Priority Date	Filing Date
SU906350 Division

Publications (1)

Publication Number	Publication Date
RU2109330C1 true RU2109330C1 (ru)	1998-04-20

Family

ID=19298718

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
SU4830360A RU2109330C1 (ru)	1990-05-04	1990-06-22	Способ управления работой порта последовательного доступа к видеопамяти

Country Status (10)

Country	Link
JP (1)	JPH073747B2 (zh)
KR (1)	KR920003269B1 (zh)
CN (1)	CN1019238B (zh)
DE (1)	DE4021600C2 (zh)
FR (1)	FR2661770B1 (zh)
GB (1)	GB2243700B (zh)
IT (1)	IT1248855B (zh)
NL (1)	NL194899C (zh)
RU (1)	RU2109330C1 (zh)
SE (1)	SE512454C2 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
CN1067477C (zh) *	1996-04-16	2001-06-20	联华电子股份有限公司	以串行编码方式进行芯片组间信号传输的装置
KR100773065B1 (ko) *	2006-09-12	2007-11-19	엠텍비젼 주식회사	듀얼 포트 메모리 장치, 메모리 장치 및 듀얼 포트 메모리장치 동작 방법
KR100773063B1 (ko) *	2006-09-12	2007-11-19	엠텍비젼 주식회사	듀얼 포트 메모리 장치, 메모리 장치 및 듀얼 포트 메모리장치 동작 방법

Citations (3)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
SU1298754A1 (ru) *	1985-03-12	1987-03-23	Войсковая часть 03080	Устройство управлени распределением оперативной пам ти
US4703449A (en) *	1983-02-28	1987-10-27	Data Translation Inc.	Interrupt driven multi-buffer DMA circuit for enabling continuous sequential data transfers
SU1348860A1 (ru) *	1986-06-25	1987-10-30	Харьковский Институт Радиоэлектроники Им.Акад.М.К.Янгеля	Устройство дл управлени пам тью видеоинформации

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPS5589980A (en) *	1978-11-27	1980-07-08	Nec Corp	Semiconductor memory unit
JPH073757B2 (ja) *	1987-02-25	1995-01-18	三菱電機株式会社	半導体記憶装置
US4817058A (en) *	1987-05-21	1989-03-28	Texas Instruments Incorporated	Multiple input/output read/write memory having a multiple-cycle write mask
JPH0760594B2 (ja) *	1987-06-25	1995-06-28	富士通株式会社	半導体記憶装置
JP2793184B2 (ja) *	1987-07-27	1998-09-03	日本電気アイシーマイコンシステム株式会社	半導体記憶装置

1990
- 1990-05-04 KR KR1019900006350A patent/KR920003269B1/ko not_active IP Right Cessation
- 1990-06-15 IT IT02065090A patent/IT1248855B/it active IP Right Grant
- 1990-06-15 SE SE9002149A patent/SE512454C2/sv unknown
- 1990-06-22 RU SU4830360A patent/RU2109330C1/ru not_active IP Right Cessation
- 1990-06-25 CN CN90104906A patent/CN1019238B/zh not_active Expired
- 1990-06-25 GB GB9014079A patent/GB2243700B/en not_active Expired - Fee Related
- 1990-07-06 DE DE4021600A patent/DE4021600C2/de not_active Expired - Fee Related
- 1990-07-16 NL NL9001613A patent/NL194899C/nl not_active IP Right Cessation
- 1990-07-20 FR FR9009334A patent/FR2661770B1/fr not_active Expired - Fee Related
- 1990-07-23 JP JP2194692A patent/JPH073747B2/ja not_active Expired - Lifetime

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4703449A (en) *	1983-02-28	1987-10-27	Data Translation Inc.	Interrupt driven multi-buffer DMA circuit for enabling continuous sequential data transfers
SU1298754A1 (ru) *	1985-03-12	1987-03-23	Войсковая часть 03080	Устройство управлени распределением оперативной пам ти
SU1348860A1 (ru) *	1986-06-25	1987-10-30	Харьковский Институт Радиоэлектроники Им.Акад.М.К.Янгеля	Устройство дл управлени пам тью видеоинформации

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
WO, заявка РСТ/US 88/00613, кл. G 06 F 12/00, 1988. *

Also Published As

Publication number	Publication date
SE512454C2 (sv)	2000-03-20
FR2661770B1 (fr)	1994-01-28
KR920003269B1 (ko)	1992-04-27
IT9020650A0 (it)	1990-06-15
CN1056361A (zh)	1991-11-20
GB9014079D0 (en)	1990-08-15
SE9002149D0 (sv)	1990-06-15
NL194899C (nl)	2003-06-04
JPH0414695A (ja)	1992-01-20
IT9020650A1 (it)	1991-12-15
GB2243700B (en)	1994-02-02
NL194899B (nl)	2003-02-03
KR910020557A (ko)	1991-12-20
IT1248855B (it)	1995-01-30
DE4021600C2 (de)	1994-04-07
CN1019238B (zh)	1992-11-25
FR2661770A1 (fr)	1991-11-08
DE4021600A1 (de)	1991-11-07
JPH073747B2 (ja)	1995-01-18
SE9002149L (sv)	1991-11-05
NL9001613A (nl)	1991-12-02
GB2243700A (en)	1991-11-06

Publication	Publication Date	Title
KR100393860B1 (ko)	2003-10-17	랜덤액세스메모리
US4958346A (en)	1990-09-18	Memory testing device
KR20070108331A (ko)	2007-11-09	반도체기억장치
RU2109330C1 (ru)	1998-04-20	Способ управления работой порта последовательного доступа к видеопамяти
JPH0146946B2 (zh)	1989-10-11
JPH033200A (ja)	1991-01-09	半導体記憶装置
US6804166B2 (en)	2004-10-12	Method and apparatus for operating a semiconductor memory at double data transfer rate
JPH0289300A (ja)	1990-03-29	半導体メモリ素子
JP3516834B2 (ja)	2004-04-05	半導体集積回路
JPS6132758B2 (zh)	1986-07-29
JPH07182849A (ja)	1995-07-21	Ｆｉｆｏメモリ
JP2545719Y2 (ja)	1997-08-27	メモリ試験データ選択回路
JPS6031040B2 (ja)	1985-07-19	メモリ用集積回路装置
JPS63142589A (ja)	1988-06-14	半導体メモリ
KR0135671B1 (ko)	1998-04-24	리드 모디파이 라이트 동작 회로
KR19980028922A (ko)	1998-07-15	반도체 메모리 장치
KR920009435B1 (ko)	1992-10-16	듀얼 포트 메모리 소자의 데이타 전송방법
JPH01140489A (ja)	1989-06-01	半導体記憶装置
JP2004079105A (ja)	2004-03-11	デュアルポートメモリ試験装置
JPH0283900A (ja)	1990-03-23	半導体記憶装置
JPS58182189A (ja)	1983-10-25	ダイナミツク型ｍｏｓｒａｍ
JPH02310889A (ja)	1990-12-26	スタティックランダムアクセスメモリ
JPH02276090A (ja)	1990-11-09	半導体メモリ集積回路
JPS6112294B2 (zh)	1986-04-07
JPH0614436B2 (ja)	1994-02-23	半導体メモリ

Legal Events

Date	Code	Title	Description
2010-07-20	MM4A	The patent is invalid due to non-payment of fees	Effective date: 20090623
2010-07-20	REG	Reference to a code of a succession state	Ref country code: RU Ref legal event code: MM4A Effective date: 20090623

Date

Code

Title

Description

2010-07-20

MM4A

The patent is invalid due to non-payment of fees

Effective date: 20090623