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Article

Detection of CMOS address decoder open faults with March and pseudo random memory tests

Authors:

Jan Otterstedt,

Dirk Niggemeyer,

T. W. WilliamsAuthors Info & Claims

ITC '98: Proceedings of the 1998 IEEE International Test Conference

Pages 53 - 62

Published: 18 October 1998 Publication History

Abstract

A new method to integrate a test for CMOS address decoder open faults into March and pseudo random tests employed for testing semiconductor memories is presented. For commonly used memory organizations, March tests are implemented that, in addition to their original target faults, detect all CMOS address decoder open faults. The detection of these faults has been believed to require separate deterministic test patterns or tests of higher order. Address sequences generated by special Complete LFSRs and address dependent data are utilized to alter March tests to detect all address decoder open faults and retain the detection properties of the original tests. The additional overhead in terms of silicon area for an on-chip realization of a built-in March test with the added fault detection features is negligible, and the test application time remains of 0(N).

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Cited By

John PAntony P R(2017)BIST Architecture for Multiple RAMs in SoCProcedia Computer Science10.1016/j.procs.2017.09.121115:C(159-165)Online publication date: 1-Nov-2017
https://dl.acm.org/doi/10.1016/j.procs.2017.09.121
Dilillo LGirard PPravossoudovitch SVirazel ABorri SHage-Hassan M(2006)ADOFs and Resistive-ADOFs in SRAM Address DecodersJournal of Electronic Testing: Theory and Applications10.1007/s10836-006-7761-122:3(287-296)Online publication date: 1-Jun-2006
https://dl.acm.org/doi/10.1007/s10836-006-7761-1
Azimane MMajhi A(2004)New Test Methodology for Resistive Open Defect Detection in Memory Address DecodersProceedings of the 22nd IEEE VLSI Test Symposium10.5555/987684.987950Online publication date: 25-Apr-2004
https://dl.acm.org/doi/10.5555/987684.987950
Show More Cited By

Detection of CMOS address decoder open faults with March and pseudo random memory tests
1. Hardware
  1. Integrated circuits

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cover image Guide Proceedings

ITC '98: Proceedings of the 1998 IEEE International Test Conference

October 1998

753 pages

ISBN:0780350936

Publisher

IEEE Computer Society

United States

Publication History

Published: 18 October 1998

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Cited By

John PAntony P R(2017)BIST Architecture for Multiple RAMs in SoCProcedia Computer Science10.1016/j.procs.2017.09.121115:C(159-165)Online publication date: 1-Nov-2017
https://dl.acm.org/doi/10.1016/j.procs.2017.09.121
Dilillo LGirard PPravossoudovitch SVirazel ABorri SHage-Hassan M(2006)ADOFs and Resistive-ADOFs in SRAM Address DecodersJournal of Electronic Testing: Theory and Applications10.1007/s10836-006-7761-122:3(287-296)Online publication date: 1-Jun-2006
https://dl.acm.org/doi/10.1007/s10836-006-7761-1
Azimane MMajhi A(2004)New Test Methodology for Resistive Open Defect Detection in Memory Address DecodersProceedings of the 22nd IEEE VLSI Test Symposium10.5555/987684.987950Online publication date: 25-Apr-2004
https://dl.acm.org/doi/10.5555/987684.987950
Dilillo LGirard PPravossoudovitch SVirazel ABorri S(2004)March iC-Proceedings of the 22nd IEEE VLSI Test Symposium10.5555/987684.987948Online publication date: 25-Apr-2004
https://dl.acm.org/doi/10.5555/987684.987948
Lee KLee BKim S(2003)A simple diagnostic method for memory testingProceedings of the 2nd WSEAS International Conference on Electronics, Control and Signal Processing10.5555/1376214.1376230(1-6)Online publication date: 7-Dec-2003
https://dl.acm.org/doi/10.5555/1376214.1376230
Bergfeld TNiggemeyer DRudnick EBolsens I(2000)Diagnostic testing of embedded memories using BISTProceedings of the conference on Design, automation and test in Europe10.1145/343647.343786(305-311)Online publication date: 1-Jan-2000
https://dl.acm.org/doi/10.1145/343647.343786
Gizdarski E(2000)Detection of Delay Faults in Memory Address DecodersJournal of Electronic Testing: Theory and Applications10.1023/A:100832210375516:4(381-387)Online publication date: 1-Aug-2000
https://dl.acm.org/doi/10.1023/A%3A1008322103755
Niggemeyer DRedeker MOtterstedt J(1998)Integration of Non-Classical Faults in Standard March TestsProceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing10.5555/580898.825055Online publication date: 24-Aug-1998
https://dl.acm.org/doi/10.5555/580898.825055

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