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This paper explores defects found in a high volumemicroprocessor when shipping at a low defect level. Abrief description of the manufacturing flow along withdefinition of DPM is covered. Three defective devices arethen root cause analyzed for defect ...

The purpose of this paper is to present a novelmethodology for the estimation of VLSI products DefectLevel, or reject rates, in the IC design environment. A newDefect-Oriented (DO) fault extraction and stratifiedsampling technique, implemented in an ...

SEMATECH has sponsored a "Test Method Evaluation"study to understand the trade-offs among the most commontest methodologies used in the industry[1,2]. This paper presentsthe results of the failure analysis portion of thatproject. The testing, ...

A new method to integrate a test for CMOS address decoder open faults into March and pseudo random tests employed for testing semiconductor memories is presented. For commonly used memory organizations, March tests are implemented that, in addition to ...

Testing two-port memories requires the useof single-port tests as well as special two-port tests; thetest strategy determines which tests to be used. Manytwo-port memories have ports which are read-only orwrite-only; this impacts the possible fault ...

Given a set of memory array faults the problem ofcomputing an optimal march test that detects all specified memory array faults is addressed. In this paper, wepropose a novel approach in which every memory arrayfault is modeled by a set of primitive ...

This paper describes a novel design-for-test (DFT) conceptfor I/O delay testing while contacting very few pads,using boundary scan and new test-generation software. Inproduction testing of the IBM System/390 Generation 3 and several ASIC chips, these ...

Testing delay faults is becoming critical in new deepsubmicron digital circuits. This paper introduces a newtechnique for delay and stuck-at fault testing in digitalintegrated circuits. The proposed technique consists ofsensitizing a path in the digital ...

The addressing and clocking schemes in PowerPC microprocessor embedded memories present modelingchallenges. The ability of most scan based test tools toaccurately generate test patterns for these embedded memoriesis limited. What is needed is aggressive ...

A new design feature of an integrated circuit (IC) testhandler tray is described that significantly improves theconvective heat transfer to the tray and the IC devices inthe tray. The improved tray incorporates verticallyprotruding ribs which breakup ...

A very compact electrical test contactor assemblydesign for a handler is described that gives a means tobetter match the temperature of the contactors (-60 degCto 160 degC) and the devices under test (DUTs). Theresulting design aims for tight ...

As microprocessor speeds and power increase, so toodoes the need for better thermal control. Today'shigh performance processors generate enormousamounts of heat at the transistor level due to selfheating effects within the die. Higher dietemperatures ...

Advances in semiconductor process and design technology enable the design of complex system chips. Traditional IC design,in which every circuit is designed from scratch and reuse is limited to standard-cell libraries, is more and more replaced bya ...

This paper presents a logic synthesis tool calledBETSY (BIST Environment Testable SYnthesis) forsynthesizing circuits that achieve complete (100%) faultcoverage in a user specified BIST environment. Insteadof optimizing the circuit for a generic pseudo-...

Existing high-level BIST synthesis methods focuson one objective, minimizing either area overhead or testtime. Hence, those methods do not render exploration oflarge design space, which may result in a local optimum.In this paper, we present a method ...

Most approaches to the synthesis of built-in self test (BIST)circuitry use a manual choose-and-evaluate approach, where aparticular BISTgenerator is chosenandthen evaluatedby fault-simulatingthe design with the vectors that the chosen ...

This paper investigates the important question of whetheror not Iddq-only fails are "bad" and should be rejectedduring testing. The analysis is based on the Sematechexperiment results and employs current signature-basedtesting.

This paper presents the results for very detailed studies ofpattern and timing-dependent failures from the 309 dies inthe retest of an experimental test chip. 22 out of the 50CUTs with pattern-dependent failures had test escapes ifthe test sets were ...