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Di Carlo SPolitano GPrinetto PSavino AScionti A(2011)Genetic defect based march test generation for SRAMProceedings of the 2011 international conference on Applications of evolutionary computation - Volume Part II10.5555/2008445.2008463(141-150)Online publication date: 27-Apr-2011
https://dl.acm.org/doi/10.5555/2008445.2008463
Ney AGirard PLandrault CPravossoudovitch SVirazel ABastian MLauwereins RMadsen J(2007)Slow write driver faults in 65nm SRAM technologyProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266479(528-533)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266479
Dilillo LGirard PPravossoudovitch SVirazel ABastian M(2007)Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge CircuitsJournal of Electronic Testing: Theory and Applications10.1007/s10836-007-5003-923:5(435-444)Online publication date: 1-Oct-2007
https://dl.acm.org/doi/10.1007/s10836-007-5003-9
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MTDT '98: Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing

August 1998

ISBN:0818684941

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Published: 24 August 1998

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Di Carlo SPolitano GPrinetto PSavino AScionti A(2011)Genetic defect based march test generation for SRAMProceedings of the 2011 international conference on Applications of evolutionary computation - Volume Part II10.5555/2008445.2008463(141-150)Online publication date: 27-Apr-2011
https://dl.acm.org/doi/10.5555/2008445.2008463
Ney AGirard PLandrault CPravossoudovitch SVirazel ABastian MLauwereins RMadsen J(2007)Slow write driver faults in 65nm SRAM technologyProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266479(528-533)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266479
Dilillo LGirard PPravossoudovitch SVirazel ABastian M(2007)Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge CircuitsJournal of Electronic Testing: Theory and Applications10.1007/s10836-007-5003-923:5(435-444)Online publication date: 1-Oct-2007
https://dl.acm.org/doi/10.1007/s10836-007-5003-9
Dilillo LRosinger PAl-Hashimi BGirard PGielen G(2006)Minimizing test power in SRAM through reduction of pre-charge activityProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131802(1159-1164)Online publication date: 6-Mar-2006
https://dl.acm.org/doi/10.5555/1131481.1131802
Dilillo LGirard PPravossoudovitch SVirazel ABastian MJoyner WMartin GKahng A(2005)Resistive-open defect injection in SRAM core-cellProceedings of the 42nd annual Design Automation Conference10.1145/1065579.1065804(857-862)Online publication date: 13-Jun-2005
https://dl.acm.org/doi/10.1145/1065579.1065804
Dilillo LGirard PPravossoudovitch SVirazel ABorri S(2004)March iC-Proceedings of the 22nd IEEE VLSI Test Symposium10.5555/987684.987948Online publication date: 25-Apr-2004
https://dl.acm.org/doi/10.5555/987684.987948
Otterstedt JNiggemeyer DWilliams T(1998)Detection of CMOS address decoder open faults with March and pseudo random memory testsProceedings of the 1998 IEEE International Test Conference10.5555/648020.745777(53-62)Online publication date: 18-Oct-1998
https://dl.acm.org/doi/10.5555/648020.745777

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Generating Complete and Optimal March Tests for Linked Faults in Memories

Minimal March Tests for Dynamic Faults in Random Access Memories

March LR: a test for realistic linked faults

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