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On the Generation of Pseudo-Deterministic Two-Patterns Test Sequence with LFSRs

Authors:

Christian Dufaza,

Yervant ZorianAuthors Info & Claims

EDTC '97: Proceedings of the 1997 European conference on Design and Test

Page 69

Published: 17 March 1997 Publication History

Abstract

Many Built-in Self Test (BIST) pattern generators use Linear Feedback Shift Registers (LFSR) to generate test sequences. In this paper, we address the generation of deterministic pairs of patterns for delay faults testing with LFSRs. A new synthesis procedure for a n-size LFSR is given and guarantees that a deterministic set of n precomputed test pairs is embedded in the maximal length pseudo-random test sequence of the LFSR. Sufficient and necessary conditions for the synthesis of this pseudo-deterministic LFSR are provided and show that at-speed delay faults testing becomes a reality without any additional cost for the LFSR. Moreover, since the theoretical properties of LFSRs are preserved, our method could be beneficially used in conjunction with any other technique proposed so far.

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Cited By

Kerkhoff HSpeek HShashani MSachdev M(2001)Design for Delay Testability in High-Speed Digital ICsJournal of Electronic Testing: Theory and Applications10.1023/A:101220721078417:3-4(225-231)Online publication date: 1-Jun-2001
https://dl.acm.org/doi/10.1023/A%3A1012207210784
Li XCheung PFujiwara H(2000)LFSR-Based Deterministic TPG for Two-Pattern TestingJournal of Electronic Testing: Theory and Applications10.1023/A:100835631321216:5(419-426)Online publication date: 1-Oct-2000
https://dl.acm.org/doi/10.1023/A%3A1008356313212
Voyiatzis IPaschalis ANikolos DHalatsis C(1999)An Accumulator-Based BIST Approach for Two-Pattern TestingJournal of Electronic Testing: Theory and Applications10.1023/A:100834092517715:3(267-278)Online publication date: 1-Dec-1999
https://dl.acm.org/doi/10.1023/A%3A1008340925177
Show More Cited By

On the Generation of Pseudo-Deterministic Two-Patterns Test Sequence with LFSRs
1. Hardware

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Published In

cover image ACM Conferences

EDTC '97: Proceedings of the 1997 European conference on Design and Test

March 1997

596 pages

ISBN:0818677864

Copyright © Copyright (c) 1997 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

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SIGDA: ACM Special Interest Group on Design Automation

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IEEE Computer Society

United States

Publication History

Published: 17 March 1997

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EDTC96

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EDTC96: European Design and Test Conference

March 17 - 20, 1997

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Cited By

Kerkhoff HSpeek HShashani MSachdev M(2001)Design for Delay Testability in High-Speed Digital ICsJournal of Electronic Testing: Theory and Applications10.1023/A:101220721078417:3-4(225-231)Online publication date: 1-Jun-2001
https://dl.acm.org/doi/10.1023/A%3A1012207210784
Li XCheung PFujiwara H(2000)LFSR-Based Deterministic TPG for Two-Pattern TestingJournal of Electronic Testing: Theory and Applications10.1023/A:100835631321216:5(419-426)Online publication date: 1-Oct-2000
https://dl.acm.org/doi/10.1023/A%3A1008356313212
Voyiatzis IPaschalis ANikolos DHalatsis C(1999)An Accumulator-Based BIST Approach for Two-Pattern TestingJournal of Electronic Testing: Theory and Applications10.1023/A:100834092517715:3(267-278)Online publication date: 1-Dec-1999
https://dl.acm.org/doi/10.1023/A%3A1008340925177
Otterstedt JNiggemeyer DWilliams T(1998)Detection of CMOS address decoder open faults with March and pseudo random memory testsProceedings of the 1998 IEEE International Test Conference10.5555/648020.745777(53-62)Online publication date: 18-Oct-1998
https://dl.acm.org/doi/10.5555/648020.745777
Zorian YBederr H(1997)An Effective Multi-Chip BIST SchemeJournal of Electronic Testing: Theory and Applications10.1023/A:100822671592910:1-2(87-95)Online publication date: 1-Feb-1997
https://dl.acm.org/doi/10.1023/A%3A1008226715929

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