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research-article

BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms

Authors:

Sandeep K. GuptaAuthors Info & Claims

IEEE Transactions on Computers, Volume 45, Issue 3

Pages 257 - 269

https://doi.org/10.1109/12.485565

Published: 01 March 1996 Publication History

Abstract

Testing for delay and CMOS stuck-open faults requires two-pattern tests, and typically a large number of two pattern tests are needed. Built-in self-test (BIST) schemes are attractive for comprehensive testing of such faults. BIST test pattern generators (TPGs) for two-pattern testing, should be designed to ensure high transition coverage. In this paper, necessary and sufficient conditions to ensure complete/maximal transition coverage for linear feedback shift register (LFSR) and cellular automata (CA) have been derived. The theory developed here identifies all LFSR/CA TPGs that maximize transition coverage under any given TPG size constraint. It is shown that LFSRs with primitive feedback polynomials with large number of terms are better for two-pattern testing. Also, CA are shown to be better TPGs than LFSRs for two pattern testing, independent of their feedback rules. Based on the necessary sufficient conditions, efficient algorithms to design optimal TPGs for two-pattern testing have been developed. Experiments on benchmark circuits indicate that TPGs designed using the procedures outlined in this paper obtain high robust path delay fault coverage in short test lengths.

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Cited By

Voyiatzis IGizopoulos DPaschalis A(2010)Recursive pseudo-exhaustive two-pattern generationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.203130018:1(142-152)Online publication date: 1-Jan-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2031300
Polian IBecker B(2004)Scalable Delay Fault BIST for Use with Low-Cost ATEJournal of Electronic Testing: Theory and Applications10.1023/B:JETT.0000023681.25483.5920:2(181-197)Online publication date: 1-Apr-2004
https://dl.acm.org/doi/10.1023/B%3AJETT.0000023681.25483.59
Savir J(2000)Distributed BIST Architecture to Combat Delay FaultsJournal of Electronic Testing: Theory and Applications10.1023/A:100837001968516:4(369-380)Online publication date: 1-Aug-2000
https://dl.acm.org/doi/10.1023/A%3A1008370019685
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Published In

cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 45, Issue 3

March 1996

128 pages

ISSN:0018-9340

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Copyright © Copyright © 1996 IEEE. All Rights Reserved.

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IEEE Computer Society

United States

Publication History

Published: 01 March 1996

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Cited By

Voyiatzis IGizopoulos DPaschalis A(2010)Recursive pseudo-exhaustive two-pattern generationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.203130018:1(142-152)Online publication date: 1-Jan-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2031300
Polian IBecker B(2004)Scalable Delay Fault BIST for Use with Low-Cost ATEJournal of Electronic Testing: Theory and Applications10.1023/B:JETT.0000023681.25483.5920:2(181-197)Online publication date: 1-Apr-2004
https://dl.acm.org/doi/10.1023/B%3AJETT.0000023681.25483.59
Savir J(2000)Distributed BIST Architecture to Combat Delay FaultsJournal of Electronic Testing: Theory and Applications10.1023/A:100837001968516:4(369-380)Online publication date: 1-Aug-2000
https://dl.acm.org/doi/10.1023/A%3A1008370019685
Li XCheung PFujiwara H(2000)LFSR-Based Deterministic TPG for Two-Pattern TestingJournal of Electronic Testing: Theory and Applications10.1023/A:100835631321216:5(419-426)Online publication date: 1-Oct-2000
https://dl.acm.org/doi/10.1023/A%3A1008356313212
Mukherjee NChakraborty TBhawmik S(1998)A BIST scheme for the detection of path-delay faultsProceedings of the 1998 IEEE International Test Conference10.5555/648020.745938Online publication date: 18-Oct-1998
https://dl.acm.org/doi/10.5555/648020.745938
Otterstedt JNiggemeyer DWilliams T(1998)Detection of CMOS address decoder open faults with March and pseudo random memory testsProceedings of the 1998 IEEE International Test Conference10.5555/648020.745777(53-62)Online publication date: 18-Oct-1998
https://dl.acm.org/doi/10.5555/648020.745777
Savir J(1997)Scan Latch Design for Delay TestProceedings of the 1997 IEEE International Test Conference10.5555/844384.845860Online publication date: 1-Nov-1997
https://dl.acm.org/doi/10.5555/844384.845860
Dufaza CZorian Y(1997)On the Generation of Pseudo-Deterministic Two-Patterns Test Sequence with LFSRsProceedings of the 1997 European conference on Design and Test10.5555/787260.787652Online publication date: 17-Mar-1997
https://dl.acm.org/doi/10.5555/787260.787652

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