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WO2022199207A1 - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
WO2022199207A1
WO2022199207A1 PCT/CN2022/070291 CN2022070291W WO2022199207A1 WO 2022199207 A1 WO2022199207 A1 WO 2022199207A1 CN 2022070291 W CN2022070291 W CN 2022070291W WO 2022199207 A1 WO2022199207 A1 WO 2022199207A1
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WO
WIPO (PCT)
Prior art keywords
layer
contact structure
substrate
contact
forming
Prior art date
Application number
PCT/CN2022/070291
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English (en)
French (fr)
Inventor
郭帅
Original Assignee
长鑫存储技术有限公司
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Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Publication of WO2022199207A1 publication Critical patent/WO2022199207A1/zh
Priority to US18/149,724 priority Critical patent/US20230142435A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Definitions

  • the present disclosure relates to, but is not limited to, a semiconductor structure and a method of fabricating the same.
  • DRAM Dynamic Random Access Memory
  • bit binary bit
  • An embodiment of the present disclosure provides a semiconductor structure, including: a first substrate including bit lines, transistors and a first contact structure arranged in a stack; a second substrate bonded to the first substrate, the The second substrate includes a stacked second contact structure and a capacitor, and the second contact structure is in direct contact with the first contact structure; wherein the first contact structure has a first contact structure facing the second substrate. a surface and a second surface opposite to the first surface, and the area of the first surface is larger than that of the second surface; the second contact structure has a third surface facing the first substrate; and The fourth surface is opposite to the third surface, and the area of the third surface is larger than that of the fourth surface.
  • the area of the first side is larger than the area of the third side.
  • the area of the first side is 5 to 20 times the area of the third side.
  • the transistor is a vertical transistor, and the vertical transistor includes a source electrode, a channel region and a drain electrode sequentially stacked on the bit line; the drain electrode and the first contact structure It also includes: a word line, the word line is connected with the channel region; the bit line extends in a first direction, the word line extends in a second direction, and the first direction is connected with the first direction The two directions are different.
  • the word there are a plurality of the vertical transistors, a plurality of the first contact structures, and the plurality of the first contact structures are connected to the plurality of the vertical transistors in one-to-one correspondence; the word There are a plurality of lines, and one of the word lines connects the channel regions of a plurality of the vertical transistors.
  • the capacitor includes a lower electrode, an upper electrode, and a dielectric layer between the upper electrode and the lower electrode, and the lower electrode is connected to the second contact structure.
  • the capacitor includes a first part and a second part, wherein the connection between the first part and the second part has an inflection point; the first part includes part of the upper electrode and part of the lower electrode and part of the dielectric layer; the second part includes part of the upper electrode, part of the lower electrode and part of the dielectric layer.
  • the upper electrodes are connected, and the dielectric layers of the plurality of capacitors are connected.
  • the second substrate further includes: a plurality of discrete electrode pads, the electrode pads are connected to the upper electrodes of the capacitor in a one-to-one correspondence, and the cross-sectional topography of the electrode pads is trapezoidal, so The height of the trapezoid is greater than the length of the parallel sides of the trapezoid.
  • the first contact structure includes a first-contact structure and a first-second contact structure arranged in layers, and the first-contact structure is located on a side away from the second substrate, and the first-contact structure is located on a side away from the second substrate.
  • a two-contact structure is located on a side close to the second substrate;
  • the second contact structure includes a second-first contact structure and a second-second contact structure arranged in layers, and the second-first contact structure is located close to the second contact structure.
  • the second two-contact structure is located on a side away from the first substrate; wherein, the contact area between the first one-contact structure and the transistor is larger than that between the first two-contact structure and all the transistors.
  • the contact area of the second-first contact structure, the contact area of the second-second contact structure and the capacitor is smaller than the contact area of the first-second contact structure and the second-first contact structure.
  • the hardness of the first-first contact structure is greater than the hardness of the first-second contact structure; the hardness of the second-second contact structure is greater than the hardness of the second-first contact structure; the first The melting point of the second contact structure is lower than the melting point of the first first contact structure; the melting point of the second first contact structure is lower than the melting point of the second second contact structure.
  • a cross-sectional topography of the first-first contact structure is a square, and a cross-sectional topography of the first-second contact structure is a trapezoid;
  • the cross-sectional topography of the second-second contact structure is square, and the cross-sectional topography of the second-first contact structure is trapezoidal.
  • the contact area of the first contact structure and the transistor is larger than the contact area of the first second contact structure and the second first contact structure, and the first contact structure and the first contact structure The resistances of the two contact structures are the same.
  • Embodiments of the present disclosure further provide a method for fabricating a semiconductor structure, including: providing a first substrate, the first substrate including a stacked bit line, a transistor and a first contact structure; and providing a second substrate, the second substrate comprising a second contact structure and a capacitor arranged in a stack; bonding the first substrate and the second substrate, and the first contact structure is in direct contact with the second contact structure; wherein, the first The contact structure has a first surface facing the second substrate and a second surface opposite to the first surface, and the area of the first surface is larger than that of the second surface; the second contact structure has A third surface facing the first substrate and a fourth surface opposite to the third surface, and the area of the third surface is larger than that of the fourth surface.
  • the transistor is a vertical transistor
  • the method for forming the vertical transistor includes: providing a first substrate, and forming a stacked source isolation layer, a first sacrificial layer on the first substrate layer and drain isolation layer, forming a plurality of third through holes through the source isolation layer, the first sacrificial layer and the drain isolation layer, the third through holes expose the top surface of the bit line forming a stacked source electrode, a channel region and a drain electrode in the third through hole, the source electrode, the channel region and the drain electrode constitute the vertical transistor; forming the vertical transistor
  • the method further includes: forming a first trench penetrating the drain isolation layer and the first sacrificial layer, the first trench extending along a second direction, the second direction and the first direction different; after the first trench is formed, the first sacrificial layer is removed to form a word line filling region; an initial word line layer filling the word line filling region is formed, and the initial word line layer is also filled with all the
  • the step of forming the first contact structure includes: forming a first insulating layer on the transistor; forming a first through hole in the first insulating layer; Carrying out hole reaming treatment at the top, so that the area of the top of the first through hole is larger than the area of the bottom of the first through hole; forming the first contact structure filling the first through hole; forming the second contact
  • the steps of the structure include: forming a second insulating layer on the capacitor; forming a second through hole in the second insulating layer; The area of the top of the through hole is larger than the area of the bottom of the second through hole; the second contact structure filling the second through hole is formed.
  • the step of forming the first through hole includes: forming a first-first stabilizing layer, a first-dielectric layer, a first-second stabilizing layer, and a first-second dielectric layer on the drain electrode. layer and the first three stable layer; the first one stable layer, the first one dielectric layer, the first two stable layer, the first two dielectric layer and the first three stable layer constitute the a first insulating layer; forming a first pass through the first-stable layer, the first-dielectric layer, the first-two-stable layer, the first-two dielectric layer and the first three-stable layer holes; removing part of the first three stable layers and the first two dielectric layers, so that the area of the top of the first through hole is larger than the area of the bottom of the first through hole; the formation of the second through hole
  • the step includes: forming a second first dielectric layer, a second first stabilization layer, a second second dielectric layer and a second second stabilization layer on the capacitor; the second first stabilization layer, the
  • the step of forming the capacitor includes: providing a second substrate, and forming a stacked third support layer, a first capacitor isolation layer and a first support layer on the second substrate; the third support layer, the first capacitive isolation layer and the first groove of the first support layer, and the width of the bottom surface of the first groove is smaller than the width of the opening of the first groove; A second sacrificial layer of the first groove; forming a second capacitive isolation layer and a second supporting layer on the first supporting layer and the second sacrificial layer; forming through the second capacitive isolation layer and the first The second groove of the two supporting layers, the second groove exposes the top surface of the second sacrificial layer, and the bottom width of the second groove is smaller than the top surface width of the filling layer; remove the first two sacrificial layers to expose the first groove; an upper electrode is formed on the surfaces of the first groove and the second groove, and the upper electrode also covers the top surface of the second support layer; A dielectric layer is formed on the
  • the first capacitive isolation layer before forming the first capacitive isolation layer, it further includes forming an electrode pad, and the step of forming the electrode pad includes: forming a stacked electrode pad isolation layer and a fourth electrode pad on the second substrate a support layer, forming a third groove penetrating the electrode pad isolation layer and the fourth support layer, and part of the third groove is also located in the second substrate; forming an electrode filling the third groove pad;
  • the upper electrode is also in contact with the electrode pad.
  • the bonding further includes the steps of: forming a first recess on a side of the first contact structure facing the second substrate; and forming a first recess on a side of the first contact structure facing the first substrate; A second concave portion is formed on one side of the bonding device; the temperature of the bonding is 400°C to 500°C, and the pressure of the bonding is 20kN to 60kN.
  • FIG. 1 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of a semiconductor structure corresponding to a step of forming alternately arranged isolation structures and bit lines in a first substrate in a manufacturing method according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of a semiconductor structure corresponding to a step of forming a transistor on a first substrate in a manufacturing method provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic cross-sectional view of FIG. 3 in a first direction.
  • FIG. 5 is a schematic diagram of a semiconductor structure corresponding to a step of forming a first trench in a manufacturing method according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic cross-sectional view of FIG. 5 in a first direction.
  • FIG. 7 is a schematic diagram of a semiconductor structure corresponding to a step of forming an initial word line layer filling a word line filling region in a manufacturing method according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a semiconductor structure corresponding to a step of removing a part of an initial word line layer to form separate word lines in a manufacturing method according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic cross-sectional view of FIG. 8 in a first direction.
  • FIG. 10 is a schematic diagram of a semiconductor structure corresponding to a step of forming a word line isolation layer filling the first trench in a manufacturing method provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of a semiconductor structure corresponding to a step of forming a first insulating layer and a first through hole on a transistor in a manufacturing method provided by an embodiment of the disclosure.
  • FIG. 12 is a schematic diagram of a semiconductor structure corresponding to a step of forming a first contact structure filling the first via hole in the manufacturing method provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of a semiconductor structure corresponding to a step of forming a first recess on a first contact structure in a manufacturing method according to an embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram of a semiconductor structure corresponding to a step of forming an electrode pad in a manufacturing method according to an embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram of a semiconductor structure corresponding to the steps of forming a third support layer, a first capacitive isolation layer and a first support layer on a second substrate in a manufacturing method provided by an embodiment of the present disclosure.
  • 16 is a schematic diagram of a semiconductor structure corresponding to the step of forming a second sacrificial layer filling the first groove in the manufacturing method provided by an embodiment of the present disclosure.
  • 17 is a schematic diagram of a semiconductor structure corresponding to the step of forming a second groove penetrating the second capacitive isolation layer and the second support layer in the manufacturing method provided by an embodiment of the present disclosure.
  • FIG. 18 is a schematic diagram of a semiconductor structure corresponding to the step of forming a capacitor in the first groove and the second groove in the manufacturing method provided by an embodiment of the present disclosure.
  • FIG. 19 is a schematic diagram of a semiconductor structure corresponding to the steps of forming a second insulating layer and a second through hole on a capacitor in a manufacturing method provided by an embodiment of the present disclosure.
  • FIG. 20 is a schematic diagram of a semiconductor structure corresponding to the steps of forming a second two-contact structure and a second one-contact structure in a second through hole in a manufacturing method provided by an embodiment of the present disclosure.
  • FIG. 21 is a schematic diagram of a semiconductor structure corresponding to the step of forming the second recess on the second contact structure in the manufacturing method according to an embodiment of the disclosure.
  • Embodiments of the present disclosure provide a semiconductor structure.
  • the semiconductor structure includes a first substrate and a second substrate bonded to the first substrate.
  • the manufacturing process can be performed on the first substrate and the second substrate at the same time. Shorten product production cycle.
  • the first contact structure has a first surface facing the second substrate and a second surface opposite to the first surface, and the area of the first surface is larger than that of the second surface; the second contact structure has a first surface facing the first substrate.
  • the first contact structure and the second contact structure can have a larger contact area, so as to reduce the contact resistance, reduce the difficulty of alignment, and avoid the bad influence of the alignment error on the semiconductor structure. Therefore, the embodiments of the present disclosure can improve the production efficiency, reduce the production difficulty, and improve the performance of the semiconductor structure.
  • the transistors are vertical transistors. Compared with planar transistors, vertical transistors have higher space utilization in the vertical direction and occupy a smaller area in the horizontal direction, which is conducive to reducing the feature size of the semiconductor structure.
  • FIG. 1 is a schematic diagram of the semiconductor structure.
  • the semiconductor structure includes: a first substrate 1 including a stacked bit line 103 , a transistor 11 and a first contact structure 12 ; a second substrate 2 bonded to the first substrate 1 , the second The substrate 2 includes a stacked second contact structure 22 and a capacitor 23, and the second contact structure 22 is in direct contact with the first contact structure 12; wherein, the first contact structure 12 has a first surface facing the second substrate 2 and is in contact with the first contact structure 12.
  • the second surface is opposite to the first surface, and the area of the first surface is larger than that of the second surface; the second contact structure 22 has a third surface facing the first substrate 1 and a fourth surface opposite to the third surface, and the second contact structure 22 has a third surface opposite to the third surface.
  • the area of the three sides is greater than the area of the fourth side.
  • the first substrate 1 also includes a first substrate 101 .
  • the material of the first substrate 101 is a semiconductor, such as silicon or germanium.
  • the material of the first substrate may also be an insulating material, such as silicon oxide or silicon nitride.
  • the bit line 103 is located in the first substrate 101 , and the first substrate 101 exposes the top surface of the bit line 103 .
  • the bit line 103 extends in the first direction.
  • the material of the bit line 103 can be a low resistance metal such as tungsten, tantalum, gold or silver.
  • Isolation structures 105 are used to isolate adjacent bit lines 103 .
  • the isolation structure 105 is located in the first substrate 101 , and the first substrate 101 exposes the top surface of the isolation structure 105 .
  • the isolation structure 105 and the bit line 103 are separated from each other.
  • the isolation structure includes a conductive structure, such as a conductive metal line (such as tungsten, ruthenium, etc.) or a conductive semiconductor line (such as polysilicon, etc.), the metal line or semiconductor line is parallel to the bit line 103, and the metal line or semiconductor line
  • the line can be configured with a constant potential, for example, the metal line or semiconductor line is configured to be grounded, and the adjacent bit lines 103 are isolated by the grounded metal line or semiconductor line, which can reduce the mutual interference between the adjacent bit lines 103 and improve the device. performance.
  • the transistor 11 is a vertical transistor. Compared with planar transistors, vertical transistors have higher space utilization in the vertical direction and occupy a smaller area in the horizontal direction, which is conducive to reducing the feature size of the semiconductor structure. In other embodiments, the transistor 11 may also be a planar transistor.
  • the vertical transistors are arranged in an array.
  • the vertical transistor includes a source electrode 111 , a channel region 110 and a drain electrode 112 sequentially stacked on the bit line 103 .
  • the source electrode 111 , the channel region 110 and the drain electrode 112 are all made of silicon, and the source electrode 111 and the drain electrode 112 have more dopant ions, and the dopant ions can be boron or phosphorus.
  • the material of the source electrode, the channel region and the drain electrode can also be germanium.
  • Source isolation layer 106 between adjacent source electrodes 111
  • drain isolation layer 108 between adjacent drain electrodes 112 .
  • the material of the source isolation layer 106 is an insulating material, such as silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, and the like.
  • the material of the drain isolation layer 108 is an insulating material, such as silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, or the like.
  • the first substrate 1 further includes: word lines 109 , and the word lines 109 are connected to the channel region 110 .
  • word lines 109 There are a plurality of word lines 109, and one word line 109 is connected to the channel regions 110 of the plurality of vertical transistors.
  • the word lines 109 extend in a second direction, and the first direction is different from the second direction.
  • the first direction is perpendicular to the second direction.
  • the included angle between the first direction and the second direction may be greater than or equal to 75° and less than 90°.
  • the material of the word line 109 can be a low resistance metal such as tungsten, tantalum, gold or silver.
  • There are multiple first contact structures 12 and the multiple first contact structures 12 are connected to the multiple vertical transistors in one-to-one correspondence; the drains 112 of the vertical transistors are connected to the first contact structures 12 .
  • the first contact structure 12 is used for connecting with the second contact structure 22 to bond the first substrate 1 and the second substrate 2 .
  • There are also multiple second contact structures 22 and the multiple second contact structures 22 are connected to the multiple first contact structures 12 in one-to-one correspondence.
  • the first contact structure 12 and the second contact structure 22 will be described in detail below.
  • the first contact structure 12 has a first surface facing the second substrate 2 and a second surface opposite to the first surface, and the area of the first surface is larger than that of the second surface;
  • the second contact structure 22 has a surface facing the first substrate 1
  • the third surface and the fourth surface opposite to the third surface, and the area of the third surface is larger than that of the fourth surface. That is, the first and third surfaces are bonding surfaces, while the second and fourth surfaces are non-bonding surfaces. Since the bonding surface has a larger area relative to the non-bonding surface, the bonding surface has a smaller contact resistance, and the operation speed of the semiconductor structure is faster.
  • the larger area of the bonding surface can reduce the difficulty of aligning the first substrate 1 and the second substrate 2, and can also avoid the adverse effects of alignment errors on the semiconductor structure.
  • the area of the first surface is larger than that of the third surface. In this way, the problem that one capacitor 23 is electrically connected to two transistors 11 at the same time can be prevented when an alignment error occurs.
  • the area of the first surface is 5 to 20 times the area of the third surface.
  • the first side has a length and width of 40 nm and an area of 1600 nm 2
  • the third side has a length and width of 10 nm and an area of 100 nm 2 .
  • the first contact structure 12 may include a semiconductor conductive layer epitaxially grown on the drain electrode 112, such as epitaxial silicon or epitaxial germanium, etc.
  • the semiconductor conductive layer grown by epitaxial growth has a lower contact resistance with the drain electrode.
  • the larger contact area of the contact structure 12 can further reduce the resistance of the first contact structure 12; the second contact structure 22 includes a metal layer that is electrically connected to the capacitor 23. Since the resistance of the metal layer is smaller than that of the semiconductor conductive layer, it can be set The smaller area of the third surface of the second contact structure 22 makes the resistance of the first contact structure 12 match the resistance of the second contact structure 22 , for example, the two have the same resistance, so as to improve device performance.
  • the first contact structure 12 and the second contact structure 22 are double-layer structures.
  • the first contact structure 12 includes a first-contact structure 121 and a first-second contact structure 122 arranged in layers, and the first-contact structure 121 is located on a side away from the second substrate 2 , and the first-contact structure 122 is located close to the second contact structure 121 . side of base 2.
  • the second contact structure 22 includes a second first contact structure 221 and a second second contact structure 222 arranged in layers, and the second first contact structure 221 is located on the side close to the first substrate 1 , and the second second contact structure 222 is located away from the first contact structure 221 . side of substrate 1.
  • the first first contact structure 121 is in contact with the transistor 11
  • the first second contact structure 122 is in contact with the second first contact structure 221
  • the second second contact structure 222 is in contact with the capacitor 23 .
  • the contact area of the first two contact structure 121 and the transistor 11 is larger than the contact area of the first two contact structure 122 and the second one contact structure 221, and the contact area of the second two contact structure 222 and the capacitor 23 is smaller than that of the first two contact structure 122 and the contact area of the second first contact structure 221 .
  • This arrangement can not only reduce the resistance of the first contact structure 12 and the on-resistance between the first contact structure 12 and the transistor 11 , but also reduce the difficulty of alignment and avoid adverse effects of alignment errors on the semiconductor structure.
  • the first-contact structure 121 can be a semiconductor conductive layer epitaxially grown on the drain 112, such as epitaxial silicon or epitaxial germanium, etc.
  • the semiconductor conductive layer grown by epitaxial has a lower contact resistance with the drain, the first-second contact
  • the contact structure 122 and the second contact structure 22 may be metal conductors such as metal tungsten.
  • the resistance of the first contact structure 12 and the resistance of the second contact structure 22 can be set to match, for example, the resistances of the two are the same, so as to improve device performance.
  • the cross-sectional shape of the first-first contact structure 121 is square, and the cross-sectional shape of the first-second contact structure 122 is trapezoidal;
  • the cross-sectional shape of the second-two contact structure 222 is square, and the cross-sectional shape of the second-first contact structure 221 is trapezoidal.
  • the cross-sectional topography of the first and second contact structures may be trapezoidal, the cross-sectional topography of the first and second contact structures may be square; the cross-sectional topography of the second and second contact structures may be trapezoidal, and the cross-sectional topography of the second and second contact structures
  • the cross-sectional shape can be square.
  • the hardness of the first-first contact structure 121 is greater than that of the first-second contact structure 122 ; the melting point of the first-second contact structure 122 is lower than the melting point of the first-first contact structure 121 .
  • the hardness of the second second contact structure 222 is greater than the hardness of the second first contact structure 221 ; the melting point of the second first contact structure 221 is lower than the melting point of the second second contact structure 222 .
  • the strength of the semiconductor structure can be improved.
  • the bonding between the first second contact structure 122 and the second first contact structure 221 can be relatively firm at a lower bonding temperature .
  • the excessive bonding temperature can also avoid adverse effects on the semiconductor structure.
  • the material of the first second contact structure 122 and the second first contact structure 221 may be copper, gold or silver.
  • the material of the first first contact structure 121 and the second second contact structure 222 may be tungsten or molybdenum.
  • first insulating layer 13 for isolating the adjacent first contact structures 12, the first insulating layer 13 is a multi-layer structure, and includes a first-stabilizing layer 131, a first-dielectric layer 132, a Two stable layers 133 , first two dielectric layers 134 and first three stable layers 135 .
  • the first first stable layer 131 , the first second stable layer 133 and the first third stable layer 135 are used to support the first contact structure 12 , so that the first contact structure 12 has greater firmness to avoid problems such as collapse or tilt. .
  • the materials of the first first stabilization layer 131 , the first second stabilization layer 133 , and the first third stabilization layer 135 have relatively high strength, and may be silicon nitride, for example.
  • the first first dielectric layer 132 and the first second dielectric layer 134 are used to isolate the adjacent first contact structures 12 and reduce the parasitic capacitance between the adjacent first contact structures 12. Therefore, the first first dielectric layer 132 and the first The material of the second dielectric layer 134 has a relatively small dielectric constant, such as silicon oxide.
  • the second insulating layer 21 includes a second second stable layer 211, a second second dielectric layer 212, a second first stable layer 213, The second first dielectric layer 214 .
  • the second second dielectric layer 212 and the second first dielectric layer 214 can reduce the parasitic capacitance between adjacent second contact structures 22 , so the material thereof has a relatively small dielectric constant, such as silicon oxide.
  • the second two-stabilizing layer 211 and the second first-stabilizing layer 213 can support the second contact structure 22, so the material thereof has greater strength, such as silicon nitride.
  • the capacitors 23 are connected to the second contact structures 22 , wherein there are multiple capacitors 23 , and the multiple capacitors 23 are connected to the multiple second contact structures 22 in one-to-one correspondence.
  • the capacitor 23 will be specifically described below.
  • the capacitor 23 includes a lower electrode 231 , an upper electrode 232 and a dielectric layer 233 between the upper electrode 232 and the lower electrode 231 , and the lower electrode 231 is connected to the second contact structure 22 .
  • the upper electrodes 232 of the plurality of capacitors 23 are connected to each other, and the dielectric layers 233 of the plurality of capacitors 23 are connected to each other.
  • the upper electrodes of the multiple capacitors may also be separated from each other, and the dielectric layers of the multiple capacitors may also be separated from each other.
  • the material of the upper electrode 232 is a conductive material, such as titanium or titanium nitride.
  • the material of the lower electrode 231 is a conductive material, such as titanium or titanium nitride.
  • the material of the dielectric layer 233 has a relatively large dielectric constant, such as zirconium oxide, aluminum oxide, hafnium oxide, and the like.
  • the capacitor 23 includes a first part and a second part, wherein the connection between the first part and the second part has an inflection point; the first part includes part of the upper electrode 232, part of the lower electrode 231 and part of the dielectric layer 233; the second part includes part of the upper electrode 232, Part of the lower electrode 231 and part of the dielectric layer 233 .
  • the connection between the first part and the second part has a corner, the relative area between the dielectric layer 233 and the upper electrode 232 and the lower electrode 231 can be increased to improve the storage capacity.
  • the stability of the capacitor 23 with the inflection point is better.
  • It also includes: a second support layer 244 , a second capacitor isolation layer 243 , a first support layer 242 , a first capacitor isolation layer 241 and a third support layer 248 that are stacked between adjacent capacitors 23 .
  • the third support layer 248 , the second support layer 244 and the first support layer 242 are used to support the capacitor 23 , so that the capacitor 23 has greater firmness to avoid problems such as collapse or tilt.
  • the materials of the third support layer 248, the second support layer 244 and the first support layer 242 have relatively high strength, such as silicon nitride.
  • the second capacitive isolation layer 243 and the first capacitive isolation layer 241 are used to isolate the adjacent capacitors 23 and reduce the parasitic capacitance between the adjacent capacitors 23. Therefore, the materials of the second capacitive isolation layer 243 and the first capacitive isolation layer 241 Has a small dielectric constant, such as silicon oxide.
  • the second substrate 2 further includes: a plurality of discrete electrode pads 202, the electrode pads 202 are connected to the upper electrodes 232 of the capacitor 23 in a one-to-one correspondence, and the cross-sectional topography of the electrode pads 202 is a trapezoid, and the height of the trapezoid is greater than the side of the parallel side of the trapezoid
  • the long, trapezoidal height can range from 100 nm to 1500 nm, such as 500 nm, 800 nm, 1200 nm, and the like.
  • the capacitor 23 is in contact with a parallel side of the trapezoid, and the length of the parallel side of the trapezoid is smaller, that is, the space position occupied by the electrode pads 202 in the horizontal direction is smaller, the distance between the adjacent electrode pads 202 is larger, and the electrode pads 202 are embedded.
  • the deeper depth into the second substrate 201 can further enhance the stability of the capacitor 23 in the second substrate 2 .
  • the material of the electrode pad 202 may be tungsten or molybdenum.
  • the electrode pad isolation layers 203 can isolate the electrode pads 202.
  • the material of the electrode pad isolation layers 203 can be silicon oxide.
  • the fourth support layer 204 may play a supporting role for the electrode pad 202, and the material of the fourth support layer 204 may be silicon nitride.
  • the manufacturing process can be performed on the first substrate 1 and the second substrate 2 at the same time, which can shorten the product production cycle.
  • the first contact structure 12 and the second contact structure 22 have a larger area of bonding surface, so as to reduce the resistance of the bonding surface, reduce the difficulty of alignment, and also avoid the adverse effects of alignment errors on the semiconductor structure. . Therefore, the embodiments of the present disclosure can improve the production efficiency, reduce the production difficulty, and improve the performance of the semiconductor structure.
  • FIGS. 2 to 21 are schematic diagrams corresponding to each step in the method for fabricating a semiconductor structure provided in this embodiment.
  • the materials and shapes inside the semiconductor structure please refer to the first embodiment, which will not be repeated here.
  • a first substrate 1 is provided, and the substrate includes a stacked bit line 103, a transistor 11 and a first contact structure 12; a second substrate 2 is provided, and the second substrate 2 includes a stacked second contact structure 22 and capacitors 23. ; Bond the first substrate 1 and the second substrate 2, and the first contact structure 12 and the second contact structure 22 are in direct contact.
  • Bonding means that under certain temperature and pressure conditions, the atoms at the bonding interface undergo physical and chemical reactions under the action of external energy. Under the forces such as van der Waals force and Coulomb force, the first substrate 1 and the second substrate 2 are combined. together.
  • the bonding temperature is 400° C. to 500° C.
  • the bonding pressure is 20 kN to 60 kN.
  • the bonding temperature is within the above-mentioned range, atomic diffusion between the first contact structure 12 and the second contact structure 22 can be accelerated, thereby enhancing the adhesion between the two.
  • the bonding pressure is in the above range, the firmness of the bonding can be improved.
  • the first contact structure 12 has a first surface facing the second substrate 2 and a second surface opposite to the first surface, and the area of the first surface is larger than that of the second surface; the second contact structure 22 has a surface facing the first surface The third surface of the substrate 1 and the fourth surface opposite to the third surface, and the area of the third surface is larger than that of the fourth surface.
  • the first and third surfaces are bonding surfaces, while the second and fourth surfaces are non-bonding surfaces. Since the bonding surface has a larger area relative to the non-bonding surface, the bonding surface has a smaller contact resistance, and the operation speed of the semiconductor structure is faster.
  • the larger area of the bonding surface can reduce the difficulty of aligning the first substrate 1 and the second substrate 2, and can also avoid the adverse effects of alignment errors on the semiconductor structure. The larger the area of the bonding surface, the stronger the bonding can be.
  • the steps of forming the first substrate 1 will be specifically described below.
  • a first substrate 101 is provided, and alternately arranged isolation structures 105 and bit lines 103 are formed in the first substrate 101. Both the isolation structures 105 and the bit lines 103 extend in a first direction, and the first substrate 101 is exposed. Top surface of bit line 103 and isolation structure 105 .
  • the isolation structure 105 is formed before the bit line 103 .
  • the steps of forming the isolation structure 105 and the bit line 103 include: forming a stacked structure of a silicon oxide layer and a silicon nitride layer on the first substrate 101; forming a patterned photoresist layer on the stacked structure;
  • the photoresist layer is a mask, and the stacked structure of the silicon oxide layer and the silicon nitride layer and the first substrate 101 are etched to form the isolation structure in the first substrate 101 to fill the trench, and the isolation structure to fill the trench
  • the groove extends along the first direction; after the isolation structure is formed to fill the trench, the photoresist is removed; the chemical vapor deposition process is used to form an initial isolation structure in the isolation structure filled trench, and the initial isolation structure is also located in the stack of silicon oxide and silicon nitride.
  • bit line may be formed first, and then the isolation structure may be formed.
  • the isolation structure includes a conductive structure, such as a conductive metal line (such as tungsten, ruthenium, etc.) or a conductive semiconductor line (such as polysilicon, etc.), the metal line or semiconductor line is parallel to the bit line 103, and the metal line or semiconductor line is parallel to the bit line 103.
  • the wire or semiconductor wire can be configured with a constant potential, for example, the metal wire or semiconductor wire can be configured to be grounded, and the adjacent bit lines 103 are isolated by the grounded metal wire or semiconductor wire, which can reduce the mutual interference between adjacent bit lines 103 , to improve device performance.
  • a transistor 11 is formed on the first substrate 101 , and the transistor 11 is a vertical transistor.
  • a source isolation layer 106 , a first sacrificial layer 107 and a drain isolation layer 108 are formed on the first substrate 101 in a stacked manner.
  • the source isolation layer 106 , the first sacrificial layer 107 and the drain isolation layer 108 are formed by chemical vapor deposition.
  • a plurality of third through holes 102 are formed through the source isolation layer 106 , the first sacrificial layer 107 and the drain isolation layer 108 , and the third through holes 102 expose the top surface of the bit line 103 .
  • the third through hole 102 is formed by a dry etching method.
  • FIG. 4 is a cross-sectional view of FIG. 3 in a first direction.
  • a source electrode 111 , a channel region 110 and a drain electrode 112 are formed in a stacked arrangement in the third through hole 102 , and the source electrode 111 , the channel region 110 and the drain electrode 112 constitute a vertical transistor.
  • a first semiconductor pillar is formed on the bit line 103 by selective epitaxial growth, the top surface of the first semiconductor pillar is flush with the top surface of the source isolation layer 106, and ion implantation is performed on the first semiconductor pillar to form a source Pole 111.
  • a second semiconductor pillar is formed on the source electrode 111 by selective epitaxial growth, the top surface of the second semiconductor pillar is flush with the top surface of the first sacrificial layer 107 , and the second semiconductor pillar serves as the channel region 110 .
  • a third semiconductor pillar is formed on the channel region 110 by a method of selective epitaxial growth, and ion implantation is performed on the third semiconductor pillar to form the drain electrode 112 .
  • the material of the first semiconductor pillar, the second semiconductor pillar and the third semiconductor pillar is silicon, and in other embodiments, the material of the first semiconductor pillar, the second semiconductor pillar and the third semiconductor pillar can also be germanium .
  • the doping ions of the first semiconductor column and the third semiconductor column are the same, for example, both can be phosphorus or both can be boron.
  • FIG. 6 is a cross-sectional view of FIG. 5 in a first direction.
  • a first trench 104 is formed through the drain isolation layer 108 and the first sacrificial layer 107 (refer to FIG. 4 ), and the first trench 104 extends in a second direction different from the first direction.
  • the first direction is perpendicular to the second direction.
  • the included angle between the first direction and the second direction may be greater than or equal to 75° and less than 90°.
  • the first trench 104 also penetrates the source isolation layer 106 .
  • the first trench may only penetrate the drain isolation layer and the first sacrificial layer.
  • the first trench 104 is formed by a dry etching method.
  • a silicon nitride layer is also formed on the drain isolation layer 108 and the drain 112 prior to dry etching. In dry etching, part of the silicon nitride layer is also removed. After dry etching, the remaining silicon nitride layer is removed. The silicon nitride layer can improve the precision of the etching pattern.
  • the first sacrificial layer 107 (refer to FIG. 4 ) is removed to form the word line filling region 109a.
  • the first sacrificial layer 107 is removed by wet etching.
  • the formed word line filling region 109a is the space occupied by the original first sacrificial layer 107 .
  • an initial word line layer 109b filling the word line filling region 109a is formed, and the initial word line layer 109b also fills the first trench 104 (refer to FIG. 6).
  • the chemical vapor deposition method is used to form the initial word line layer 109b.
  • the physical vapor deposition method can also be used to form the initial word line layer.
  • FIG. 9 is a cross-sectional view of FIG. 8 in a first direction.
  • a portion of the initial word line layer 109b is removed to form mutually discrete word lines 109, and the first trenches 104 are exposed. That is, the remaining initial word line layer 109b serves as the word line 109, and the first trench 104 divides the word line 109.
  • a dry etching method is used to remove part of the initial word line layer 109b.
  • word line isolation layers 113 filling the first trenches 104 are formed.
  • the word line isolation layer 113 is an insulating material, such as silicon oxide or silicon nitride, for isolating adjacent word lines 109 .
  • the steps of forming the first contact structure 12 include: forming a first insulating layer 13 on the transistor 11 ; forming a first through hole 136 in the first insulating layer 13 ; The hole reaming process is performed so that the area of the top of the first through hole 136 is larger than the area of the bottom of the first through hole 136 ; the first contact structure 12 filling the first through hole 136 is formed.
  • the first insulating layer 13 is a multi-layer structure, and the steps of forming the first through holes 136 include: referring to FIG. 132, the first two stable layers 133, the first two dielectric layers 134 and the first three stable layers 135; the first one stable layer 131, the first one dielectric layer 132, the first two stable layers 133, the first two dielectric layers 134 and the first tristable layer 135 constitute the first insulating layer 13 .
  • the chemical vapor deposition method is used to form the first insulating layer 13 .
  • first through holes 136 penetrating the first-first stable layer 131, the first-dielectric layer 132, the first-second stable layer 133, the first-second dielectric layer 134 and the first three-stable layer 135; removing part of the first three-stable layer 135 and the first and second dielectric layers 134 , so that the area of the top of the first through hole 136 is larger than the area of the bottom of the first through hole 136 .
  • the first through holes 136 are formed by a dry etching method, and the first through holes 136 are expanded by a dry etching method.
  • a first two-contact structure 122 and a first one-contact structure 121 that are stacked and disposed are formed in the first through hole 136 (refer to FIG. 11 ).
  • the first two contact structure 122 and the first one contact structure 121 are formed by epitaxial growth and chemical vapor deposition, respectively.
  • the physical vapor deposition method can also be used to form the first two-contact structure and the first one-contact structure.
  • a first recess 123 is formed on the side of the first contact structure 12 facing the second substrate 2 (refer to FIG. 1 ). That is, the first concave portion 123 is formed on the bonding surface of the first-contact structure 12 .
  • the first recessed portion 123 can be formed .
  • the chemical mechanical polishing method is used to form the first concave portion 123 .
  • the step of forming the electrode pad 202 includes: forming a stacked electrode pad isolation layer 203 and a fourth supporting layer 204 on the second substrate 201 ; There are three grooves, and some of the third grooves are also located in the second substrate 201 .
  • the third groove is formed by dry etching.
  • Electrode pads 202 filling the third grooves are formed.
  • the electrode pad 202 is formed by a physical vapor deposition method.
  • the electrode pad can also be formed by chemical vapor deposition.
  • the steps of forming the capacitor 23 include:
  • a second substrate 201 is provided, and a third support layer 248 , a first capacitive isolation layer 241 and a first support layer 242 are formed in a stacked arrangement on the second substrate.
  • the chemical vapor deposition method is used to form the third support layer 248 , the first capacitor isolation layer 241 and the first support layer 242 .
  • a first groove 245 is formed through the third support layer 248 , the first capacitive isolation layer 241 and the first support layer 242 , and the bottom surface width of the first groove 245 is smaller than the opening width of the first groove 245 .
  • the first groove 245 is formed by a dry etching method.
  • a second sacrificial layer 246 filling the first grooves 245 is formed.
  • the material of the second sacrificial layer 246 is amorphous silicon.
  • a second capacitive isolation layer 243 and a second support layer 244 are formed on the first support layer 242 and the second sacrificial layer 246 .
  • the chemical vapor deposition method is used to form the second capacitive isolation layer 243 and the second support layer 244 .
  • a second groove 247 is formed through the second capacitive isolation layer 243 and the second support layer 244, the second groove 247 exposes the top surface of the second sacrificial layer 246, and the width of the bottom surface of the second groove 247 is smaller than The width of the top surface of the second sacrificial layer 246 ; the second sacrificial layer 246 is removed to expose the first groove 245 . As such, the intersection of the first groove 245 and the second groove 247 has a corner.
  • the upper electrode 232 is formed on the surfaces of the first groove 245 and the second groove 247 , and the upper electrode 232 also covers the top surface of the second support layer 244 .
  • a dielectric layer 233 is formed on the surface of the upper electrode 232 , a lower electrode 231 is formed on the surface of the dielectric layer 233 , and the lower electrode 231 on the second support layer 244 is removed; the lower electrode 231 , the upper electrode 232 and the dielectric layer 233 constitute the capacitor 23 .
  • the lower electrode 231 fills the first groove 245 and the second groove 247 completely. In other embodiments, the lower electrode may not fill the first groove and the second groove.
  • the first grooves 245 and the second grooves 247 are formed respectively.
  • the step-by-step method is easier to reduce the line width of the capacitor and the difficulty of etching.
  • the superposition of the two grooves can increase the height of the capacitor, thereby ensuring a larger storage capacitor.
  • the step-by-step method can also make the junction of the first groove 245 and the second groove 247 have corners, and the corners can increase the relative area between the dielectric layer 233 and the upper electrode 232 and the lower electrode 231, so as to improve the storage capacity and capacitance stability.
  • the steps of forming the second contact structure 22 include: forming a second insulating layer 21 on the capacitor; forming a second through hole 215 in the second insulating layer 21 ; The hole reaming process is performed so that the area of the top of the second through hole 215 is larger than the area of the bottom of the second through hole 215 ; the second contact structure 22 filling the second through hole 215 is formed.
  • the second first dielectric layer 214 , the second first stabilizing layer 213 , the second second dielectric layer 212 and the second second stabilizing layer 211 are formed on the capacitor 23 ; the second first dielectric layer 214 , the second first The stabilization layer 213 , the second second dielectric layer 212 and the second second stabilization layer 211 constitute the second insulating layer 21 .
  • the chemical vapor deposition method is used to form the second insulating layer 21 .
  • a second two-contact structure 222 and a second one-contact structure 221 that are stacked and disposed are formed in the second through hole 215 .
  • the physical vapor deposition method is used to form the second two-contact structure 222 and the second one-contact structure 221 .
  • the chemical vapor deposition method can also be used to form the second two-contact structure and the second one-contact structure.
  • a step is further included: forming a second concave portion 223 on the side of the second contact structure 22 facing the first substrate 1 .
  • the second concave portion 223 can reduce the adverse effect of thermal stress on the bonding, thereby improving the bonding strength between the second substrate 2 and the first substrate 1 , and further improving the firmness of the semiconductor structure.
  • the second concave portion 223 is formed by chemical mechanical polishing.
  • the manufacturing process flow of the first substrate 1 and the second substrate 2 can be performed separately, so that the production cycle can be shortened.
  • the first contact structure 12 and the second contact structure 22 have bonding surfaces with larger areas to reduce the difficulty of alignment.
  • the first groove 245 and the second groove 247 are formed respectively, which is easier to reduce the line width of the capacitor and the difficulty of etching; the superposition of the two grooves can increase the height of the capacitor, thereby ensuring a larger storage capacitor.
  • Embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, so as to reduce the difficulty of a DRAM manufacturing process, improve production efficiency, shorten production cycle, improve DRAM performance, and help reduce the feature size of the semiconductor structure.

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Abstract

本公开实施例提供一种半导体结构及其制造方法，半导体结构包括：第一基底，第一基底包括堆叠设置的位线、晶体管和第一接触结构；与第一基底相键合的第二基底，第二基底包括堆叠设置的第二接触结构和电容，且第二接触结构与第一接触结构正对接触；其中，第一接触结构具有朝向第二基底的第一面以及与第一面相对的第二面，且第一面的面积大于第二面的面积；第二接触结构具有朝向第一基底的第三面以及与第三面相对的第四面，且第三面的面积大于第四面的面积。

Description

半导体结构及其制造方法
本公开要求在2021年03月22日提交中国专利局、申请号为202110304024.6、发明名称为“半导体结构及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及但不限于一种半导体结构及其制造方法。
背景技术
半导体结构中的动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)是一种广泛应用于计算机系统的半导体存储器。DRAM的主要作用原理是利用电容内存储电荷的多寡来代表一个二进制比特(bit)是1还是0。
然而，为提高半导体集成电路的集成度，DRAM的特征尺寸越来越小；从而使得DRAM的制造工艺难度越来越大，生产周期越来越长，其性能也有待进一步提升。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种半导体结构，包括：第一基底，所述第一基底包括堆叠设置的位线、晶体管和第一接触结构；与所述第一基底相键合的第二基底，所述第二基底包括堆叠设置的第二接触结构和电容，且所述第二接触结构与所述第一接触结构正对接触；其中，所述第一接触结构具有朝向所述第二基底的第一面以及与所述第一面相对的第二面，且所述第一面的面积大于所述第二面的面积；所述第二接触结构具有朝向所述第一基底的第三面以及与所述第三面相对的第四面，且所述第三面的面积大于所述第四面的面积。
在一些实施例中，所述第一面的面积大于所述第三面的面积。
在一些实施例中，所述第一面的面积是所述第三面的面积的5倍～20倍。
在一些实施例中，所述晶体管为竖直晶体管，所述竖直晶体管包括依次堆叠于所述位线上的源极、沟道区和漏极；所述漏极与所述第一接触结构相连；还包括：字线，所述字线与所述沟道区相连；所述位线沿第一方向延伸，所述字线沿第二方向延伸，且所述第一方向与所述第二方向不同。
在一些实施例中，所述竖直晶体管为多个，所述第一接触结构为多个，且多个所述第一接触结构与多个所述竖直晶体管一一对应相连；所述字线为多个，且一个所述字线连接多个所述竖直晶体管的沟道区。
在一些实施例中，所述电容包括下电极、上电极以及位于所述上电极和所述下电极之间的介质层，所述下电极与所述第二接触结构相连。
在一些实施例中，所述电容包括第一部分和第二部分，其中所述第一部分和所述第二部分的连接处具有拐点；所述第一部分包括部分所述上电极、部分所述下电极和部分所述介质层；所述第二部分包括部分上电极、部分下电极和部分介质层。
在一些实施例中，所述电容为多个，所述第二接触结构为多个，多个所述电容与多个所述第二接触结构一一对应相连；其中，多个所述电容的上电极相连，多个所述电容的介质层相连。
在一些实施例中，所述第二基底还包括：多个分立的电极垫，所述电极垫与所述电 容的上电极一一对应相连，且所述电极垫的剖面形貌为梯形，所述梯形的高度大于梯形平行边的边长。
在一些实施例中，所述第一接触结构包括层叠设置的第一一接触结构和第一二接触结构，且所述第一一接触结构位于远离所述第二基底的一侧，所述第一二接触结构位于靠近所述第二基底的一侧；所述第二接触结构包括层叠设置的第二一接触结构和第二二接触结构，且所述第二一接触结构位于靠近所述第一基底的一侧，所述第二二接触结构位于远离所述第一基底的一侧；其中，所述第一一接触结构和所述晶体管的接触面积大于所述第一二接触结构和所述第二一接触结构的接触面积，所述第二二接触结构和所述电容的接触面积小于所述第一二接触结构和所述第二一接触结构的接触面积。
在一些实施例中，所述第一一接触结构的硬度大于所述第一二接触结构的硬度；所述第二二接触结构的硬度大于所述第二一接触结构的硬度；所述第一二接触结构的熔点低于所述第一一接触结构的熔点；所述第二一接触结构的熔点低于所述第二二接触结构的熔点。
在一些实施例中，在垂直于所述第一基底表面的剖面上，所述第一一接触结构的剖面形貌为方形，所述第一二接触结构的剖面形貌为梯形；在垂直于所述第二基底表面的剖面上，所述第二二接触结构的剖面形貌为方形，所述第二一接触结构的剖面形貌为梯形。
在一些实施例中，所述第一一接触结构和所述晶体管的接触面积大于所述第一二接触结构和所述第二一接触结构的接触面积，所述第一接触结构和所述第二接触结构的电阻相同。
本公开实施例还提供一种半导体结构的制造方法，包括：提供第一基底，所述第一基底包括堆叠设置的位线、晶体管和第一接触结构；提供第二基底，所述第二基底包括堆叠设置的第二接触结构和电容；将所述第一基底与所述第二基底键合，且所述第一接触结构与所述第二接触结构正对接触；其中，所述第一接触结构具有朝向所述第二基底的第一面以及与所述第一面相对的第二面，且所述第一面的面积大于所述第二面的面积；所述第二接触结构具有朝向所述第一基底的第三面以及与所述第三面相对的第四面，且所述第三面的面积大于所述第四面的面积。
在一些实施例中，所述晶体管为竖直晶体管，所述竖直晶体管的形成方法包括：提供第一衬底，在所述第一衬底上形成层叠设置的源极隔离层、第一牺牲层和漏极隔离层，形成贯穿所述源极隔离层、所述第一牺牲层和所述漏极隔离层的若干第三通孔，所述第三通孔露出所述位线的顶面；在所述第三通孔内形成层叠设置的源极、沟道区和漏极，所述源极、所述沟道区和所述漏极构成所述竖直晶体管；形成所述竖直晶体管后，还包括：形成贯穿所述漏极隔离层和所述第一牺牲层的第一沟槽，所述第一沟槽沿第二方向延伸，所述第二方向与所述第一方向不同；形成所述第一沟槽后，去除所述第一牺牲层，以形成字线填充区；形成填充所述字线填充区的初始字线层，所述初始字线层还填充满所述第一沟槽；去除部分所述初始字线层，以形成相互分立的字线，并露出所述第一沟槽；形成填充所述第一沟槽的字线隔离层。
在一些实施例中，形成所述第一接触结构的步骤包括：在所述晶体管上形成第一绝缘层；在所述第一绝缘层内形成第一通孔；对所述第一通孔的顶部进行扩孔处理，以使所述第一通孔顶部的面积大于所述第一通孔底部的面积；形成填充所述第一通孔的所述第一接触结构；形成所述第二接触结构的步骤包括：在所述电容上形成第二绝缘层；在所述第二绝缘层内形成第二通孔；对所述第二通孔的顶部进行扩孔处理，以使所述第二通孔顶部的面积大于所述第二通孔底部的面积；形成填充所述第二通孔的所述第二接触结构。
在一些实施例中，所述第一通孔的形成步骤，包括：在所述漏极上形成层叠设置的 第一一稳定层、第一一介质层、第一二稳定层、第一二介质层和第一三稳定层；所述第一一稳定层、所述第一一介质层、所述第一二稳定层、所述第一二介质层和所述第一三稳定层构成所述第一绝缘层；形成贯穿所述第一一稳定层、所述第一一介质层、所述第一二稳定层、所述第一二介质层和所述第一三稳定层的第一通孔；去除部分所述第一三稳定层和所述第一二介质层，以使所述第一通孔顶部的面积大于所述第一通孔底部的面积；所述第二通孔的形成步骤，包括：在所述电容上形成层叠设置的第二一介质层、第二一稳定层、第二二介质层和第二二稳定层；所述第二一稳定层、所述第二一介质层、所述第二二稳定层和所述第二二介质层构成所述第二绝缘层；形成贯穿所述第二一稳定层、所述第二一介质层、所述第二二稳定层和所述第二二介质层的第二通孔；去除部分所述第二二介质层和所述第二二稳定层，以使所述第二通孔顶部的面积大于所述第二通孔底部的面积。
在一些实施例中，形成所述电容的步骤包括：提供第二衬底，在所述第二衬底上形成层叠设置的第三支撑层、第一电容隔离层和第一支撑层；形成贯穿所述第三支撑层、第一电容隔离层和所述第一支撑层的第一凹槽，且所述第一凹槽的底面宽度小于所述第一凹槽的开口宽度；形成填充所述第一凹槽的第二牺牲层；在所述第一支撑层和所述第二牺牲层上形成第二电容隔离层和第二支撑层；形成贯穿所述第二电容隔离层和所述第二支撑层的第二凹槽，所述第二凹槽露出所述第二牺牲层的顶面，且所述第二凹槽的底部宽度小于所述填充层的顶面宽度；去除所述第二牺牲层，以露出所述第一凹槽；在所述第一凹槽和所述第二凹槽的表面形成上电极，所述上电极还覆盖所述第二支撑层的顶面；在所述上电极的表面形成介质层，在所述介质层的表面形成下电极，去除位于所述第二支撑层上的所述下电极；所述下电极、所述上电极和所述介质层构成所述电容。
在一些实施例中，在形成所述第一电容隔离层之前还包括形成电极垫，形成所述电极垫的步骤包括：在所述第二衬底上形成层叠设置的电极垫隔离层和第四支撑层，形成贯穿所述电极垫隔离层和所述第四支撑层的第三凹槽，且部分第三凹槽还位于所述第二衬底内；形成填充所述第三凹槽的电极垫；
所述上电极还与所述电极垫接触。
在一些实施例中，所述键合之前还包括步骤：在所述第一接触结构朝向所述第二基底的一侧形成第一凹陷部；在所述第二接触结构朝向所述第一基底的一侧形成第二凹陷部；所述键合的温度为400℃～500℃，所述键合的压力为20kN～60kN。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本申请的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1为本公开一实施例提供的半导体结构的示意图。
图2为本公开一实施例提供的制造方法中在第一衬底内形成交替设置的隔离结构和位线的步骤对应的半导体结构的示意图。
图3为本公开一实施例提供的制造方法中在第一衬底上形成晶体管的步骤对应的半导体结构的示意图。
图4为图3在第一方向上的剖面示意图。
图5为本公开一实施例提供的制造方法中形成第一沟槽的步骤对应的半导体结构的示意图。
图6为图5在第一方向上的剖面示意图。
图7为本公开一实施例提供的制造方法中形成填充字线填充区的初始字线层的步骤对应的半导体结构的示意图。
图8为本公开一实施例提供的制造方法中去除部分初始字线层形成相互分立的字线的步骤对应的半导体结构的示意图。
图9为图8在第一方向上的剖面示意图。
图10为本公开一实施例提供的制造方法中形成填充第一沟槽的字线隔离层的步骤对应的半导体结构的示意图。
图11为本公开一实施例提供的制造方法中在晶体管上形成第一绝缘层、第一通孔的步骤对应的半导体结构的示意图。
图12为本公开一实施例提供的制造方法中形成填充第一通孔的第一接触结构的步骤对应的半导体结构的示意图。
图13为本公开一实施例提供的制造方法中在第一接触结构上形成第一凹陷部的步骤对应的半导体结构的示意图。
图14为本公开一实施例提供的制造方法中形成电极垫的步骤对应的半导体结构的示意图。
图15为本公开一实施例提供的制造方法中在第二衬底上形成第三支撑层、第一电容隔离层和第一支撑层的步骤对应的半导体结构的示意图。
图16为本公开一实施例提供的制造方法中形成填充第一凹槽的第二牺牲层的步骤对应的半导体结构的示意图。
图17为本公开一实施例提供的制造方法中形成贯穿第二电容隔离层和第二支撑层的第二凹槽的步骤对应的半导体结构的示意图。
图18为本公开一实施例提供的制造方法中在第一凹槽和第二凹槽形成电容的步骤对应的半导体结构的示意图。
图19为本公开一实施例提供的制造方法中在电容上形成第二绝缘层、第二通孔的步骤对应的半导体结构的示意图。
图20为本公开一实施例提供的制造方法中在第二通孔内形成第二二接触结构和第二一接触结构的步骤对应的半导体结构的示意图。
图21为本公开一实施例提供的制造方法中在第二接触结构上形成第二凹陷部的步骤对应的半导体结构的示意图。
具体实施方式
由背景技术可知，DRAM的制造工艺难度越来越大，生产周期越来越长，其性能也有待进一步提升。经分析发现，主要原因在于：现目前通常在一个基底上依次形成DRAM的晶体管和电容等结构，然而随着DRAM尺寸的不断缩小，工艺难度不断增大，生产时间不断增加。
本公开实施例提供一种半导体结构，半导体结构包括：第一基底，以及与第一基底相键合的第二基底，制造工艺的流程可以同时在第一基底和第二基底上进行，如此可以缩短产品生产周期。
此外，第一接触结构具有朝向第二基底的第一面以及与第一面相对的第二面，且第一面的面积大于第二面的面积；第二接触结构具有朝向第一基底的第三面以及与第三面相对的第四面，且第三面的面积大于第四面的面积。如此，可以使得第一接触结构与第二接触结构具有较大的接触面积，以降低接触电阻，还可以降低对准的难度，并且能避 免对准误差对半导体结构造成的不良影响。因此，本公开实施例能够提高生产效率，降低生产难度，提高半导体结构的性能。
其中，晶体管为竖直晶体管。相比于平面晶体管，竖直晶体管在竖直方向上的空间利用率更高，在水平方向上的所占据的面积更小，如此，有利于缩小半导体结构的特征尺寸。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
本公开一实施例提供一种半导体结构，图1为半导体结构的示意图。参考图1，半导体结构包括：第一基底1，第一基底1包括堆叠设置的位线103、晶体管11和第一接触结构12；与第一基底1相键合的第二基底2，第二基底2包括堆叠设置的第二接触结构22和电容23，且第二接触结构22与第一接触结构12正对接触；其中，第一接触结构12具有朝向第二基底2的第一面以及与第一面相对的第二面，且第一面的面积大于第二面的面积；第二接触结构22具有朝向第一基底1的第三面以及与第三面相对的第四面，且第三面的面积大于第四面的面积。
以下将结合附图进行具体分析。
第一基底1还包括第一衬底101。本实施例中，第一衬底101的材料为半导体，比如可以为硅或锗。在其他实施例中，第一衬底的材料也可以为绝缘材料，比如可以为氧化硅或氮化硅。
位线103位于第一衬底101内，且第一衬底101露出位线103的顶面。位线103沿第一方向延伸。位线103的材料可以为钨、钽、金或银等低电阻金属。
隔离结构105用于隔离相邻位线103。隔离结构105位于第一衬底101内，且第一衬底101露出隔离结构105的顶面。本实施例中，隔离结构105与位线103相互分立。在一示例中，隔离结构包括导电结构，例如导电的金属线(如钨，钌等)或导电的半导体线(如多晶硅等)，金属线或半导体线与位线103平行，且金属线或半导体线可以配置恒定的电位，例如，金属线或半导体线配置为接地，通过接地的金属线或半导体线隔离相邻的位线103，可以减弱相邻的位线103之间的互相干扰，提高器件性能。
本实施例中，晶体管11为竖直晶体管。相比于平面晶体管，竖直晶体管在竖直方向上的空间利用率更高，在水平方向上的所占据的面积更小，如此，有利于缩小半导体结构的特征尺寸。在其他实施例中，晶体管11也可以为平面晶体管。
本实施例中，竖直晶体管为多个，且竖直晶体管为阵列排布。
竖直晶体管包括依次堆叠于位线103上的源极111、沟道区110和漏极112。本实施例中，源极111、沟道区110和漏极112的材料均为硅，且源极111和漏极112中具有较多的掺杂离子，掺杂离子可以为硼或磷。在其他实施例中，源极、沟道区和漏极的材料也可以为锗。
相邻源极111之间还具有源极隔离层106，相邻漏极112之间还具有漏极隔离层108。
源极隔离层106的材料为绝缘材料，比如可以为氮化硅、氧化硅、碳氮化硅、氮氧化硅等。漏极隔离层108的材料为绝缘材料，比如可以为氮化硅、氧化硅、碳氮化硅、氮氧化硅等。
本实施例中，第一基底1还包括：字线109，字线109与沟道区110相连。字线109为多个，且一个字线109连接多个竖直晶体管的沟道区110。
字线109沿第二方向延伸，且第一方向与第二方向不同。本实施例中，第一方向与第二方向相垂直。在其他实施例中，第一方向与第二方向的夹角可以大于或等于75°， 且小于90°。
字线109的材料可以为钨、钽、金或银等低电阻金属。第一接触结构12为多个，且多个第一接触结构12与多个竖直晶体管一一对应相连；竖直晶体管的漏极112与第一接触结构12相连。第一接触结构12用于与第二接触结构22相连，以使第一基底1与第二基底2相键合。第二接触结构22也为多个，且多个第二接触结构22与多个第一接触结构12一一对应相连。
以下将对第一接触结构12和第二接触结构22进行具体说明。第一接触结构12具有朝向第二基底2的第一面以及与第一面相对的第二面，且第一面的面积大于第二面的面积；第二接触结构22具有朝向第一基底1的第三面以及与第三面相对的第四面，且第三面的面积大于第四面的面积。即第一面和第三面为键合面，而第二面和第四面为非键合面。由于键合面相对于非键合面具有更大的面积，因此，键合面具有较小的接触电阻，半导体结构的运行速率较快。其中，较大面积的键合面能够降低第一基底1与第二基底2对准难度，还能够避免对准误差对半导体结构造成的不良影响。
其中，第一面的面积大于第三面的面积。如此，可以防止出现对准误差时，一个电容23同时与两个晶体管11发生电连接的问题。
其中，第一面的面积是第三面的面积的5倍～20倍。在一个例子中，第一面的长度和宽度为40nm，其面积为1600nm 2，第三面的长度和宽度为10nm，其面积为100nm 2。当第一面和第三面的面积相差较大时，既能降低对准的难度，也可以避免发生错误的电连接。第一接触结构12可以包括在漏极112上外延生长的半导体导电层，如外延硅或外延锗等，通过外延生长的半导体导电层与漏极具有较低的接触电阻，同时，通过设置第一接触结构12较大的接触面积，可以进一步减低第一接触结构12的电阻；第二接触结构22包括与电容23电连接的金属层，由于金属层的电阻小于半导体导电层的电阻，因此可以设置较小的第二接触结构22的第三面的面积，使得第一接触结构12的电阻与第二接触结构22的电阻相匹配，例如二者的电阻相同，以提高器件性能。
本实施例中，第一接触结构12和第二接触结构22为双层结构。第一接触结构12包括层叠设置的第一一接触结构121和第一二接触结构122，且第一一接触结构121位远离第二基底2的一侧，第一二接触结构122位于靠近第二基底2的一侧。
第二接触结构22包括层叠设置的第二一接触结构221和第二二接触结构222，且第二一接触结构221位于靠近第一基底1的一侧，第二二接触结构222位于远离第一基底1的一侧。
即第一一接触结构121与晶体管11接触，第一二接触结构122与第二一接触结构221接触，第二二接触结构222与电容23接触。
其中，第一一接触结构121和晶体管11的接触面积大于第一二接触结构122和第二一接触结构221的接触面积，第二二接触结构222和电容23的接触面积小于第一二接触结构122和第二一接触结构221的接触面积。如此设置，不仅能降低第一接触结构12的电阻以及和晶体管11之间的导通电阻，同时能够降低对准难度，避免对准误差对半导体结构产生的不良影响。例如，第一一接触结构121可以为在漏极112上外延生长的半导体导电层，如外延硅或外延锗等，通过外延生长的半导体导电层与漏极具有较低的接触电阻，第一二接触结构122和第二接触结构22可以为金属钨等金属导体。第一接触结构12的电阻与第二接触结构22的电阻可以设置相匹配，例如二者的电阻相同，以提高器件性能。
在垂直于第一基底1表面的剖面上，第一一接触结构121的剖面形貌为方形，第一二接触结构122的剖面形貌为梯形；垂直于第二基底2表面的剖面上，第二二接触结构222的剖面形貌为方形，第二一接触结构221的剖面形貌为梯形。在其他实施例中，第一一接触结构的剖面形貌可以为梯形，第一二接触结构的剖面形貌可以为方形；第二二接触 结构的剖面形貌可以为梯形，第二一接触结构的剖面形貌可以为方形。
第一一接触结构121的硬度大于第一二接触结构122的硬度；第一二接触结构122的熔点低于第一一接触结构121的熔点。第二二接触结构222的硬度大于第二一接触结构221的硬度；第二一接触结构221的熔点低于第二二接触结构222的熔点。
当第一一接触结构121和第二二接触结构222具有较大的硬度时，能够提高半导体结构的强度。当第一二接触结构122和第二一接触结构221具有较低的熔点时，在较低的键合温度下，第一二接触结构122和第二一接触结构221之间能够结合地较为牢固。其中，还可以避免过高的键合温度对半导体结构产生不良影响。
第一二接触结构122和第二一接触结构221的材料可以为铜、金或银。第一一接触结构121和第二二接触结构222的材料可以为钨或钼。
还包括：用于隔离相邻第一接触结构12的第一绝缘层13，第一绝缘层13为多层结构，包括层叠设置的第一一稳定层131、第一一介质层132、第一二稳定层133、第一二介质层134和第一三稳定层135。
第一一稳定层131、第一二稳定层133、第一三稳定层135用于支撑第一接触结构12，使得第一接触结构12具有较大的牢固性，以避免发生坍塌或倾斜等问题。
第一一稳定层131、第一二稳定层133、第一三稳定层135的材料具有较大的强度，比如可以为氮化硅。
第一一介质层132和第一二介质层134用于隔离相邻第一接触结构12，并降低相邻第一接触结构12之间的寄生电容，因此，第一一介质层132和第一二介质层134的材料具有较小的介电常数，比如可以为氧化硅。
还包括：用于隔离相邻第二接触结构22的第二绝缘层21，第二绝缘层21包括层叠设置的第二二稳定层211、第二二介质层212、第二一稳定层213、第二一介质层214。
第二二介质层212和第二一介质层214能够降低相邻第二接触结构22之间的寄生电容，因此其材料具有较小的介电常数，比如可以为氧化硅。
第二二稳定层211和第二一稳定层213能够支撑第二接触结构22，因此其材料具有较大的强度，比如可以为氮化硅。
电容23与第二接触结构22相连，其中，电容23为多个，多个电容23与多个第二接触结构22一一对应相连。以下将对电容23进行具体说明。
电容23包括下电极231、上电极232以及位于上电极232和下电极231之间的介质层233，下电极231与第二接触结构22相连。本实施例中，多个电容23的上电极232相连，多个电容23的介质层233相连。在其他实施例中，多个电容的上电极也可以相互分立，多个电容的介质层也可以相互分立。
上电极232的材料为导电材料，比如可以为钛或氮化钛。下电极231的材料为导电材料，比如可以为钛或氮化钛。介质层233的材料具有较大的介电常数，比如可以为氧化锆、氧化铝、氧化铪等。
电容23包括第一部分和第二部分，其中第一部分和第二部分的连接处具有拐点；第一部分包括部分上电极232、部分下电极231和部分介质层233；第二部分包括部分上电极232、部分下电极231和部分介质层233。其中，当第一部分与第二部分的连接处具有拐角时，可以增大介质层233与上电极232和下电极231的相对面积，以提高存储容量。同时，具有拐点的电容23的稳定性更好。
还包括：位于相邻电容23之间层叠设置的第二支撑层244、第二电容隔离层243、第一支撑层242、第一电容隔离层241和第三支撑层248。
第三支撑层248、第二支撑层244和第一支撑层242用于支撑电容23，使得电容23具有较大的牢固性，以避免发生坍塌或倾斜等问题。
第三支撑层248、第二支撑层244和第一支撑层242的材料具有较大的强度，比如可 以为氮化硅。
第二电容隔离层243和第一电容隔离层241用于隔离相邻电容23，并降低相邻电容23之间的寄生电容，因此，第二电容隔离层243和第一电容隔离层241的材料具有较小的介电常数，比如可以为氧化硅。
第二基底2还包括：多个分立的电极垫202，电极垫202与电容23的上电极232一一对应相连，且电极垫202的剖面形貌为梯形，梯形的高度大于梯形平行边的边长，梯形的高度范围可以为100nm～1500nm，例如500nm，800nm，1200nm等。电容23与梯形的一个平行边相接触，梯形的平行边边长较小，即电极垫202在水平方向上所占据的空间位置较小，相邻电极垫202的间距较大，电极垫202嵌入到第二衬底201中的深度较深，可以进一步增强电容23在第二基底2中的稳定性。电极垫202的材料可以为钨或钼。
相邻电极垫202之间还具有层叠设置的电极垫隔离层203和第四支撑层204，电极垫隔离层203可以对电极垫202起到隔离作用，电极垫隔离层203的材料可以为氧化硅。第四支撑层204可以对电极垫202起到支撑的作用，第四支撑层204的材料可以为氮化硅。
综上所述，由于第一基底1与第二基底2为两个独立的结构，因此制造工艺的流程可以同时在第一基底1和第二基底2上进行，如此可以缩短产品生产周期。其中，第一接触结构12与第二接触结构22具有较大面积的键合面，以降低键合面的电阻，并且降低对准的难度，还能够避免对准误差对半导体结构造成的不良影响。因此，本公开实施例能够提高生产效率，降低生产难度，提高半导体结构的性能。
本公开另一实施例还提供一种半导体结构的制造方法，图2-图21为本实施例提供的半导体结构的制造方法中各步骤对应的示意图。有关半导体结构内部的材料和形状等说明，请参考第一实施例，在此不再赘述。
参考图1，提供第一基底1，基底包括堆叠设置的位线103、晶体管11和第一接触结构12；提供第二基底2，第二基底2包括堆叠设置的第二接触结构22和电容23；将第一基底1与第二基底2键合，且第一接触结构12与第二接触结构22正对接触。
键合是指在一定温度和压力条件下，键合界面处的原子在外界能量的作用下发生物理化学反应，在范德华力和库仑力等作用力下，第一基底1和第二基底2结合在一起。
本实施例中，键合的温度为400℃～500℃，键合的压力为20kN～60kN。
当键合温度在上述范围内时，可以加快第一接触结构12和第二接触结构22之间的原子扩散，从而增强二者的粘结力。
当键合压力在上述范围时，可以提高键合的牢固性。
其中，第一接触结构12具有朝向第二基底2的第一面以及与第一面相对的第二面，且第一面的面积大于第二面的面积；第二接触结构22具有朝向第一基底1的第三面以及与第三面相对的第四面，且第三面的面积大于第四面的面积。
即第一面和第三面为键合面，而第二面和第四面为非键合面。由于键合面相对于非键合面具有更大的面积，因此，键合面具有较小的接触电阻，半导体结构的运行速率较快。较大面积的键合面能够降低第一基底1与第二基底2对准难度，还能够避免对准误差对半导体结构造成的不良影响。键合面的面积较大，也可以提高键合的强度。
以下将对第一基底1的形成步骤进行具体说明。
参考图2，提供第一衬底101，在第一衬底101内形成交替设置的隔离结构105和位线103，隔离结构105和位线103均沿第一方向延伸，第一衬底101露出位线103和隔离结构105的顶面。
本实施例中，隔离结构105先于位线103形成。形成隔离结构105和位线103的步骤包括：在第一衬底101上形成氧化硅层和氮化硅层的叠层结构；在叠层结构上形成图形 化的光刻胶层；以图形化的光刻胶层为掩膜，刻蚀氧化硅层和氮化硅层的叠层结构以及第一衬底101，以形成位于第一衬底101内的隔离结构填充沟槽，隔离结构填充沟槽沿第一方向延伸；形成隔离结构填充沟槽后，去除光刻胶；采用化学气相沉积工艺在隔离结构填充沟槽中形成初始隔离结构，初始隔离结构还位于氧化硅和氮化硅的叠层结构上；去除位于氧化硅和氮化硅的叠层结构上的初始隔离层，去除部分初始隔离层后，去除氮化硅层；去除氮化硅层后，在氧化硅层上形成图形化的光刻胶层，以图形化的光刻胶层为掩膜刻蚀氧化硅层，以露出第一衬底101的上表面；采用离子注入的方法，在被露出的第一衬底101内形成位线103。
在其他实施例中，还可以先形成位线，后形成隔离结构。
在其他实施例中，隔离结构包括导电结构，例如导电的金属线(如钨，钌等)或导电的半导体线(如多晶硅等)，金属线或半导体线与位线103平行，且所述金属线或半导体线可以配置恒定的电位，例如，金属线或半导体线配置为接地，通过接地的金属线或半导体线隔离相邻的位线103，可以减弱相邻的位线103之间的互相干扰，提高器件性能。
参考图2-图3，在第一衬底101上形成晶体管11，晶体管11为竖直晶体管。参考图2，在第一衬底101上形成层叠设置的源极隔离层106、第一牺牲层107和漏极隔离层108。本实施例中，通过化学气相沉积法形成源极隔离层106、第一牺牲层107和漏极隔离层108。
形成贯穿源极隔离层106、第一牺牲层107和漏极隔离层108的若干第三通孔102，第三通孔102露出位线103的顶面。本实施例中，采用干法刻蚀的方法形成第三通孔102。
参考图3-图4，图4为图3在第一方向上的剖面图。在第三通孔102内形成层叠设置的源极111、沟道区110和漏极112，源极111、沟道区110和漏极112构成竖直晶体管。
通过选择性外延生长的方法在位线103上形成第一半导体柱，第一半导体柱的顶面与源极隔离层106的顶面齐平，并对第一半导体柱进行离子注入，以形成源极111。通过选择性外延生长的方法，在源极111上形成第二半导体柱，第二半导体柱的顶面与第一牺牲层107的顶面齐平，第二半导体柱作为沟道区110。通过选择性外延生长的方法，在沟道区110上形成第三半导体柱，对第三半导体柱进行离子注入，以形成漏极112。
本实施例中，第一半导体柱、第二半导体柱和第三半导体柱的材料为硅，在其他实施例中，第一半导体柱、第二半导体柱和第三半导体柱的材料也可以为锗。第一半导体柱和第三半导体柱的掺杂离子相同，比如可以均为磷，也可以均为硼。
参考图5-图6，图6为图5在第一方向上的剖面图。形成贯穿漏极隔离层108和第一牺牲层107(参考图4)的第一沟槽104，第一沟槽104沿第二方向延伸，第二方向与第一方向不同。本实施例中，第一方向与第二方向垂直。在其他实施例中，第一方向与第二方向的夹角可以大于或等于75°，且小于90°。
本实施例中，第一沟槽104还贯穿源极隔离层106。在其他实施例中，第一沟槽可以只贯穿漏极隔离层和第一牺牲层。
本实施例中，采用干法刻蚀的方法形成第一沟槽104。在干法刻蚀之前，还在漏极隔离层108和漏极112上形成氮化硅层。在干法刻蚀中，还去除部分氮化硅层。在干法刻蚀后，去除剩余的氮化硅层。氮化硅层能够提高刻蚀图形的精度。
形成第一沟槽104后，去除第一牺牲层107(参考图4)，以形成字线填充区109a。本实施例中，采用湿法刻蚀的方法去除第一牺牲层107。形成的字线填充区109a为原第一牺牲层107所占据的空间位置。
参考图7，形成填充字线填充区109a的初始字线层109b，初始字线层109b还填充满第一沟槽104(参考图6)。本实施例中，采用化学气相沉积的方法形成初始字线层109b， 在其他实施例中，也可以采用物理气相沉积的方法形成初始字线层。
参考图8-图9，图9为图8在第一方向上的剖面图。去除部分初始字线层109b，以形成相互分立的字线109，并露出第一沟槽104。即剩余的初始字线层109b作为字线109，且第一沟槽104将字线109分割开。本实施例中，采用干法刻蚀的方法去除部分初始字线层109b。
参考图10，形成填充第一沟槽104的字线隔离层113。字线隔离层113为绝缘材料，比如可以为氧化硅或氮化硅，用于隔离相邻字线109。
参考图11-图12，形成第一接触结构12的步骤包括：在晶体管11上形成第一绝缘层13；在第一绝缘层13内形成第一通孔136；对第一通孔136的顶部进行扩孔处理，以使第一通孔136顶部的面积大于第一通孔136底部的面积；形成填充第一通孔136的第一接触结构12。
本实施例中，第一绝缘层13为多层结构，第一通孔136的形成步骤包括：参考图11，在漏极112上形成层叠设置的第一一稳定层131、第一一介质层132、第一二稳定层133、第一二介质层134和第一三稳定层135；第一一稳定层131、第一一介质层132、第一二稳定层133、第一二介质层134和第一三稳定层135构成第一绝缘层13。
本实施例中，采用化学气相沉积的方法形成第一绝缘层13。
形成贯穿第一一稳定层131、第一一介质层132、第一二稳定层133、第一二介质层134和第一三稳定层135的第一通孔136；去除部分第一三稳定层135和第一二介质层134，以使第一通孔136顶部的面积大于第一通孔136底部的面积。本实施例中，采用干法刻蚀的方法形成第一通孔136，并采用干法刻蚀的方法对第一通孔136进行扩孔处理。
参考图12，在第一通孔136(参考图11)内形成层叠设置的第一二接触结构122和第一一接触结构121。本实施例中，分别采用外延生长和化学气相沉积法形成第一二接触结构122和第一一接触结构121。在其他实施例中，也可以采用物理气相沉积法形成第一二接触结构和第一一接触结构。
参考图13，在第一接触结构12朝向第二基底2(参考图1)的一侧形成第一凹陷部123。即在第一一接触结构12的键合面上形成第一凹陷部123。其中，在第一基底1和第二基底2的键合过程中，由于温度较高，从而存在较大的应力；为降低热应力对键合效果产生的不良影响，可以形成第一凹陷部123。本实施例中，采用化学机械研磨的方法形成第一凹陷部123。
以下将对第二基底2的形成步骤进行具体说明。
参考图14，形成电极垫202的步骤包括：在第二衬底201上形成层叠设置的电极垫隔离层203和第四支撑层204，形成贯穿电极垫隔离层203和第四支撑层204的第三凹槽，且部分第三凹槽还位于第二衬底201内。本实施例中，通过干法刻蚀的方法形成第三凹槽。
形成填充第三凹槽的电极垫202。本实施例中，采用物理气相沉积的方法形成电极垫202。在其他实施例中，也可以采用化学气相沉积的方法形成电极垫。
参考图15-图18，形成电容23的步骤包括：
参考图15，提供第二衬底201，在第二衬底上形成层叠设置的第三支撑层248、第一电容隔离层241和第一支撑层242。本实施例中，采用化学气相沉积法形成第三支撑层248、第一电容隔离层241和第一支撑层242。
形成贯穿第三支撑层248、第一电容隔离层241和第一支撑层242的第一凹槽245，且第一凹槽245的底面宽度小于第一凹槽245的开口宽度。本实施例中，采用干法刻蚀的方法形成第一凹槽245。
参考图16，形成填充第一凹槽245的第二牺牲层246。第二牺牲层246的材料为非晶 硅。
在第一支撑层242和第二牺牲层246上形成第二电容隔离层243和第二支撑层244。本实施例中，采用化学气相沉积的方法形成第二电容隔离层243和第二支撑层244。
参考图17，形成贯穿第二电容隔离层243和第二支撑层244的第二凹槽247，第二凹槽247露出第二牺牲层246的顶面，且第二凹槽247的底面宽度小于第二牺牲层246的顶面宽度；去除第二牺牲层246，以露出第一凹槽245。如此，第一凹槽245和第二凹槽247的交界处具有拐角。
参考图18，在第一凹槽245和第二凹槽247的表面形成上电极232，上电极232还覆盖第二支撑层244的顶面。在上电极232的表面形成介质层233，在介质层233的表面形成下电极231，去除位于第二支撑层244上的下电极231；下电极231、上电极232和介质层233构成电容23。
本实施例中，下电极231填充满第一凹槽245和第二凹槽247。在其他实施例中，下电极可以不填充满第一凹槽和第二凹槽。
本实施例中，分别形成第一凹槽245和第二凹槽247，相比于一次性形成凹槽，分步形成的方法更容易降低电容的线宽，也更易降低刻蚀的难度。两个凹槽相叠加，可以提高电容的高度，从而保证较大的存储电容。分步形成的方法还可以使得第一凹槽245和第二凹槽247的交界处具有拐角，拐角可以增大介质层233与上电极232和下电极231的相对面积，以提高存储容量以及电容的稳定性。
参考图19-图20，形成第二接触结构22的步骤包括：在电容上形成第二绝缘层21；在第二绝缘层21内形成第二通孔215；对第二通孔215的顶部进行扩孔处理，以使第二通孔215顶部的面积大于第二通孔215底部的面积；形成填充第二通孔215的第二接触结构22。
参考图19：在电容23上形成层叠设置的第二一介质层214、第二一稳定层213、第二二介质层212和第二二稳定层211；第二一介质层214、第二一稳定层213、第二二介质层212和第二二稳定层211构成第二绝缘层21。本实施例中，采用化学气相沉积的方法形成第二绝缘层21。
形成贯穿第二一介质层214、第二一稳定层213、第二二介质层212和第二二稳定层211的第二通孔215；去除部分第二二稳定层211和第二二介质层212，以使第二通孔215顶部的面积大于第二通孔215底部的面积。
参考图20，在第二通孔215内形成层叠设置的第二二接触结构222和第二一接触结构221。本实施例中，采用物理气相沉积的方法形成第二二接触结构222和第二一接触结构221。在其他实施例中，也可以采用化学气相沉积的方法形成第二二接触结构和第二一接触结构。
参考图21，键合之前还包括步骤：在第二接触结构22朝向第一基底1的一侧形成第二凹陷部223。第二凹陷部223能够降低热应力对键合产生的不良影响，从而提高第二基底2与第一基底1的键合强度，进而提高半导体结构的牢固性。本实施例中，通过化学机械研磨的方法形成第二凹陷部223。
综上所述，本实施例中，第一基底1和第二基底2的制造工艺流程可以分别进行，从而能够缩短生产周期。第一接触结构12与第二接触结构22具有较大面积的键合面，以降低对准的难度。其中，分别形成第一凹槽245和第二凹槽247，更容易降低电容的线宽，也更易降低刻蚀的难度；两个凹槽相叠加，可以提高电容的高度，从而保证较大的存储电容。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例提供一种半导体结构及其制造方法，以降低DRAM的制造工艺难度，提高生产效率，缩短生产周期，提高DRAM的性能，并且利于缩小半导体结构的特征尺寸。

Claims (19)

  1. 一种半导体结构，所述半导体结构包括：
    第一基底，所述第一基底包括堆叠设置的位线、晶体管和第一接触结构；
    与所述第一基底相键合的第二基底，所述第二基底包括堆叠设置的第二接触结构和电容，且所述第二接触结构与所述第一接触结构正对接触；
    其中，所述第一接触结构具有朝向所述第二基底的第一面以及与所述第一面相对的第二面，且所述第一面的面积大于所述第二面的面积；
    所述第二接触结构具有朝向所述第一基底的第三面以及与所述第三面相对的第四面，且所述第三面的面积大于所述第四面的面积。
  2. 根据权利要求1所述的半导体结构，其中，所述第一面的面积大于所述第三面的面积。
  3. 根据权利要求2所述的半导体结构，其中，所述第一面的面积是所述第三面的面积的5倍～20倍。
  4. 根据权利要求1所述的半导体结构，其中，所述晶体管为竖直晶体管，所述竖直晶体管包括依次堆叠于所述位线上的源极、沟道区和漏极；所述漏极与所述第一接触结构相连；还包括：字线，所述字线与所述沟道区相连；所述位线沿第一方向延伸，所述字线沿第二方向延伸，且所述第一方向与所述第二方向不同。
  5. 根据权利要求4所述的半导体结构，其中，所述竖直晶体管为多个，所述第一接触结构为多个，且多个所述第一接触结构与多个所述竖直晶体管一一对应相连；所述字线为多个，且一个所述字线连接多个所述竖直晶体管的所述沟道区。
  6. 根据权利要求1所述的半导体结构，其中，所述电容包括下电极、上电极以及位于所述上电极和所述下电极之间的介质层，所述下电极与所述第二接触结构相连。
  7. 根据权利要求6所述的半导体结构，其中，所述电容包括第一部分和第二部分，其中所述第一部分和所述第二部分的连接处具有拐点；所述第一部分包括部分所述上电极、部分所述下电极和部分所述介质层；所述第二部分包括部分所述上电极、部分所述下电极和部分所述介质层。
  8. 根据权利要求6所述的半导体结构，其中，所述电容为多个，所述第二接触结构为多个，多个所述电容与多个所述第二接触结构一一对应相连；其中，多个所述电容的所述上电极相连，多个所述电容的所述介质层相连。
  9. 根据权利要求6所述的半导体结构，其中，所述第二基底还包括：多个分立的电极垫，所述电极垫与所述电容的所述上电极一一对应相连，且所述电极垫的剖面形貌为梯形，所述梯形的高度大于所述梯形平行边的边长。
  10. 根据权利要求1所述的半导体结构，其中，所述第一接触结构包括层叠设置的第一一接触结构和第一二接触结构，且所述第一一接触结构位于远离所述第二基底的一侧，所述第一二接触结构位于靠近所述第二基底的一侧；
    所述第二接触结构包括层叠设置的第二一接触结构和第二二接触结构，且所述第二一接触结构位于靠近所述第一基底的一侧，所述第二二接触结构位于远离所述第一基底的一侧；
    其中，所述第一一接触结构和所述晶体管的接触面积大于所述第一二接触结构和所述第二一接触结构的接触面积，所述第二二接触结构和所述电容的接触面积小于所述第一二接触结构和所述第二一接触结构的接触面积。
  11. 根据权利要求10所述的半导体结构，其中，所述第一一接触结构的硬度大于所 述第一二接触结构的硬度；所述第二二接触结构的硬度大于所述第二一接触结构的硬度；所述第一二接触结构的熔点低于所述第一一接触结构的熔点；所述第二一接触结构的熔点低于所述第二二接触结构的熔点。
  12. 根据权利要求10所述的半导体结构，其中，所述第一一接触结构和所述晶体管的接触面积大于所述第一二接触结构和所述第二一接触结构的接触面积，所述第一接触结构和所述第二接触结构的电阻相同。
  13. 一种半导体结构的制造方法，所述制造方法包括：
    提供第一基底，所述第一基底包括堆叠设置的位线、晶体管和第一接触结构；
    提供第二基底，所述第二基底包括堆叠设置的第二接触结构和电容；
    将所述第一基底与所述第二基底键合，且所述第一接触结构与所述第二接触结构正对接触；
    其中，所述第一接触结构具有朝向所述第二基底的第一面以及与所述第一面相对的第二面，且所述第一面的面积大于所述第二面的面积；
    所述第二接触结构具有朝向所述第一基底的第三面以及与所述第三面相对的第四面，且所述第三面的面积大于所述第四面的面积。
  14. 根据权利要求13所述的半导体结构的制造方法，其中，所述晶体管为竖直晶体管，所述竖直晶体管的形成方法包括：
    提供第一衬底，在所述第一衬底上形成层叠设置的源极隔离层、第一牺牲层和漏极隔离层，形成贯穿所述源极隔离层、所述第一牺牲层和所述漏极隔离层的若干第三通孔，所述第三通孔露出所述位线的顶面；
    在所述第三通孔内形成层叠设置的源极、沟道区和漏极，所述源极、所述沟道区和所述漏极构成所述竖直晶体管；
    形成所述竖直晶体管后，还包括：形成贯穿所述漏极隔离层和所述第一牺牲层的第一沟槽，所述第一沟槽沿第二方向延伸，所述位线沿第一方向延伸，所述第二方向与所述第一方向不同；形成所述第一沟槽后，去除所述第一牺牲层，以形成字线填充区；形成填充所述字线填充区的初始字线层，所述初始字线层还填充满所述第一沟槽；去除部分所述初始字线层，以形成相互分立的字线，并露出所述第一沟槽；形成填充所述第一沟槽的字线隔离层。
  15. 根据权利要求13所述的半导体结构的制造方法，其中，形成所述第一接触结构的步骤包括：在所述晶体管上形成第一绝缘层；在所述第一绝缘层内形成第一通孔；对所述第一通孔的顶部进行扩孔处理，以使所述第一通孔顶部的面积大于所述第一通孔底部的面积；形成填充所述第一通孔的所述第一接触结构；
    形成所述第二接触结构的步骤包括：在所述电容上形成第二绝缘层；在所述第二绝缘层内形成第二通孔；对所述第二通孔的顶部进行扩孔处理，以使所述第二通孔顶部的面积大于所述第二通孔底部的面积；形成填充所述第二通孔的所述第二接触结构。
  16. 根据权利要求15所述的半导体结构的制造方法，其中，所述第一通孔的形成步骤，包括：在所述漏极上形成层叠设置的第一一稳定层、第一一介质层、第一二稳定层、第一二介质层和第一三稳定层；所述第一一稳定层、所述第一一介质层、所述第一二稳定层、所述第一二介质层和所述第一三稳定层构成所述第一绝缘层；
    形成贯穿所述第一一稳定层、所述第一一介质层、所述第一二稳定层、所述第一二介质层和所述第一三稳定层的所述第一通孔；去除部分所述第一三稳定层和所述第一二介质层，以使所述第一通孔顶部的面积大于所述第一通孔底部的面积；
    所述第二通孔的形成步骤，包括：在所述电容上形成层叠设置的第二一介质层、第二一稳定层、第二二介质层和第二二稳定层；所述第二一稳定层、所述第二一介质层、所述第二二稳定层和所述第二二介质层构成所述第二绝缘层；
    形成贯穿所述第二一稳定层、所述第二一介质层、所述第二二稳定层和所述第二二介质层的所述第二通孔；去除部分所述第二二介质层和所述第二二稳定层，以使所述第二通孔顶部的面积大于所述第二通孔底部的面积。
  17. 根据权利要求13所述的半导体结构的制造方法，其中，形成所述电容的步骤包括：提供第二衬底，在所述第二衬底上形成层叠设置的第三支撑层、第一电容隔离层和第一支撑层；
    形成贯穿所述第三支撑层、所述第一电容隔离层和所述第一支撑层的第一凹槽，且所述第一凹槽的底面宽度小于所述第一凹槽的开口宽度；
    形成填充所述第一凹槽的第二牺牲层；
    在所述第一支撑层和所述第二牺牲层上形成第二电容隔离层和第二支撑层；形成贯穿所述第二电容隔离层和所述第二支撑层的第二凹槽，所述第二凹槽露出所述第二牺牲层的顶面，且所述第二凹槽的底部宽度小于所述填充层的顶面宽度；
    去除所述第二牺牲层，以露出所述第一凹槽；
    在所述第一凹槽和所述第二凹槽的表面形成上电极，所述上电极还覆盖所述第二支撑层的顶面；在所述上电极的表面形成介质层，在所述介质层的表面形成下电极，去除位于所述第二支撑层上的所述下电极；所述下电极、所述上电极和所述介质层构成所述电容。
  18. 根据权利要求17所述的半导体结构的制造方法，其中，在形成所述第一电容隔离层之前，还包括：形成电极垫，形成所述电极垫的步骤包括：在所述第二衬底上形成层叠设置的电极垫隔离层和第四支撑层，形成贯穿所述电极垫隔离层和所述第四支撑层的第三凹槽，且部分所述第三凹槽还位于所述第二衬底内；形成填充所述第三凹槽的所述电极垫；
    所述上电极还与所述电极垫接触。
  19. 根据权利要求13所述的半导体结构的制造方法，其中，所述键合之前还包括步骤：在所述第一接触结构朝向所述第二基底的一侧形成第一凹陷部；在所述第二接触结构朝向所述第一基底的一侧形成第二凹陷部；
    所述键合的温度为400℃～500℃，所述键合的压力为20kN～60kN。
PCT/CN2022/070291 2021-03-22 2022-01-05 半导体结构及其制造方法 WO2022199207A1 (zh)

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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113053900B (zh) * 2021-03-22 2023-01-20 长鑫存储技术有限公司 半导体结构及其制造方法
CN115565983A (zh) * 2021-07-01 2023-01-03 长鑫存储技术有限公司 一种半导体结构及其形成方法
CN115643747A (zh) * 2021-07-19 2023-01-24 长鑫存储技术有限公司 半导体结构的制作方法及半导体结构
EP4276883A4 (en) * 2021-09-15 2024-09-18 Changxin Memory Tech Inc MEMORY DEVICE AND ASSOCIATED TRAINING METHOD
CN116489987A (zh) * 2022-01-11 2023-07-25 长鑫存储技术有限公司 存储器及其制作方法
CN115884594B (zh) * 2023-02-09 2023-07-21 长鑫存储技术有限公司 半导体结构及半导体结构的制备方法
CN116648058B (zh) * 2023-04-24 2024-04-09 北京超弦存储器研究院 一种半导体器件及其制造方法、电子设备

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110192269A (zh) * 2019-04-15 2019-08-30 长江存储科技有限责任公司 三维nand存储器件与多个功能芯片的集成
CN110249427A (zh) * 2019-04-30 2019-09-17 长江存储科技有限责任公司 具有嵌入式动态随机存取存储器的三维存储器件
CN110546762A (zh) * 2019-04-30 2019-12-06 长江存储科技有限责任公司 键合的统一半导体芯片及其制造和操作方法
US20210074709A1 (en) * 2019-09-11 2021-03-11 Yangtze Memory Technologies Co., Ltd. Bonded semiconductor devices having processor and static random-access memory and methods for forming the same
CN113053900A (zh) * 2021-03-22 2021-06-29 长鑫存储技术有限公司 半导体结构及其制造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7052941B2 (en) * 2003-06-24 2006-05-30 Sang-Yun Lee Method for making a three-dimensional integrated circuit structure
CN101673744B (zh) * 2008-09-12 2011-05-18 南亚科技股份有限公司 晶体管结构、动态随机存取存储器结构及其制造方法
CN102543877B (zh) * 2010-12-29 2014-03-12 中国科学院微电子研究所 制备三维半导体存储器件的方法
CN109155301A (zh) * 2018-08-13 2019-01-04 长江存储科技有限责任公司 具有帽盖层的键合触点及其形成方法
CN111223843A (zh) * 2018-11-26 2020-06-02 长鑫存储技术有限公司 电容器阵列结构及其制造方法和包含它的半导体存储器
JP7278394B2 (ja) * 2019-04-30 2023-05-19 長江存儲科技有限責任公司 フラッシュメモリーコントローラーを有する結合されたメモリーデバイス、ならびに、その製作方法および動作方法
EP3925003B1 (en) * 2020-02-20 2024-09-04 Yangtze Memory Technologies Co., Ltd. Dram memory device with xtacking architecture

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110192269A (zh) * 2019-04-15 2019-08-30 长江存储科技有限责任公司 三维nand存储器件与多个功能芯片的集成
CN110249427A (zh) * 2019-04-30 2019-09-17 长江存储科技有限责任公司 具有嵌入式动态随机存取存储器的三维存储器件
CN110546762A (zh) * 2019-04-30 2019-12-06 长江存储科技有限责任公司 键合的统一半导体芯片及其制造和操作方法
US20210074709A1 (en) * 2019-09-11 2021-03-11 Yangtze Memory Technologies Co., Ltd. Bonded semiconductor devices having processor and static random-access memory and methods for forming the same
CN113053900A (zh) * 2021-03-22 2021-06-29 长鑫存储技术有限公司 半导体结构及其制造方法

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