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WO2016076300A1 - Élément de conversion photoélectrique - Google Patents

Élément de conversion photoélectrique Download PDF

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Publication number
WO2016076300A1
WO2016076300A1 PCT/JP2015/081562 JP2015081562W WO2016076300A1 WO 2016076300 A1 WO2016076300 A1 WO 2016076300A1 JP 2015081562 W JP2015081562 W JP 2015081562W WO 2016076300 A1 WO2016076300 A1 WO 2016076300A1
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WO
WIPO (PCT)
Prior art keywords
amorphous semiconductor
semiconductor layer
type amorphous
region
photoelectric conversion
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PCT/JP2015/081562
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English (en)
Japanese (ja)
Inventor
督章 國吉
神川　剛
真臣 原田
敏彦 酒井
柳民 鄒
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シャープ株式会社
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Publication of WO2016076300A1 publication Critical patent/WO2016076300A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present disclosure relates to a photoelectric conversion element.
  • JP-T-2010-503222 discloses an example of a back junction solar cell in which a passivation layer and a back contact layer are formed on the back surface of a semiconductor substrate.
  • a passivation layer is formed on the entire back surface of the semiconductor substrate, an opening is formed in the passivation layer by etching using hydrogen plasma.
  • the back contact layer is formed in the opening of the passivation layer.
  • JP-T-2010-503222 an opening penetrating in the thickness direction is formed in the passivation layer by etching the passivation layer until it reaches the back surface of the semiconductor substrate. As a result, the interface portion between the semiconductor substrate and the passivation layer is damaged, so that the passivation property is deteriorated and the contact resistance may be increased.
  • the present disclosure aims to provide a photoelectric conversion element that can ensure good passivation and reduce contact resistance.
  • the photoelectric conversion element according to the present disclosure is formed on a semiconductor substrate, one surface of the semiconductor substrate, and has at least one concave portion on the surface, and is formed on a passivation layer made of an intrinsic amorphous semiconductor, and on the passivation layer.
  • FIG. 1 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the first embodiment.
  • FIG. 2A is a diagram showing a first step in the method of manufacturing the photoelectric conversion element shown in FIG.
  • FIG. 2B is a diagram showing a second step in the method of manufacturing the photoelectric conversion element shown in FIG.
  • FIG. 2C is a diagram showing a third step in the method of manufacturing the photoelectric conversion element shown in FIG.
  • FIG. 2D is a diagram showing a fourth step in the method of manufacturing the photoelectric conversion element shown in FIG.
  • FIG. 2E is a diagram showing a fifth step in the method for manufacturing the photoelectric conversion element shown in FIG. 1.
  • 2F is a diagram showing a sixth step in the method of manufacturing the photoelectric conversion element shown in FIG. FIG.
  • FIG. 2G is a diagram showing a seventh step in the method of manufacturing the photoelectric conversion element shown in FIG.
  • FIG. 2H is a diagram showing an eighth step in the method of manufacturing the photoelectric conversion element shown in FIG.
  • FIG. 2I is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element completed through the first to eighth steps.
  • FIG. 3 is a diagram showing the shape of the recess formed in the fourth step.
  • FIG. 4A is a diagram showing the shape of the n-type amorphous semiconductor layer formed in the fifth step.
  • FIG. 4B is a diagram showing another shape of the n-type amorphous semiconductor layer formed in the fifth step.
  • FIG. 5 is a diagram showing the lifetime of the photoelectric conversion element for each thickness of the passivation layer.
  • FIG. 5 is a diagram showing the lifetime of the photoelectric conversion element for each thickness of the passivation layer.
  • FIG. 6A is a diagram showing contact resistance for each thickness of a portion where an n-type amorphous semiconductor layer is disposed in the passivation layer.
  • FIG. 6B is a diagram showing contact resistance for each thickness of a portion where the p-type amorphous semiconductor layer is disposed in the passivation layer.
  • FIG. 7 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the second embodiment.
  • FIG. 8A is a diagram showing one step in the method of manufacturing the photoelectric conversion element shown in FIG.
  • FIG. 8B is a diagram illustrating a step in the method for manufacturing the photoelectric conversion element illustrated in FIG. 7.
  • FIG. 8C is a diagram showing one step in the method for manufacturing the photoelectric conversion element shown in FIG. 7.
  • FIG. 8A is a diagram showing contact resistance for each thickness of a portion where an n-type amorphous semiconductor layer is disposed in the passivation layer.
  • FIG. 6B is a diagram showing contact resistance for
  • FIG. 8D is a cross-sectional view showing a schematic configuration of the photoelectric conversion element completed through the steps shown in FIGS. 8A to 8C.
  • FIG. 9 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the third embodiment.
  • FIG. 10 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the fourth embodiment.
  • FIG. 11A is a diagram illustrating a step in the method of manufacturing the photoelectric conversion element illustrated in FIG. 10.
  • FIG. 11B is a diagram illustrating a step in the method for manufacturing the photoelectric conversion element illustrated in FIG. 10.
  • FIG. 11C is a diagram illustrating a step in the method of manufacturing the photoelectric conversion element illustrated in FIG. 10.
  • FIG. 11A is a diagram illustrating a step in the method of manufacturing the photoelectric conversion element illustrated in FIG. 10.
  • FIG. 11B is a diagram illustrating a step in the method for manufacturing the photoelectric conversion element illustrated in FIG. 10.
  • FIG. 11D is a diagram illustrating a step in the method of manufacturing the photoelectric conversion element illustrated in FIG. 10.
  • FIG. 11E is a cross-sectional view showing a schematic configuration of the photoelectric conversion element completed through the steps shown in FIGS. 11A to 11D.
  • FIG. 12 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the fifth embodiment.
  • FIG. 13 is a schematic diagram illustrating a configuration example of a photoelectric conversion module according to the sixth embodiment.
  • FIG. 14 is a schematic diagram illustrating a configuration example of the solar power generation system according to the seventh embodiment.
  • FIG. 15 is a schematic diagram illustrating a configuration example of the photoelectric conversion module array illustrated in FIG. 14.
  • FIG. 16 is a schematic diagram illustrating another configuration example of the solar power generation system according to the seventh embodiment.
  • FIG. 17 is a schematic diagram illustrating a configuration example of the solar power generation system according to the eighth embodiment.
  • FIG. 18 is a schematic diagram illustrating another configuration example of the solar power generation system according to the eighth embodiment.
  • the photoelectric conversion element according to the embodiment is formed on a semiconductor substrate, one surface of the semiconductor substrate, and has at least one concave portion on the surface, and is formed on a passivation layer made of an intrinsic amorphous semiconductor, and on the passivation layer.
  • the passivation layer is interposed between the first and second amorphous semiconductor layers and the semiconductor substrate, the semiconductor is formed when the first and second amorphous semiconductor layers are formed.
  • the interface portion between the substrate and the passivation layer is not easily damaged. For this reason, favorable passivation property can be ensured.
  • At least one of the first and second amorphous semiconductor layers is disposed in the recess provided on the surface of the passivation layer. That is, in the passivation layer, the thickness of at least one of the portion where the first amorphous semiconductor layer is disposed and the portion where the second amorphous semiconductor layer is disposed is smaller than the thickness of the other portion. For this reason, the contact resistance between the semiconductor substrate and the passivation layer can be reduced.
  • Both the first amorphous semiconductor layer and the second amorphous semiconductor layer may be disposed in the recess (second configuration).
  • the thickness of both the portion where the first amorphous semiconductor layer is disposed and the portion where the second amorphous semiconductor layer is disposed is smaller than the thickness of the other portion. Become. For this reason, the contact resistance between the passivation layer and the semiconductor substrate can be further reduced.
  • the thickness of the passivation layer in the region where the first amorphous semiconductor layer is in contact may be different from the thickness in the region where the second amorphous semiconductor layer is in contact (third configuration).
  • the thickness of the region in contact with the first amorphous semiconductor layer and the thickness of the region in contact with the second amorphous semiconductor layer can be determined according to the characteristics of the photoelectric conversion element. For this reason, passivation property can be improved efficiently.
  • the first amorphous semiconductor layer may have an n-type conductivity
  • the second amorphous semiconductor layer may have a p-type conductivity.
  • the thickness in the region in contact with the second amorphous semiconductor layer may be larger than the thickness in the region in contact with the first amorphous semiconductor layer (fourth configuration).
  • the passivation layer is formed so that the thickness of the region in contact with the second amorphous semiconductor layer having the p-type conductivity is relatively large.
  • the passivation layer may have a thickness of 5 nm to 20 nm in a portion where no recess is provided (fifth configuration).
  • the portion of the passivation layer where the first and second amorphous semiconductor layers are not disposed has a sufficient thickness to protect the semiconductor substrate. Therefore, recombination of carriers (electrons and holes) can be suppressed in a region corresponding to the first and second amorphous semiconductor layers in the semiconductor substrate, and good passivation can be realized. .
  • FIG. 1 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the first embodiment.
  • the photoelectric conversion element 10 includes a semiconductor substrate 1, an antireflection film 2, a passivation layer 3, an n-type amorphous semiconductor layer 4, a p-type amorphous semiconductor layer 5, an electrode. 6 and 7.
  • the semiconductor substrate 1 is, for example, an n-type single crystal silicon substrate.
  • the semiconductor substrate 1 has a thickness of 100 to 150 ⁇ m, for example.
  • a texture structure is formed on one surface of the semiconductor substrate 1.
  • the surface on which the texture structure is formed is referred to as a light receiving surface, and the surface opposite to the light receiving surface is referred to as a back surface.
  • the antireflection film 2 is formed on the light receiving surface of the semiconductor substrate 1.
  • the antireflection film 2 is made of, for example, a silicon nitride film.
  • the antireflection film 2 has a film thickness of 60 nm, for example.
  • the passivation layer 3 is formed on the back surface of the semiconductor substrate 1.
  • the passivation layer 3 has a plurality of recesses 34a and 34b on the surface.
  • the recesses 34a and 34b are formed in the passivation layer 3 by, for example, etching using hydrogen plasma.
  • the upper surface in the thickness direction of the passivation layer 3 includes a first region 31 in contact with the n-type amorphous semiconductor layer 4 and a second region 32 in contact with the p-type amorphous semiconductor layer 5.
  • the upper surface in the thickness direction of the passivation layer 3 further includes a third region 33 where neither the n-type amorphous semiconductor layer 4 nor the p-type amorphous semiconductor layer 5 is in contact.
  • region 31 is an area
  • the bottom surface of the recess 34 a does not reach the interface between the semiconductor substrate 1 and the passivation layer 3.
  • the bottom surface of the recess 34 a is positioned above the interface between the semiconductor substrate 1 and the passivation layer 3 in the thickness direction.
  • the thickness T31 of the passivation layer 3 in the first region 31 is smaller than the thickness T33 of the passivation layer 3 in the third region 33.
  • the thickness T31 can be appropriately determined within a range of 2 to 10 nm, for example.
  • region 32 is an area
  • the bottom surface of the recess 34 b does not reach the interface between the semiconductor substrate 1 and the passivation layer 3. That is, the bottom surface of the recess 34 b is positioned above the interface between the semiconductor substrate 1 and the passivation layer 3 in the thickness direction.
  • the thickness T32 of the passivation layer 3 in the second region 32 is smaller than the thickness T33 of the passivation layer 3 in the third region 33.
  • the thickness T32 can be appropriately determined within a range of 2 to 10 nm, for example.
  • the thickness T32 in the second region 32 is different from the thickness T31 in the first region 31.
  • the thickness T32 is larger than the thickness T31.
  • the thickness T32 may be smaller than the thickness T31 or may be equal to the thickness T31.
  • the recesses 34a and 34b are provided so as not to overlap each other. That is, the first region 31 and the second region 32 are spaced apart in the in-plane direction of the semiconductor substrate 1. A third region 33 is interposed between the first region 31 and the second region 32 in the in-plane direction of the semiconductor substrate 1.
  • the distance G between the first region 31 and the second region 32 in the in-plane direction of the semiconductor substrate 1 is preferably 250 ⁇ m or less.
  • the interval G is the shortest distance between the edge of the first region 31 and the edge of the second region 32 in the in-plane direction of the semiconductor substrate 1.
  • region 33 is an area
  • the thickness T33 in the third region 33 can be set in the range of 5 nm to 20 nm.
  • the n-type amorphous semiconductor layer 4 is formed on the passivation layer 3. More specifically, the n-type amorphous semiconductor layer 4 is formed in the recess 34a. Therefore, the n-type amorphous semiconductor layer 4 is in contact with the bottom surface of the recess 34 a that is the first region 31.
  • the thickness of the n-type amorphous semiconductor layer 4 is, for example, 3 to 50 nm.
  • the n-type amorphous semiconductor layer 4 is an amorphous semiconductor layer having n-type conductivity and containing hydrogen.
  • the n-type amorphous semiconductor layer 4 contains, for example, phosphorus (P) as an n-type dopant.
  • the n-type amorphous semiconductor layer 4 includes, for example, n-type amorphous silicon, n-type amorphous silicon germanium, n-type amorphous germanium, n-type amorphous silicon carbide, and n-type amorphous silicon nitride. N-type amorphous silicon oxide, n-type amorphous silicon oxynitride, n-type amorphous silicon carbon oxide, or the like.
  • the p-type amorphous semiconductor layer 5 is formed on the passivation layer 3. More specifically, the p-type amorphous semiconductor layer 5 is formed in the recess 34b. Therefore, the p-type amorphous semiconductor layer 5 is in contact with the bottom surface of the recess 34 b that is the second region 32.
  • the thickness of the p-type amorphous semiconductor layer 5 is, for example, 5 to 50 nm.
  • the p-type amorphous semiconductor layer 5 is an amorphous semiconductor layer having p-type conductivity and containing hydrogen.
  • the p-type amorphous semiconductor layer 5 includes, for example, boron (B) as a p-type dopant.
  • the p-type amorphous semiconductor layer 5 includes, for example, p-type amorphous silicon, p-type amorphous silicon germanium, p-type amorphous germanium, p-type amorphous silicon carbide, and p-type amorphous silicon nitride. , P-type amorphous silicon oxide, p-type amorphous silicon oxynitride, p-type amorphous silicon carbon oxide, or the like.
  • the second region 32 is arranged away from the first region 31 in the in-plane direction of the semiconductor substrate 1. Therefore, on the surface of the passivation layer 3, the p-type amorphous semiconductor layer 5 provided on the second region 32 is disposed away from the n-type amorphous semiconductor layer 4 provided on the first region 31. .
  • a plurality of n-type amorphous semiconductor layers 4 and a plurality of p-type amorphous semiconductor layers 5 are alternately arranged in the in-plane direction of the semiconductor substrate 1 on the passivation layer 3. .
  • the electrode 6 is formed on the n-type amorphous semiconductor layer 4.
  • the electrode 7 is formed on the p-type amorphous semiconductor layer 5.
  • each electrode 6 and 7 may have a laminated structure.
  • each electrode 6 and 7 may include a transparent conductive layer and a metal layer.
  • the thickness of the transparent conductive layer of each electrode 6 and 7 can be 3 to 100 nm, for example.
  • the thickness of the metal layer of each electrode 6 and 7 is preferably 50 nm or more.
  • the transparent conductive layer of the electrode 6 is preferably made of a material having high adhesion to the n-type amorphous semiconductor layer 4.
  • the transparent conductive layer of the electrode 7 is preferably made of a material having high adhesion to the p-type amorphous semiconductor layer 5.
  • the metal layers of the electrodes 6 and 7 are preferably made of a metal having high conductivity.
  • the transparent conductive layers of the electrodes 6 and 7 can be made of, for example, ITO (Indium Tin Oxide), ZnO, or IWO (Indium Tungsten Oxide).
  • the metal layers of the electrodes 6 and 7 are, for example, silver (Ag), nickel (Ni), aluminum (Al), copper (Cu), tin (Sn), platinum (Pt), gold (Au), chromium (Cr ), Tungsten (W), cobalt (Co), titanium (Ti), alloys thereof, or laminated films thereof.
  • the electrodes 6 and 7 may not include the above-described transparent conductive layer or metal layer.
  • the metal layer of each electrode 6, 7 is made of Ti, Ni, Al, Cr, etc., and has an adhesion layer having a thickness of about 1 to 10 nm, Al, It can have a laminated structure with a light reflecting metal layer mainly composed of Ag or the like.
  • FIG. 1 Manufacturing method of photoelectric conversion element
  • the semiconductor substrate 1 shown in FIG. 2A is prepared (first step).
  • a wafer having a thickness of 100 to 300 ⁇ m is cut out from bulk silicon, and etching for removing a damaged layer on the wafer surface and etching for adjusting the thickness are performed.
  • a protective film is formed on one surface of the etched wafer.
  • silicon oxide, silicon nitride, or the like is used for the protective film.
  • wet etching is performed on the wafer on which the protective film is formed using an alkaline solution such as NaOH or KOH (for example, an aqueous solution of KOH: 1 to 5 wt%, isopropyl alcohol: 1 to 10 wt%).
  • an alkaline solution such as NaOH or KOH
  • KOH for example, an aqueous solution of KOH: 1 to 5 wt%, isopropyl alcohol: 1 to 10 wt%.
  • the antireflection film 2 is formed on the light receiving surface of the semiconductor substrate 1, that is, the surface on which the texture structure is formed (second step).
  • the antireflection film 2 can be formed, for example, by sequentially stacking a silicon oxide film and a silicon nitride film on the light receiving surface of the semiconductor substrate 1.
  • the silicon oxide film can be formed by subjecting the light receiving surface of the semiconductor substrate 1 to thermal oxidation or wet treatment.
  • the thermal oxidation treatment for example, the semiconductor substrate 1 is heated to 900 to 1000 ° C. in an atmosphere of oxygen or water vapor.
  • wet processing for example, the semiconductor substrate 1 is immersed in hydrogen peroxide, nitric acid, ozone water, or the like, and then heated to 800 to 1000 ° C. in a dry atmosphere.
  • the silicon nitride film can be formed by, for example, a plasma CVD (Plasma Chemical Vapor Deposition) method.
  • An i-type amorphous semiconductor layer and an n-type amorphous semiconductor layer can be sequentially formed between the silicon nitride film and the semiconductor substrate 1 instead of the silicon oxide film.
  • the i-type amorphous semiconductor layer and the n-type amorphous semiconductor layer can be formed by, for example, a plasma CVD method.
  • an i-type amorphous semiconductor layer 300 is formed on the back surface of the semiconductor substrate 1 (third step).
  • i-type amorphous semiconductor layer 300 is formed by depositing i-type amorphous silicon on the entire back surface of semiconductor substrate 1 by plasma CVD.
  • the i-type amorphous silicon is deposited to a thickness sufficient to ensure good passivation, for example, 5 to 20 nm.
  • the i-type amorphous semiconductor layer 300 is formed to have a thickness T300 equal to the thickness T33 (FIG. 1) in the third region 33 of the passivation layer 3.
  • the reaction gas introduced into the reaction chamber provided in the plasma CVD apparatus is, for example, hydrogen gas and silane gas.
  • the processing conditions at this time are, for example, the temperature of the semiconductor substrate 1: 130 to 210 ° C., the hydrogen gas flow rate: 0 to 100 sccm, the silane gas (SiH 4 ) flow rate: about 40 sccm, the pressure in the reaction chamber: 40 to 120 Pa, and the frequency: 13 .56 MHz, power density: 5 to 15 mW / cm 2 .
  • the recess 34a is formed in the i-type amorphous semiconductor layer 300 (fourth step).
  • a shadow mask 200 is disposed on the i-type amorphous semiconductor layer 300.
  • the i-type amorphous semiconductor layer 300 is etched by, for example, hydrogen plasma through the opening 200 a of the shadow mask 200.
  • etching of a depth smaller than the thickness T300 of the i-type amorphous semiconductor layer 300 is performed so that the semiconductor substrate 1 is not exposed from the i-type amorphous semiconductor layer 300.
  • the recess 34 a is formed in the i-type amorphous semiconductor layer 300.
  • Etching with hydrogen plasma can be performed using a plasma CVD apparatus.
  • the processing conditions at this time are, for example, the temperature of the semiconductor substrate 1: 130 to 210 ° C., an atmosphere of 100% hydrogen gas, the pressure in the reaction chamber: 40 to 300 Pa, the frequency: 13.56 MHz, and the power density: 10 to 100 mW / cm 2 , treatment time: 10 to 300 seconds.
  • etch back of several nm can be performed without penetrating the i-type amorphous semiconductor layer 300, and the interface between the semiconductor substrate 1 and the i-type amorphous semiconductor layer 300 is damaged by etching. Can be prevented.
  • FIG. 3 is a diagram showing the relationship between the etching depth and the width of the opening 200a (the length of the opening 200a in the in-plane direction of the semiconductor substrate 1).
  • FIG. 3 shows the etching depth when etching is performed in the same time when the width of the opening 200a of the shadow mask 200 is 200 ⁇ m, 400 ⁇ m, 600 ⁇ m, 800 ⁇ m, and 1000 ⁇ m.
  • FIG. 3 shows that the larger the width of the opening 200a, the smaller the etching depth and the slower the etching rate. That is, if the width of the opening 200a is large, a wide and shallow concave portion 34a is formed, and if the width of the opening 200a is small, a narrow and deep concave portion 34a is formed.
  • the recesses 34a having various shapes can be formed.
  • the n-type amorphous semiconductor layer 4 is formed in the recess 34a (fifth step).
  • an n-type amorphous material is formed in the recess 34a through the opening 200a by plasma CVD. Deposit quality silicon. Thereby, the n-type amorphous semiconductor layer 4 is formed in the recess 34a.
  • the reaction gas introduced into the reaction chamber provided in the plasma CVD apparatus is, for example, silane gas, hydrogen gas, and phosphine gas diluted with hydrogen gas (phosphine concentration is 1%, for example) ).
  • the processing conditions at this time are, for example, a temperature of the semiconductor substrate 1 of about 170 ° C., a hydrogen gas flow rate of 0 to 100 sccm, a silane gas flow rate of about 40 sccm, a phosphine gas flow rate of about 40 sccm, a pressure in the reaction chamber of about 40 Pa, and a high frequency power. Density: about 8.33 mW / cm 2 .
  • FIG. 4A shows a result of measuring the film thickness of the n-type amorphous semiconductor layer 4 by scanning the n-type amorphous semiconductor layer 4 in the in-plane direction of the semiconductor substrate 1 with a stylus profilometer.
  • the n-type amorphous semiconductor layer 4 formed through the opening 200a of the shadow mask 200 includes a flat region L, a film thickness reduction region T, and a tapered region R, as shown in FIG. 4A.
  • the thickness of the n-type amorphous semiconductor layer 4 normalized by setting the thickness of the flat region L to 1.0 is plotted on the vertical axis.
  • the n-type amorphous semiconductor layer 4 has the maximum film thickness at a point C that is substantially the center in the in-plane direction of the semiconductor substrate 1.
  • the flat region L is a region where the film thickness hardly changes from the maximum film thickness. In the example of FIG. 4A, the region between the lengths in the scanning direction between 280 ⁇ m and 380 ⁇ m is the flat region L.
  • the length of the flat region L depends on the width of the opening 200a, but the deposition (deposition rate) does not depend on the width of the opening 200a.
  • the film thickness gradually decreases in the region from one end K10 to the point K11 of the flat region L and the region from the other end K20 to the point K12 of the flat region L.
  • the film thickness sharply decreases in the region from the point K11 to the point K21 and the region from the point K12 to the point K22. That is, rather than the reduction rate (first reduction rate) of each film thickness in the region from one end K10 to the point K11 of the flat region L and the region from the other end K20 to the point K12 of the flat region L, The decreasing rate (second decreasing rate) of each film thickness in the region from the point K11 to the point K21 and the region from the point K12 to the point K22 is large.
  • the film thickness reduction region T is a region in which the film thickness reduction rate gradually changes in the n-type amorphous semiconductor layer 4, and includes a region from the end K10 to the point K11 of the flat region L and an end of the flat region L. This is an area from the portion K20 to the point K12. That is, the film thickness reduction region T has a first point at which the film thickness of the thin film is maximized in one thin film formed on the semiconductor substrate 1, and the film thickness decreases in the in-plane direction of the thin film. When the point at which the rate of decrease changes from the first rate of decrease to the second rate of decrease is taken as the second point, this is the region from the first point to the second point in the in-plane direction of the thin film.
  • the tapered region R is a region formed in a tapered shape, and is a region from the points K21 and K22 to the lower ends K31 and K32 of the n-type amorphous semiconductor layer 4, respectively.
  • the tapered region R is a region formed around the opening 200 a, that is, around the shadow mask 200.
  • the width of the tapered region R varies depending on the film forming conditions of the n-type amorphous semiconductor layer 4 and is, for example, 400 ⁇ m or less, preferably 100 ⁇ m or less.
  • the amount of film thickness reduction in the film thickness reduction region T is preferably 5% or more of the film thickness of the flat region L, and more preferably 10% or more. That is, in FIG. 4A, the amount of decrease in the film thickness from the ends K10, K20 of the flat region L to the points K11, K21 is preferably 5% or more of the film thickness of the flat region L, and is preferably 10% or more. It is more preferable. In the example of FIG. 4A, the film thickness reduction region T is reduced by 20% or more than the film thickness of the flat region L, which is a preferable state.
  • the width of the film thickness reduction region T is preferably 20 ⁇ m or more, and more preferably 100 ⁇ m or more.
  • FIG. 4B is a diagram showing another shape of the n-type amorphous semiconductor layer 4.
  • the n-type amorphous semiconductor layer 4 does not have the flat region L, but the film thickness of the region from the point C to the point K10 that is the approximate center of the n-type amorphous semiconductor layer 4 is increased.
  • the decreasing rate is smaller than the decreasing rate of the film thickness in the region from the point K10 to the point K20.
  • Each region T1 from the point C10 to the point K10 is a film thickness decreasing region of the n-type amorphous semiconductor layer 4 having the shape shown in FIG. 4B.
  • the film thickness outside the point K20 is substantially constant, and the tapered region R is not formed.
  • the tapered region R can be formed by adjusting the film forming pressure, the distance between the shadow mask 200 and the passivation layer 3, or the like.
  • the n-type amorphous semiconductor layer 4 may have a film thickness at a point C that is substantially the center in the in-plane direction of the semiconductor substrate 1 smaller than the film thickness at both ends. That is, the n-type amorphous semiconductor layer 4 may be formed in a shape in which the central portion is recessed from both end portions.
  • the n-type amorphous semiconductor layer 4 has the first point at which the film thickness is maximum, and the reduction rate of the film thickness in the in-plane direction of the n-type amorphous semiconductor layer 4 is The region from the first point to the second point in the in-plane direction of the n-type amorphous semiconductor layer 4 when the point where the first decrease rate changes to the second decrease rate is the second point.
  • a film thickness reduction region can be provided.
  • a recess 34b is formed in the i-type amorphous semiconductor layer 300 (sixth step).
  • a shadow mask 201 is disposed on the i-type amorphous semiconductor layer 300. Then, the i-type amorphous semiconductor layer 300 is etched by, for example, hydrogen plasma through the opening 201 a of the shadow mask 201. At this time, etching with a depth smaller than the thickness of the i-type amorphous semiconductor layer 300 is performed so that the semiconductor substrate 1 is not exposed from the i-type amorphous semiconductor layer 300. Thereby, the recess 34b is formed in the i-type amorphous semiconductor layer 300, and the passivation layer 3 is completed.
  • Etching with hydrogen plasma can be performed using a plasma CVD apparatus under the same processing conditions as in the fourth step. Therefore, even when the recess 34b is formed, etch back of several nm can be performed without penetrating the i-type amorphous semiconductor layer 300, and the interface between the semiconductor substrate 1 and the i-type amorphous semiconductor layer 300 is etched. Can prevent damage.
  • the etching depth when forming the recess 34b is different from the etching depth when forming the recess 34a.
  • the etching depth D34b when forming the recess 34b is smaller than the etching depth D34a when forming the recess 34a.
  • the recess 34b can be formed in various shapes depending on the width of the opening 201a of the shadow mask 201.
  • the concave portion 34b shallower than the concave portion 34a may be formed by making the width of the opening 201a larger than the opening 200a of the shadow mask 200 used for forming the concave portion 34a.
  • the shape of the recess 34b may be adjusted by changing the processing conditions such as the etching time when forming the recess 34a.
  • the p-type amorphous semiconductor layer 5 is formed in the recess 34b (seventh step).
  • a p-type is formed in the recess 34b through the opening 201a by the plasma CVD method.
  • Amorphous silicon is deposited.
  • the p-type amorphous semiconductor layer 5 is formed in the recess 34b.
  • the reaction gas introduced into the reaction chamber provided in the plasma CVD apparatus is, for example, silane gas, hydrogen gas, and diborane gas diluted with hydrogen (diborane concentration is about 2%, for example). is there.
  • the processing conditions at this time are, for example, the temperature of the semiconductor substrate 1: 150 to 210 ° C., hydrogen gas flow rate: 0 to 100 sccm, silane gas flow rate: about 40 sccm, diborane gas flow rate: about 40 sccm, pressure in the reaction chamber: 40 to 120 Pa, high frequency Power density: 5 to 15 mW / cm 2 .
  • the p-type amorphous semiconductor layer 5 formed through the opening 201a of the shadow mask 201 has the same shape as the n-type amorphous semiconductor layer 4 shown in FIG. That is, similarly to the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5 includes a flat region L, a film thickness reduction region T, and a tapered region R.
  • electrodes 6 and 7 are formed on the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, respectively (eighth step).
  • a mask 202 is disposed on the back surface of the semiconductor substrate 1 on which the passivation layer 3, the n-type amorphous semiconductor layer 4, and the p-type amorphous semiconductor layer 5 are formed. Then, electrodes 6 and 7 are formed on the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 through the openings 202a of the mask 202, for example, by vapor deposition or sputtering.
  • the photoelectric conversion element 10 shown in FIG. 2I is manufactured.
  • each mask 200, 201, 202 used in each of the above steps is, for example, a metal made of a metal such as stainless steel, copper, nickel, an alloy containing nickel (for example, 42 alloy or Invar material), molybdenum or the like. It is a mask.
  • Each mask 200 to 204 may be made of glass, ceramic, organic film or the like.
  • the passivation layer 3 is interposed between the semiconductor substrate 1 and the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5. Yes.
  • the interface portion between the semiconductor substrate 1 and the passivation layer 3 is not easily damaged. Therefore, good passivation properties can be ensured.
  • the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are disposed in the recesses 34a and 34b of the passivation layer 3, respectively. That is, in the passivation layer 3, the thickness T31 in the first region 31 that is in contact with the n-type amorphous semiconductor layer 4 and the thickness T32 in the second region 32 that is in contact with the p-type amorphous semiconductor layer 5 are n-type amorphous. It is smaller than the thickness T33 in the third region 33 where the semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are not in contact. For this reason, the contact resistance between the semiconductor substrate 1 and the passivation layer 3 can be reduced in the n-side region and the p-side region.
  • the thickness T32 of the second region 32 in contact with the p-type amorphous semiconductor layer 5 is larger than the thickness T31 of the first region 31 in contact with the n-type amorphous semiconductor layer 4.
  • the recesses 34 a and 34 b are formed without exposing the semiconductor substrate 1 from the i-type amorphous semiconductor layer 300. For this reason, when forming the recesses 34a and 34b, the interface portion between the semiconductor substrate 1 and the i-type amorphous semiconductor layer 300 (passivation layer 3) is not damaged, and the passivation property can be improved.
  • the semiconductor substrate 1 has a texture structure on the light receiving surface. For this reason, it is possible to prevent light from being reflected from the light receiving surface of the semiconductor substrate 1, and to ensure a large amount of light incident on the photoelectric conversion element 10.
  • the thickness T33 of the third region 33 where the n-type and p-type amorphous semiconductor layers 4 and 5 are not in contact with each other is, for example, 5 nm to 20 nm.
  • the thicknesses T31 and T32 of the first region 31 in contact with the n-type amorphous semiconductor layer 4 and the second region 32 in contact with the p-type amorphous semiconductor layer 5 are, for example, 2 nm to 10 nm. .
  • the thickness of the portion where the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are disposed is sufficiently small, and the contact resistance in the n-side and p-side regions is more reliably ensured. Can be reduced.
  • the distance G between the first region 31 and the second region 32 in the in-plane direction of the semiconductor substrate 1 is, for example, 250 ⁇ m or less. Thereby, a large area of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 disposed on the passivation layer 3 can be secured, and the collection efficiency of carriers (electrons and holes) is improved. Can be made.
  • the passivation layer 3 is formed by forming the i-type amorphous semiconductor layer 300 on the back surface of the semiconductor substrate 1 and then providing the recesses 34 a and 34 b in the i-type amorphous semiconductor layer 300.
  • the back surface of the semiconductor substrate 1 is not exposed from the i-type amorphous semiconductor layer 300. That is, the passivation layer 3 is formed without going through a step of exposing a part of the back surface of the semiconductor substrate 1. For this reason, the interface portion between the semiconductor substrate 1 and the passivation layer 3 is not damaged, and good passivation can be realized.
  • the formation of the recess 34 a of the passivation layer 3 and the formation of the n-type amorphous semiconductor layer 4 are performed continuously using the same shadow mask 200.
  • the formation of the recess 34 b of the passivation layer 3 and the formation of the p-type amorphous semiconductor layer 5 are performed continuously using the same shadow mask 201. For this reason, it can suppress that an impurity mixes into the passivation layer 3, and can ensure favorable passivation property.
  • FIG. 5 is a diagram illustrating the lifetime of the photoelectric conversion element 10 for each thickness of the passivation layer 3.
  • FIG. 6A is a diagram illustrating the contact resistance in the n-side region for each thickness of the first region 31.
  • FIG. 6B is a diagram showing the contact resistance in the p-side region for each thickness of the second region 32.
  • the film thickness of 1.75 times, the film thickness of 1.5 times, and the film thickness of 1.25 times are 1.75 times that the passivation layer 3 has a predetermined thickness (standard film thickness). It means having double thickness, 1.5 times thickness, and 1.25 times thickness.
  • the lifetime of the photoelectric conversion element 10 exhibiting passivation properties increases as the thickness of the passivation layer 3 increases.
  • the thickness of the passivation layer 3 increases, deterioration with time is alleviated. From this, it can be seen that if the thickness of the passivation layer 3 is increased, good passivation properties can be secured.
  • the contact resistance in the p-side region significantly increases as the thickness T32 of the second region 32 increases. Therefore, it can be seen that the contact resistance can be effectively reduced by making the thickness T32 of the second region 32 smaller than the thicknesses T31 and T33 of the other regions in the passivation layer 3.
  • the contact resistance in the n-side region does not increase significantly according to the thickness T31 of the first region 31, but in addition to the thickness T32 of the second region 32, If the thickness T31 is made smaller than the thickness T33 of other regions, the contact resistance can be further reduced.
  • the thickness T33 of the third region 33 where the n-type and p-type amorphous semiconductor layers 4 and 5 are not in contact is sufficiently ensured.
  • the thickness T31 of the first region 31 in contact with the n-type amorphous semiconductor layer 4 and the thickness T32 of the second region 32 in contact with the p-type amorphous semiconductor layer 5 are the third region. It is smaller than the thickness T33 of 33. Therefore, it is possible to reduce contact resistance while ensuring good passivation.
  • FIG. 7 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the second embodiment.
  • the photoelectric conversion element 102 is first in that a part of the n-type amorphous semiconductor layer 4 and a part of the p-type amorphous semiconductor layer 5 overlap on the passivation layer 320. Different from the embodiment.
  • a recess 324 having a stepped bottom surface is formed in the passivation layer 320.
  • the lower surface of the bottom surface of the recess 324 is a first region 321 in contact with the n-type amorphous semiconductor layer 4.
  • the upper surface of the bottom surface of the recess 324 is a second region 322 that is in contact with the p-type amorphous semiconductor layer 5.
  • the thickness T321 in the first region 321 is smaller than the thickness T322 in the second region 322, as in the first embodiment.
  • the thickness T323 of the third region 303 where the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are not in contact is larger than the thickness T321 in the first region 321 and the thickness T322 in the second region 322. .
  • the entire bottom surface of the n-type amorphous semiconductor layer 4 is in contact with the first region 321 of the passivation layer 3.
  • the p-type amorphous semiconductor layer 5 has most of the bottom surface in contact with the second region 322 of the passivation layer 3, but part of the bottom surface is in contact with the top surface in the thickness direction of the n-type amorphous semiconductor layer 4. Yes. That is, the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are disposed on the passivation layer 3 so as to partially overlap.
  • the p-type amorphous semiconductor layer 5 partially overlaps the n-type amorphous semiconductor layer 4, but the n-type amorphous semiconductor layer is formed on the p-type amorphous semiconductor layer 5.
  • a part of 4 may overlap.
  • the thickness T321 of the first region 321 in which the n-type amorphous semiconductor layer 4 is disposed is set to a p-type amorphous.
  • the thickness T322 of the second region 322 where the quality semiconductor layer 5 is disposed may be smaller.
  • a texture structure is formed on the light receiving surface of the semiconductor substrate 1, and the antireflection film 2 is formed.
  • an i-type amorphous semiconductor layer 302 is formed on the back surface of the semiconductor substrate 1 in the same manner as in the third step of the first embodiment.
  • the recess 400a is formed on the i-type amorphous semiconductor layer 302, and the n-type amorphous semiconductor layer 4 is formed in the recess 400a.
  • the concave portion 400 b is formed in the i-type amorphous semiconductor layer 302.
  • the recess 400b can be formed by the same method and conditions as in the sixth step of the first embodiment. However, the recess 400b is different from the recess 34b formed in the sixth step of the first embodiment in that the recess 400b is formed in contact with the recess 400a. That is, the recess 400 b is formed adjacent to the recess 400 a so as not to be separated from the recess 400 a in the in-plane direction of the semiconductor substrate 1.
  • the i-type amorphous semiconductor layer 302 is etched by, for example, hydrogen plasma through the opening 203a of the shadow mask 200 to form the recess 400b.
  • etching with a depth smaller than the thickness of the i-type amorphous semiconductor layer 302 is performed so that the semiconductor substrate 1 is not exposed from the i-type amorphous semiconductor layer 302.
  • the etching depth for forming the recess 400b is smaller than the etching depth for forming the recess 400a.
  • a recess 324 having a stepped bottom surface is formed by the recesses 400a and 400b.
  • the p-type amorphous semiconductor layer 5 is formed in the recess 400b.
  • the p-type amorphous semiconductor layer 5 can be formed using, for example, a plasma CVD method under the same processing conditions as in the seventh step of the first embodiment. Specifically, as shown in FIG. 8C, the p-type amorphous semiconductor layer 5 is formed in the recess 400b through the opening 204a of the shadow mask 204. At this time, the recess 400b and a part of the n-type amorphous semiconductor layer 4 are exposed from the opening 204a. Therefore, a part of the p-type amorphous semiconductor layer 5 is formed on the n-type amorphous semiconductor layer 4 and the other part is formed in the recess 400b.
  • a plasma CVD method under the same processing conditions as in the seventh step of the first embodiment. Specifically, as shown in FIG. 8C, the p-type amorphous semiconductor layer 5 is formed in the recess 400b through the opening 204a of the shadow mask 204. At this time, the recess 400b and a part of the
  • electrodes 6 and 7 are formed on the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, respectively, in the same manner as in the eighth step of the first embodiment.
  • FIG. 9 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the third embodiment.
  • the n-type amorphous semiconductor layer 4 is disposed in the recess 334, and the p-type amorphous semiconductor layer 5 is disposed in the recess.
  • the first embodiment There is no difference from the first embodiment.
  • the bottom surface of the recess 334 formed in the passivation layer 330 is a first region 331 in contact with the n-type amorphous semiconductor layer 4.
  • the thickness T331 in the first region 331 is smaller than the thickness in other regions. That is, the thickness T331 is smaller than the thickness T332 of the second region 332 in contact with the p-type amorphous semiconductor layer 5, and the third region in which the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are not in contact. It is smaller than the thickness T333 of 333.
  • the p-type amorphous semiconductor layer 5 is not disposed in the recess of the passivation layer 330. Accordingly, in the passivation layer 330, the thickness T332 of the second region 332 in contact with the p-type amorphous semiconductor layer 5 is equal to the third region 333 in which the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are not in contact. Is substantially equal to the thickness T333.
  • the photoelectric conversion element 103 can be manufactured by the same method as the photoelectric conversion element 10 according to the first embodiment. However, in the photoelectric conversion element 103, since the p-type amorphous semiconductor layer 5 is not disposed in the recess of the passivation layer 330, the sixth step of forming the recess 34b for disposing the p-type amorphous semiconductor layer 5 is performed. It is unnecessary. That is, the photoelectric conversion element 103 can be manufactured through the first to fifth steps, the seventh step, and the eighth step of Embodiment 1.
  • the n-type amorphous semiconductor layer 4 is disposed in the recess 334 of the passivation layer 330.
  • the thickness T331 of the first region 331 with which the n-type amorphous semiconductor layer 4 is in contact is smaller than the thickness of other regions, so that the contact resistance can be reduced.
  • the thicknesses T332 and T333 of regions other than the first region 331 are relatively large, so that good passivation properties can be ensured.
  • the thickness T332 of the second region 332 in contact with the p-type amorphous semiconductor layer 5 is larger than the thickness T331 of the first region 331 in contact with the n-type amorphous semiconductor layer 4. For this reason, in the p-side region where the passivation property is likely to deteriorate, it is possible to suppress the deterioration of the passivation property.
  • FIG. 10 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the fourth embodiment.
  • the photoelectric conversion element 104 in the passivation layer 340, the p-type amorphous semiconductor layer 5 is disposed in the recess 344, and the n-type amorphous semiconductor layer 44 is disposed in the recess.
  • the photoelectric conversion element 104 is also different from the first embodiment in that the n-type amorphous semiconductor layer 44 has a separation portion 441.
  • the bottom surface of the recess 344 formed in the passivation layer 340 is a second region 342 in contact with the p-type amorphous semiconductor layer 5.
  • the thickness T342 in the second region 342 is smaller than the thickness in other regions. That is, the thickness T342 is smaller than the thickness T341 of the first region 341 in contact with the n-type amorphous semiconductor layer 44.
  • the n-type amorphous semiconductor layer 44 is separated into a plurality of parts by the separation part 441 in the in-plane direction of the semiconductor substrate 1. That is, the separation part 441 penetrates the n-type amorphous semiconductor layer 44 in the thickness direction and divides it in the in-plane direction of the semiconductor substrate 1.
  • a p-type amorphous semiconductor layer 5 is disposed in the separation portion 441.
  • a texture structure is formed on the light receiving surface of the semiconductor substrate 1, and the antireflection film 2 is formed.
  • an i-type amorphous semiconductor layer 304 is formed on the back surface of the semiconductor substrate 1 in the same manner as in the third step of the first embodiment.
  • an n-type amorphous semiconductor film 500 is formed on the i-type amorphous semiconductor layer 304.
  • the n-type amorphous semiconductor film 500 can be formed by a plasma CVD method in the same manner as the fifth step of the first embodiment. However, in the fourth embodiment, the n-type amorphous semiconductor film 500 is formed on the entire surface of the i-type amorphous semiconductor layer 304. For this reason, the shadow mask 200 used in the fifth step of the first embodiment is not disposed on the i-type amorphous semiconductor layer 304, and n-type amorphous silicon is deposited by plasma CVD.
  • a separation portion 441 is formed in the n-type amorphous semiconductor film 500 and a recess 344 is formed in the i-type amorphous semiconductor layer 304.
  • the n-type amorphous semiconductor film 500 and the i-type amorphous semiconductor layer 304 are etched using, for example, hydrogen plasma through the opening 205a of the shadow mask 205.
  • Do. Etching can be performed under the same conditions as in the fourth step of the first embodiment. The etching is performed at a depth that penetrates the n-type amorphous semiconductor film 500 and does not reach the interface between the i-type amorphous semiconductor layer 304 and the semiconductor substrate 1.
  • the passivation layer 340 having the recess 344 and the n-type amorphous semiconductor layer 44 separated in the in-plane direction of the semiconductor substrate 1 by the separation portion 441 are completed.
  • the p-type amorphous semiconductor layer 5 is formed in the recess 344 of the passivation layer 340 and the separation part 441 of the n-type amorphous semiconductor layer 44.
  • the p-type amorphous semiconductor layer 5 is formed by plasma CVD or the like through the opening 205a while the shadow mask 205 is disposed on the n-type amorphous semiconductor layer 44.
  • the film formation conditions at this time can be the same as those in the seventh step of the first embodiment.
  • the p-type amorphous semiconductor layer 5 is formed in the recess 344 of the passivation layer 340 and the separation portion 441 of the n-type amorphous semiconductor layer 44.
  • electrodes 6 and 7 are formed on the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, respectively, in the same manner as in the eighth step of the first embodiment.
  • the p-type amorphous semiconductor layer 5 is disposed in the recess 344 of the passivation layer 340.
  • the thickness T342 of the second region 342 in contact with the p-type amorphous semiconductor layer 5 is smaller than other regions, so that the contact resistance can be reduced.
  • the thickness T341 of the first region 341 in contact with the n-type amorphous semiconductor layer 44 in the passivation layer 340 is relatively large, good passivation can be ensured.
  • FIG. 12 is a cross-sectional view illustrating a schematic configuration of the photoelectric conversion element according to the fifth embodiment.
  • the photoelectric conversion element 105 is different from the first embodiment in that the thickness T351 of the first region 351 and the thickness T352 of the second region 352 are equal in the passivation layer 350.
  • the passivation layer 350 has recesses 354a and 354b.
  • the n-type amorphous semiconductor layer 4 is disposed in the recess 354a.
  • the p-type amorphous semiconductor layer 5 is disposed in the recess 354b.
  • the bottom surfaces of the recesses 354a and 354b are a first region 351 in contact with the n-type amorphous semiconductor layer 4 and a second region 352 in contact with the p-type amorphous semiconductor layer 5, respectively.
  • the depths of the recesses 354a and 354b are substantially equal. That is, in the thickness direction of the passivation layer 350, the position of the bottom surface of the recess 354a is substantially equal to the position of the bottom surface of the recess 354b. Therefore, in the passivation layer 350, the thickness T351 of the first region 351 and the thickness T352 of the second region 352 are substantially equal. The thickness T351 of the first region 351 and the thickness T352 of the second region 352 are smaller than the thickness T353 of the third region 353 where the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 do not contact.
  • the photoelectric conversion element 105 can be manufactured by the same method as in the first embodiment.
  • the first embodiment since the depths of the recesses 34a and 34b are different from each other, it is necessary to form the recesses 34a and 34b by changing the processing conditions such as the opening width of the shadow mask and the etching time.
  • the fifth embodiment since the depths of the recesses 354a and 354b are the same, the recesses 354a and 354b can be formed with the same opening width of the shadow mask and other processing conditions.
  • the photoelectric conversion element 105 also has the thickness T351 of the first region 351 in contact with the n-type amorphous semiconductor layer 4 and the p-type in the passivation layer 330, as in the first embodiment.
  • Both the thickness T352 of the second region 352 that the amorphous semiconductor layer 5 is in contact with are smaller than the thickness T353 of the third region 353 that the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are not in contact with. For this reason, favorable passivation property can be ensured and contact resistance can be reduced.
  • FIG. 13 is a schematic diagram illustrating a configuration of a photoelectric conversion module according to the sixth embodiment.
  • the photoelectric conversion module 1000 includes a plurality of photoelectric conversion elements 1001, a cover 1002, and output terminals 1003 and 1004.
  • At least one of the plurality of photoelectric conversion elements 1001 is any one of the photoelectric conversion elements 10 and 102 to 105 according to the first to fifth embodiments.
  • the plurality of photoelectric conversion elements 1001 are, for example, arranged in an array and connected in series. Instead of connecting in series, parallel connection or a combination of series and parallel may be performed.
  • the cover 1002 is made of a weather resistant cover and covers the plurality of photoelectric conversion elements 1001.
  • the cover 1002 includes, for example, a transparent base material (for example, glass) provided on the light receiving surface side of the photoelectric conversion element 1001 and a back surface base material (on the reverse side opposite to the light receiving surface side of the photoelectric conversion element 1001).
  • a transparent base material for example, glass
  • a back surface base material on the reverse side opposite to the light receiving surface side of the photoelectric conversion element 1001
  • glass, a resin sheet, etc. and the sealing material (for example, EVA etc.) which fills the clearance gap between the said transparent base material and the said resin base material are included.
  • the output terminal 1003 is connected to a photoelectric conversion element 1001 with a wiring sheet disposed at one end of a plurality of photoelectric conversion elements 1001 connected in series.
  • the output terminal 1004 is connected to the photoelectric conversion element 1001 disposed at the other end of the plurality of photoelectric conversion elements 1001 connected in series.
  • the photoelectric conversion elements 10 and 102 to 105 have a high open circuit voltage (Voc) and improved element characteristics. Therefore, the performance of the photoelectric conversion module 1000 can be improved.
  • Voc open circuit voltage
  • the photoelectric conversion module according to the present embodiment is not limited to the configuration shown in FIG. 13, but any configuration as long as any one of the photoelectric conversion elements 10 and 102 to 105 according to the first to fifth embodiments is used. May be.
  • FIG. 14 is a schematic diagram illustrating a configuration of a photovoltaic power generation system according to the seventh embodiment.
  • the photovoltaic power generation system 1100 includes a photoelectric conversion module array 1101, a connection box 1102, a power conditioner 1103, a distribution board 1104, and a power meter 1105.
  • Functions such as “Home Energy Management System (HEMS)” and “Building Energy Management System (BEMS)” are added to the photovoltaic power generation system 1100. Can do.
  • HEMS Home Energy Management System
  • BEMS Building Energy Management System
  • connection box 1102 is connected to the photoelectric conversion module array 1101.
  • the power conditioner 1103 is connected to the connection box 1102.
  • Distribution board 1104 is connected to power conditioner 1103 and electrical equipment 1110.
  • the power meter 1105 is connected to the distribution board 1104 and system linkage.
  • the photoelectric conversion module array 1101 converts sunlight into electricity to generate DC power, and supplies the generated DC power to the connection box 1102.
  • connection box 1102 receives the DC power generated by the photoelectric conversion module array 1101 and supplies the received DC power to the power conditioner 1103.
  • the power conditioner 1103 converts the DC power received from the connection box 1102 into AC power, and supplies the converted AC power to the distribution board 1104.
  • Distribution board 1104 supplies AC power received from power conditioner 1103 and / or commercial power received via power meter 1105 to electrical equipment 1110. Further, when the AC power received from the power conditioner 1103 is larger than the power consumption of the electrical equipment 1110, the distribution board 1104 supplies the surplus AC power to the system linkage via the power meter 1105.
  • the power meter 1105 measures the power in the direction from the grid connection to the distribution board 1104 and measures the power in the direction from the distribution board 1104 to the grid cooperation.
  • FIG. 15 is a schematic diagram showing the configuration of the photoelectric conversion module array 1101 shown in FIG.
  • photoelectric conversion module array 1101 includes a plurality of photoelectric conversion modules 1120 and output terminals 1121 and 1122.
  • the plurality of photoelectric conversion modules 1120 are arranged in an array and connected in series. Each of the plurality of photoelectric conversion modules 1120 includes a photoelectric conversion module 1000 shown in FIG.
  • the output terminal 1121 is connected to a photoelectric conversion module 1120 located at one end of a plurality of photoelectric conversion modules 1120 connected in series.
  • the output terminal 1122 is connected to the photoelectric conversion module 1120 located at the other end of the plurality of photoelectric conversion modules 1120 connected in series.
  • the photoelectric conversion module array 1101 generates sunlight by converting sunlight into electricity, and supplies the generated DC power to the power conditioner 1103 via the connection box 1102.
  • the power conditioner 1103 converts the DC power received from the photoelectric conversion module array 1101 into AC power, and supplies the converted AC power to the distribution board 1104.
  • the distribution board 1104 supplies the AC power received from the power conditioner 1103 to the electrical device 1110 when the AC power received from the power conditioner 1103 is greater than or equal to the power consumption of the electrical device 1110. Then, the distribution board 1104 supplies surplus AC power to the system linkage via the power meter 1105.
  • Distribution board 1104 supplies AC power received from system cooperation and AC power received from power conditioner 1103 to electric device 1110 when the AC power received from power conditioner 1103 is less than the power consumption of electric device 1110. To do.
  • the photovoltaic power generation system 1100 includes any of the photoelectric conversion elements according to the first to fifth embodiments having improved element characteristics. Therefore, the performance of the photovoltaic power generation system 1100 can be improved.
  • the photovoltaic power generation system according to the present embodiment is not limited to the configuration shown in FIGS. 14 and 15, and may have any configuration as long as any of the photoelectric conversion elements according to the first to fifth embodiments is used. Also good.
  • a storage battery 1106 may be connected to the power conditioner 1103. In this case, output fluctuation due to fluctuations in the amount of sunlight can be suppressed, and power stored in the storage battery 1106 can be supplied even in a time zone without sunlight.
  • the storage battery 1106 may be built in the power conditioner 1103.
  • FIG. 17 is a schematic diagram illustrating a configuration of a photovoltaic power generation system according to the eighth embodiment.
  • the photovoltaic power generation system 1200 includes subsystems 1201 to 120n (n is an integer of 2 or more), power conditioners 1211 to 121n, and a transformer 1221.
  • the photovoltaic power generation system 1200 is a photovoltaic power generation system having a larger scale than the photovoltaic power generation system 1100 shown in FIGS.
  • the power conditioners 1211 to 121n are connected to the subsystems 1201 to 120n, respectively.
  • the transformer 1221 is connected to the power conditioners 1211 to 121n and the system linkage.
  • Each of the subsystems 1201 to 120n includes module systems 1231 to 123j (j is an integer of 2 or more).
  • Each of the module systems 1231 to 123j includes photoelectric conversion module arrays 1301 to 130i (i is an integer of 2 or more), connection boxes 1311 to 131i, and a current collection box 1321.
  • Each of the photoelectric conversion module arrays 1301 to 130i has the same configuration as the photoelectric conversion module array 1101 shown in FIG.
  • connection boxes 1311 to 131i are connected to the photoelectric conversion module arrays 1301 to 130i, respectively.
  • the current collection box 1321 is connected to the connection boxes 1311 to 131i. Also, j current collection boxes 1321 of the subsystem 1201 are connected to the power conditioner 1211. The j current collection boxes 1321 of the subsystem 1202 are connected to the power conditioner 1212. Hereinafter, similarly, j current collection boxes 1321 of the subsystem 120n are connected to the power conditioner 121n.
  • the i photoelectric conversion module arrays 1301 to 130i of the module system 1231 generate sunlight by converting sunlight into electricity, and the generated DC power is collected through the connection boxes 1311 to 131i, respectively.
  • the i photoelectric conversion module arrays 1301 to 130i of the module system 1232 generate sunlight by converting sunlight into electricity, and the generated DC power is collected through the connection boxes 1311 to 131i, respectively.
  • the i photoelectric conversion module arrays 1301 to 130i of the module system 123j convert sunlight into electricity to generate DC power, and the generated DC power is connected to the connection boxes 1311 to 131i, respectively. To the current collection box 1321.
  • the j current collection boxes 1321 of the subsystem 1201 supply DC power to the power conditioner 1211.
  • the j current collection boxes 1321 of the subsystem 1202 supply DC power to the power conditioner 1212 in the same manner.
  • the j current collecting boxes 1321 of the subsystem 120n supply DC power to the power conditioner 121n.
  • the power conditioners 1211 to 121n convert the DC power received from the subsystems 1201 to 120n into AC power, and supply the converted AC power to the transformer 1221.
  • the transformer 1221 receives AC power from the power conditioners 1211 to 121n, converts the voltage level of the received AC power, and supplies it to the system linkage.
  • the photovoltaic power generation system 1200 includes any of the photoelectric conversion elements according to the first to fifth embodiments having improved element characteristics. Therefore, the performance of the photovoltaic power generation system 1200 can be improved.
  • the photovoltaic power generation system according to the eighth embodiment is not limited to the configuration shown in FIG. 17, and any configuration can be used as long as any of the photoelectric conversion elements according to the first to fifth embodiments is used. Good.
  • a storage battery 1213 may be connected to the power conditioners 1211 to 121n, or the storage battery 1213 may be built in the power conditioners 1211 to 121n.
  • the power conditioners 1211 to 121n can appropriately convert part or all of the DC power received from the current collection box 1321 and store it in the storage battery 1213.
  • the electric power stored in the storage battery 1213 is appropriately supplied to the power conditioners 1211 to 121n according to the power generation amount of the subsystems 1201 to 120n, and is appropriately converted into electric power and supplied to the transformer 1221.
  • the texture structure is formed only on the light receiving surface of the semiconductor substrate.
  • the texture structure can be formed on the back surface of the semiconductor substrate.
  • the adhesion between the n-type amorphous semiconductor layer and the p-type amorphous semiconductor layer and each electrode is improved, and as a result, the yield and reliability of the photoelectric conversion element can be improved.
  • the contact area between the n-type amorphous semiconductor layer and the p-type amorphous semiconductor layer and each electrode is larger than when the back surface of the semiconductor substrate is flat, the contact resistance can also be reduced. .
  • the semiconductor substrate is an n-type single crystal silicon substrate.
  • the semiconductor substrate may be a p-type silicon substrate.
  • the antireflection film is formed on the light receiving surface of the semiconductor substrate, but the antireflection film may not be provided on the light receiving surface of the semiconductor substrate.
  • an n + layer in which a high concentration n-type dopant is diffused may be formed on the light receiving surface of the semiconductor substrate instead of the antireflection film.
  • an n + layer in which a high concentration n-type dopant is diffused may be formed between the light receiving surface of the semiconductor substrate and the antireflection film.
  • each amorphous semiconductor layer is formed using the plasma CVD method.
  • a CatCVD (Catalytic Chemical Vapor Deposition) method is used instead of the plasma CVD method. You can also.
  • the temperature of the semiconductor substrate is 100 to 300 ° C.
  • the deposition pressure is 10 to 500 Pa
  • the temperature of the thermal catalyst is 1500 to 2000 ° C.
  • RF power The film may be formed at a density of 0.01 to 1 W / cm 2 . By doing so, a high-quality amorphous semiconductor layer and a separation portion can be formed at a relatively low temperature and in a short time.

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  • Engineering & Computer Science (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Energy (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photovoltaic Devices (AREA)

Abstract

La présente invention concerne un élément de conversion photoélectrique qui permet d'obtenir une excellente passivation et de réduire la résistance de contact. L'élément de conversion photoélectrique (10) comprend : un substrat semi-conducteur (1) ; une couche de passivation (3) formée sur une surface du substrat semi-conducteur (1), la couche de passivation (3) ayant au moins un évidement (34a, 34b) sur la surface et comprenant un semi-conducteur amorphe intrinsèque ; une première couche semi-conductrice amorphe (4) formée sur la couche de passivation (3), la première couche semi-conductrice amorphe (4) ayant un premier type de conductivité ; et une seconde couche semi-conductrice amorphe (5) formée sur la couche de passivation (3), la seconde couche semi-conductrice amorphe (5) ayant un second type de conductivité qui est opposé au premier type de conductivité. La première couche semi-conductrice amorphe (4) et/ou la seconde couche semi-conductrice amorphe (5) sont disposées dans l'évidement (34a, 34b).
PCT/JP2015/081562 2014-11-14 2015-11-10 Élément de conversion photoélectrique WO2016076300A1 (fr)

Applications Claiming Priority (2)

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JP2014232118 2014-11-14
JP2014-232118 2014-11-14

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WO2016076300A1 true WO2016076300A1 (fr) 2016-05-19

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019181834A1 (fr) * 2018-03-23 2019-09-26 株式会社カネカ Procédé permettant de produire une cellule solaire, et cellule solaire
WO2020035987A1 (fr) * 2018-08-13 2020-02-20 株式会社カネカ Élément de conversion photoélectrique et procédé de fabrication d'élément de conversion photoélectrique
WO2020217999A1 (fr) * 2019-04-23 2020-10-29 株式会社カネカ Procédé de fabrication de cellule solaire et cellule solaire

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Publication number Priority date Publication date Assignee Title
JP2010129872A (ja) * 2008-11-28 2010-06-10 Kyocera Corp 太陽電池素子
JP2013191656A (ja) * 2012-03-13 2013-09-26 Sharp Corp 光電変換素子およびその製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010129872A (ja) * 2008-11-28 2010-06-10 Kyocera Corp 太陽電池素子
JP2013191656A (ja) * 2012-03-13 2013-09-26 Sharp Corp 光電変換素子およびその製造方法

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019181834A1 (fr) * 2018-03-23 2019-09-26 株式会社カネカ Procédé permettant de produire une cellule solaire, et cellule solaire
JPWO2019181834A1 (ja) * 2018-03-23 2021-03-11 株式会社カネカ 太陽電池の製造方法、および、太陽電池
JP7221276B2 (ja) 2018-03-23 2023-02-13 株式会社カネカ 太陽電池の製造方法、および、太陽電池
WO2020035987A1 (fr) * 2018-08-13 2020-02-20 株式会社カネカ Élément de conversion photoélectrique et procédé de fabrication d'élément de conversion photoélectrique
CN112567535A (zh) * 2018-08-13 2021-03-26 株式会社钟化 光电转换元件和光电转换元件的制造方法
JPWO2020035987A1 (ja) * 2018-08-13 2021-08-10 株式会社カネカ 光電変換素子および光電変換素子の製造方法
JP7053851B2 (ja) 2018-08-13 2022-04-12 株式会社カネカ 光電変換素子および光電変換素子の製造方法
CN112567535B (zh) * 2018-08-13 2024-03-26 株式会社钟化 光电转换元件和光电转换元件的制造方法
WO2020217999A1 (fr) * 2019-04-23 2020-10-29 株式会社カネカ Procédé de fabrication de cellule solaire et cellule solaire
JPWO2020217999A1 (ja) * 2019-04-23 2021-11-25 株式会社カネカ 太陽電池の製造方法および太陽電池
JP7169440B2 (ja) 2019-04-23 2022-11-10 株式会社カネカ 太陽電池の製造方法および太陽電池

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