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TWI581345B - 半導體裝置以及形成引線上接合互連用於鑲嵌半導體晶粒在扇出晶圓級晶片規模封裝中之方法 - Google Patents

半導體裝置以及形成引線上接合互連用於鑲嵌半導體晶粒在扇出晶圓級晶片規模封裝中之方法 Download PDF

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Publication number
TWI581345B
TWI581345B TW100130052A TW100130052A TWI581345B TW I581345 B TWI581345 B TW I581345B TW 100130052 A TW100130052 A TW 100130052A TW 100130052 A TW100130052 A TW 100130052A TW I581345 B TWI581345 B TW I581345B
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Taiwan
Prior art keywords
semiconductor die
semiconductor
bumps
conductive layer
track lines
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TW100130052A
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English (en)
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TW201214590A (en
Inventor
瑞莎Ａ 派蓋菈
拉簡德拉 潘斯
具俊謨
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史達晶片有限公司
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Publication of TW201214590A publication Critical patent/TW201214590A/zh
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Description

半導體裝置以及形成引線上接合互連用於鑲嵌半導體晶粒在扇出晶圓級晶片規模封裝中之方法
本發明大體上關於半導體裝置，且更明確地說，係關於半導體基板以及形成引線上接合或軌道上接合互連用於鑲嵌半導體晶粒在扇出晶圓級晶片規模封裝中之方法。
在現代的電子產品中經常會發現半導體裝置。半導體裝置會有不同數量與密度的電組件。離散式半導體裝置通常含有一種類型的電組件，舉例來說，發光二極體(Light Emitting Diode，LED)、小訊號電晶體、電阻器、電容器、電感器、以及功率金屬氧化物半導體場效電晶體(Metal Oxide Semiconductor Field Effect Transistor，MOSFET)。整合式半導體裝置通常含有數百個至數百萬個電組件。整合式半導體裝置的範例包含微控制器、微處理器、電荷耦合裝置(Charged-Coupled Device，CCD)、太陽能電池、以及數位微鏡裝置(Digital Micro-mirror Device，DMD)。
半導體裝置會實施各式各樣的功能，例如，訊號處理、高速計算、傳送與接收電磁訊號、控制電子裝置、將太陽光轉換成電能、以及產生電視顯示器的視覺投影。在娛樂領域、通訊領域、電力轉換領域、網路領域、電腦領域、以及消費性產品領域中皆會發現半導體裝置。在軍事應用、航空、自動車、工業控制器、以及辦公室設備中同樣會發現半導體裝置。
半導體裝置會利用半導體材料的電氣特性。半導體材料的原子結構會使得可藉由施加電場或基礎電流或是經由摻雜的處理來操縱其導電性。摻雜會將雜質引入至該半導體材料之中，用以操縱及控制該半導體裝置的傳導性。
一半導體裝置會含有主動式電氣結構與被動式電氣結構。主動式結構(其包含雙極電晶體與場效電晶體)會控制電流的流動。藉由改變摻雜的程度以及施加電場或基礎電流，該電晶體會提高或限制電流的流動。被動式結構(其包含電阻器、電容器、以及電感器)會創造用以實施各式各樣電功能所需要的電壓和電流之間的關係。該等被動式結構與主動式結構會被電連接以形成讓該半導體裝置實施高速計算及其它實用功能的電路。
半導體裝置通常會使用兩種複雜的製程來製造，也就是，前端製造以及後端製造，每一者皆可能涉及數百道步驟。前端製造涉及在一半導體晶圓的表面上形成複數個晶粒。每一個晶粒通常會相同並且含有藉由電連接主動式組件和被動式組件而形成的電路。後端製造涉及從已完成的晶圓中單體化裁切個別的晶粒並且封裝該晶粒，用以提供結構性支撐及環境隔離。
半導體製造的其中一個目標便係生產較小的半導體裝置。較小的裝置通常會消耗較少電力，具有較高效能，並且能夠更有效地生產。此外，較小的半導體裝置還會有較小的覆蓋面積，這係較小的末端產品所需要的。藉由改善前端製程可以達成較小的晶粒尺寸，從而導致具有較小以及較高密度之主動式組件和被動式組件的晶粒。後端製程可以藉由改善電互連材料及封裝材料而導致具有較小覆蓋面積的半導體裝置封裝。
在習知的扇出晶圓級晶片規模封裝(Fan-Out Chip Scale Package，FO-WLCSP)中，一有凸塊的半導體晶粒通常會藉由一囊封劑被鑲嵌至一載板並且被密封。該載板會被移除而且一增進互連結構會被形成在該囊封劑與半導體晶粒上。該半導體晶粒之上的該等凸塊通常會被接合至一被形成在該載板上或該互連結構裡面的凸塊觸墊。該等凸塊觸墊會增加互連間距並減少輸入/輸出(I/O)數。
本技術領域需要提供一種用於FO-WLCSP中半導體晶粒的細微間距互連。據此，於其中一實施例中，本發明係一種製造半導體裝置的方法，其包括下面步驟：提供一載板；在該載板上形成一包含複數條軌道線的傳導層；提供一半導體晶粒，其具有複數個接觸觸墊以及被形成在該等接觸觸墊上的多個第一凸塊；將該半導體晶粒鑲嵌至該傳導層，讓該等第一凸塊直接被接合至該等軌道線的一末端部分；在該半導體晶粒與傳導層上沉積一囊封劑；移除該載板；以及在該囊封劑與半導體晶粒上形成一互連結構。
於另一實施例中，本發明係一種製造半導體裝置的方法，其包括下面步驟：提供一載板；在該載板上形成一包含複數條軌道線的傳導層；提供一半導體晶粒，其具有複數個接觸觸墊以及被形成在該等接觸觸墊上的多個第一凸塊；將該半導體晶粒鑲嵌至該傳導層，讓該等第一凸塊直接被接合至該等軌道線；以及在該半導體晶粒與傳導層上沉積一囊封劑。該傳導層包含可潤濕的材料，以便在囊封期間減少該半導體晶粒的偏移。該方法還進一步包含下面的步驟：移除該載板；以及在該囊封劑與半導體晶粒上形成一互連結構。
於另一實施例中，本發明係一種製造半導體裝置的方法，其包括下面步驟：形成一包含複數條軌道線的傳導層；提供一半導體晶粒，其具有複數個接觸觸墊以及被形成在該等接觸觸墊上的多個第一凸塊；將該半導體晶粒鑲嵌至該傳導層，讓該等第一凸塊直接被接合至該等軌道線；以及在該半導體晶粒與傳導層上沉積一囊封劑。
於另一實施例中，本發明係一種半導體裝置，其包括：一傳導層，其包含複數條軌道線；一半導體晶粒，其具有複數個接觸觸墊以及被形成在該等接觸觸墊上的多個第一凸塊；該半導體晶粒會被鑲嵌至該傳導層，讓該等第一凸塊直接被接合至該等軌道線；一囊封劑，其會被沉積在該半導體晶粒與傳導層上；以及一互連結構，其會被形成在該囊封劑與半導體晶粒上。
下面的說明書中會參考圖式於一或多個實施例中來說明本發明，於該等圖式中，相同的符號代表相同或雷同的元件。雖然本文係以達成本發明目的的最佳模式來說明本發明；不過，熟習本技術的人士便會明白，本發明希望涵蓋受到下面揭示內容及圖式支持的隨附申請專利範圍及它們的等效範圍所定義的本發明的精神與範疇內可能併入的替代例、修正例、以及等效例。
半導體裝置通常會使用兩種複雜的製程來製造：前端製造和後端製造。前端製造涉及在一半導體晶圓的表面上形成複數個晶粒。該晶圓上的每一個晶粒皆含有主動式電組件和被動式電組件，它們會被電連接而形成功能性電路。主動式電組件(例如電晶體與二極體)能夠控制電流的流動。被動式電組件(例如電容器、電感器、電阻器、以及變壓器)會創造用以實施電路功能所需要的電壓和電流之間的關係。
被動式組件和主動式組件會藉由一連串的製程步驟被形成在該半導體晶圓的表面上方，該等製程步驟包含：摻雜、沉積、光微影術、蝕刻、以及平坦化。摻雜會藉由下面的技術將雜質引入至半導體材料之中，例如：離子植入或是熱擴散。摻雜製程會修正主動式裝置中半導體材料的導電性，將該半導體材料轉換成絕緣體、導體，或是響應於電場或基礎電流來動態改變半導體材料傳導性。電晶體含有不同類型和摻雜程度的多個區域，它們會在必要時被排列成用以在施加該電場或基礎電流時讓該電晶體可以提高或限制電流的流動。
主動式組件和被動式組件係由具有不同電氣特性的多層材料所構成。該等層能夠藉由各式各樣的沉積技術來形成，該等沉積技術部分取決於要被沉積的材料的類型。舉例來說，薄膜沉積可能包含：化學氣相沉積(Chemical Vapor Deposition，CVD)製程、物理氣相沉積(Physical Vapor Deposition，PVD)製程、電解質電鍍製程、以及無電極電鍍製程。每一層通常都會被圖樣化，以便形成主動式組件、被動式組件、或是組件之間的電連接線的一部分。
該等層能夠利用光微影術被圖樣化，其涉及在要被圖樣化的層的上方沉積光敏材料，舉例來說，光阻。一圖樣會利用光從一光罩處被轉印至該光阻。該光阻圖樣中受到光作用的部分會利用溶劑移除，從而露出下方層之中要被圖樣化的部分。該光阻中的剩餘部分會被移除，從而留下一己圖樣化層。或者，某些類型的材料會利用無電極電鍍以及電解質電鍍之類的技術將該材料直接沉積至由先前沉積及/或蝕刻製程所形成的區域或空隙(void)之中而被圖樣化。
在一既有圖樣的上方沉積一薄膜材料可能會擴大下方圖樣並且產生一不均勻平坦的表面。生產較小且更密集封裝的主動式組件和被動式組件需要用到均勻平坦的表面。平坦化作用可用來從晶圓的表面處移除材料，並且產生一均勻平坦的表面。平坦化作用涉及利用一研磨墊來研磨晶圓的表面。有磨蝕作用的材料以及腐蝕性的化學藥劑會在研磨期間被加到該晶圓的表面。由化學藥劑的磨蝕性作用及腐蝕性作用所組成的組合式機械作用會移除任何不規律的拓樸形狀，從而產生一均勻平坦的表面。
後端製造係指將已完成的晶圓切割或單體化裁切成個別晶粒，並且接著封裝該晶粒，以達結構性支撐及環境隔離的效果。為單體化裁切該晶粒，晶圓會沿著該晶圓中被稱為切割道(saw street)或切割線(scribe)的非功能性區域被刻痕並且折斷。該晶圓會利用雷射切割工具或鋸片來進行單體化裁切。經過單體化裁切之後，個別晶粒便會被鑲嵌在包含接針或接觸觸墊的封裝基板上，以便和其它系統組件進行互連。被形成在該半導體晶粒上方的接觸觸墊接著會被連接至該封裝裡面的接觸觸墊。該等電連接線可利用焊料凸塊、短柱凸塊、導電膏、或是焊線來製成。一囊封劑或是其它模造材料會被沉積在該封裝的上方，用以提供物理性支撐和電隔離。接著，該已完成的封裝便會被插入一電氣系統之中並且讓其它系統組件可取用該半導體裝置的功能。
圖1圖解一電子裝置50，其具有一晶片載體基板或是印刷電路板(Printed Circuit Board，PCB)52，在其表面上鑲嵌著複數個半導體封裝。電子裝置50可能具有一類型的半導體封裝或是多種類型的半導體封裝，端視應用而定。為達解釋的目的，圖1中顯示不同類型的半導體封裝。
電子裝置50可能係一單機型系統，其會使用該等半導體封裝來實施一或多項電功能。或者，電子裝置50可能係一較大型系統中的一子組件。舉例來說，電子裝置50可能係一蜂巢式電話、一個人數位助理(Personal Digital Assistant，PDA)、一數位錄像機(Digital Video Camera，DVC)、或是其它電子通訊裝置的一部分。或者，電子裝置50可能係一圖形卡、一網路介面卡、或是能夠被插入一電腦之中的其它訊號處理卡。該半導體封裝可能包含：微處理器、記憶體、特定應用積體電路(Application Specific Integrated Circuits，ASIC)、邏輯電路、類比電路、RF電路、離散式裝置、或是其它半導體晶粒或電組件。此等產品要被市場接受，微型化以及減輕重量很重要。半導體裝置之間的距離必須縮短，以便達到更高的密度。
在圖1中，PCB 52提供一通用基板，用以結構性支撐及電互連被鑲嵌在該PCB之上的半導體封裝。多條導體訊號線路54會利用下面製程被形成在PCB 52的一表面上方或是多層裡面：蒸發製程、電解質電鍍製程、無電極電鍍製程、網印製程、或是其它合宜的金屬沉積製程。訊號線路54會在該等半導體封裝、被鑲嵌的組件、以及其它外部系統組件中的每一者之間提供電通訊。線路54還會提供連接至每一個該等半導體封裝的電力連接線及接地連接線。
於某些實施例中，一半導體裝置會有兩個封裝層。第一層封裝係一種用於以機械方式及電氣方式將該半導體晶粒附接至一中間載板的技術。第二層封裝則涉及以機械方式及電氣方式將該中間載板附接至該PCB。於其它實施例中，一半導體裝置可能僅有該第一層封裝，其中，該晶粒會以機械方式及電氣方式直接被鑲嵌至該PCB。
為達解釋的目的，圖中在PCB 52之上顯示數種類型的第一層封裝，其包含焊線封裝56以及覆晶58。除此之外，圖中還顯示被鑲嵌在PCB 52之上的數種類型第二層封裝，其包含：球柵陣列(Ball Grid Array，BGA)60；凸塊晶片載板(Bump Chip Carrier，BCC)62；雙直列封裝(Dual In-line Package，DIP)64；平台格柵陣列(Land Grid Array，LGA)66；多晶片模組(Multi-Chip Module，MCM)68；方形扁平無引線封裝(Quad Flat Non-leaded package，QFN)70；以及方形扁平封裝72。端視系統需求而定，被配置成由具有第一層封裝樣式和第二層封裝樣式之任何組合以及其它電子組件所組成的任何半導體封裝組合皆能夠被連接至PCB 52。於某些實施例中，電子裝置50包含單一附接半導體封裝；而其它實施例則可能要求多個互連封裝。藉由在單一基板上方組合一或多個半導體封裝，製造商便能夠將事先製造的組件併入電子裝置和系統之中。因為該等半導體封裝包含精密的功能，所以，電子裝置能夠使用較便宜的組件及有效率的製程來製造。所產生的裝置比較不可能失效而且製造價格較低廉，從而會降低消費者的成本。
圖2a至2c所示的係示範性半導體封裝。圖2a所示的係被鑲嵌在PCB 52之上的DIP 64的進一步細節。半導體晶粒74包含一含有類比電路或數位電路的主動區，該等類比電路或數位電路會被施行為被形成在該晶粒裡面的主動式裝置、被動式裝置、傳導層、以及介電層，並且會根據該晶粒的電氣設計來進行電互連。舉例來說，該電路可能包含被形成在半導體晶粒74的該主動區裡面的一或多個電晶體、二極體、電感器、電容器、電阻器、以及其它電路元件。接觸觸墊76係一或多層導體材料(例如鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、或是銀(Ag))，並且會被電連接至形成在半導體晶粒74裡面的電路元件。在DIP 64的組裝期間，半導體晶粒74會利用一金-矽共熔合金層或是膠黏材料(例如熱環氧樹脂或環氧樹脂)被鑲嵌在一中間載板78上。該封裝主體包含一絕緣封裝材料，例如聚合物或是陶瓷。導體引線80以及焊線82會在半導體晶粒74與PCB 52之間提供電互連。囊封劑84會被沉積在該封裝的上方，防止濕氣和粒子進入該封裝並污染晶粒74或焊線82，以便達到環境保護的目的。
圖2b所示的係被鑲嵌在PCB 52之上的BCC 62的進一步細節。半導體晶粒88會利用底層填充材料或環氧樹脂膠黏材料92會被鑲嵌在載板90的上方。焊線94會在接觸觸墊96與98之間提供第一層封裝互連。模造化合物或囊封劑100會被沉積在半導體晶粒88和焊線94的上方，用以為該裝置提供物理性支撐以及電隔離效果。多個接觸觸墊102會利用合宜的金屬沉積製程(例如電解質電鍍或無電極電鍍)被形成在PCB 52的一表面上方，用以防止氧化。接觸觸墊102會被電連接至PCB 52中的一或多條導體訊號線路54。多個凸塊104會被形成在BCC 62的接觸觸墊98和PCB 52的接觸觸墊102之間。
在圖2c中，半導體晶粒58會利用覆晶樣式的第一層封裝以面朝下的方式被鑲嵌至中間載板106。半導體晶粒58的主動區108含有類比電路或數位電路，該等類比電路或數位電路會被施行為根據該晶粒的電氣設計所形成的主動式裝置、被動式裝置、傳導層、以及介電層。舉例來說，該電路可能包含被形成在主動區108裡面的一或多個電晶體、二極體、電感器、電容器、電阻器、以及其它電路元件。半導體晶粒58會經由多個凸塊110以電氣方式及機械方式被連接至載板106。
BGA 60會以利用多個凸塊112的BGA樣式第二層封裝以電氣方式及機械方式被連接至PCB 52。半導體晶粒58會經由凸塊110、訊號線114、以及凸塊112被電連接至PCB 52中的導體訊號線路54。一模造化合物或囊封劑116會被沉積在半導體晶粒58和載板106的上方，用以為該裝置提供物理性支撐以及電隔離效果。該覆晶半導體裝置會從半導體晶粒58上的該等主動式裝置處至PCB 52上的傳導軌提供一條短的電傳導路徑，以便縮短訊號傳播距離、降低電容、並且改善整體電路效能。於另一實施例中，該半導體晶粒58會利用覆晶樣式的第一層封裝以機械方式及電氣方式直接被連接至PCB 52，而沒有中間載板106。
圖3a顯示一半導體晶圓120，其具有一基板材料122，例如，矽、鍺、砷化鎵、磷化銦、或是碳化矽，用以達到結構性支撐的目的。如上面所述，複數個半導體晶粒或組件124會被形成在晶圓120之上，藉由切割道126來分離。
圖3b所示的係半導體晶圓120的一部分的剖視圖。每一個半導體晶粒124都有一背表面128與一含有類比電路或數位電路的主動表面130，該等類比電路或數位電路會被施行為被形成在該晶粒裡面的主動式裝置、被動式裝置、傳導層、以及介電層，並且會根據該晶粒的電氣設計來進行電互連。舉例來說，該電路可能包含被形成在主動表面130裡面的一或多個電晶體、二極體、以及其它電路元件，用以施行類比電路或數位電路，例如，數位訊號處理器(Digital Signal Processor，DSP)、ASIC、記憶體、或是其它訊號處理電路。半導體晶粒124可能還含有用於RF訊號處理的整合被動元件(IPD)，例如，電感器、電容器、以及電阻器。於其中一實施例中，半導體晶粒124係一覆晶型半導體晶粒。
一導電層132會使用PVD製程、CVD製程、電解質電鍍製程、無電極電鍍製程、或是其它合宜的金屬沉積製程被形成在主動表面130上方。傳導層132可能係由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。傳導層132的操作如同被電連接至主動表面130上之該等電路的接觸觸墊。多個凸塊134會被形成在接觸觸墊132上。或者，多個微凸塊或短柱凸塊會被形成在接觸觸墊132上。
在圖3c中，半導體晶圓120會利用鋸片或雷射切割工具136經由切割道(saw street)126被單體化裁切成個別的半導體晶粒124。
圖4a至4s配合圖1以及2a至2c來圖解一用以形成軌道上接合(Bond-On-Trace，BOL)或引線上接合(Bond-On-Lead，BOL)互連以便在FO-WLCSP中鑲嵌半導體晶粒的製程。在圖4a中，一基板或載板140含有暫時性或犧牲性基礎材料，例如，矽、聚合物、氧化鈹、或是其它合宜的低成本剛性材料，用以達到結構性支撐的目的。一介面層或雙面膠142會被形成在載板140的上方，作為一暫時性黏著接合膜或蝕刻阻止層。
在圖4b中，一導電層144會使用PVD、CVD、電解質電鍍、無電極電鍍製程、或是其它合宜的金屬沉積製程被形成在介面層142與載板140的上方。傳導層144可能係由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。傳導層144含有接觸觸墊144a與144h以及訊號軌道線或引線144b、144c、144d、144e、144f、以及144g。圖4c所示的係具有接觸觸墊144a與144h以及訊號軌道線144b至144g的介面層142的一部分的俯視圖。接觸觸墊144a和訊號軌道線144b為電氣連續，而接觸觸墊144h和訊號軌道線144g為電氣連續。於其中一實施例中，接觸觸墊144a與144h的寬度或直徑D為150至250微米(μm)，而訊號軌道線144b至144g的寬度為60至90μm。接觸觸墊144a與144h以及訊號軌道線144b至144g會被緊密地放置在一起而偏移距離為一細微間距。於其中一實施例中，軌道線144b至144g的間距P為約80至110μm。用於傳導層144的額外接觸觸墊與軌道線可能會被形成在該等橫向方向與垂直方向中。軌道線144b至144g具有一末端部分或尖端146，其會終止在一被指定為對齊半導體晶粒124之凸塊134的位置處。用於傳導層144的額外接觸觸墊與軌道線可能會被形成在該等橫向方向與垂直方向中。
在圖4d中，圖3a至3c的半導體晶粒124會利用一拾取與放置操作被放置在介面層142上，主動表面130會被配向成朝向載板140。明確地說，凸塊134會對齊訊號軌道線144b至144g的尖端146。訊號軌道線144b至144g的尖端146會在晶粒鑲嵌期間提供對齊標記。半導體晶粒124的凸塊134會以冶金的方式及電氣方式被連接至訊號軌道線144b至144g的尖端146，成為一BOT或BOL互連線。圖4e所示的係以冶金的方式及電氣方式被連接至訊號軌道線144b至144g之尖端146的半導體晶粒124的凸塊134的俯視圖。凸塊134的直徑大於軌道線144b至144g的寬度。當凸塊134直接被接合至軌道線時，軌道線144b至144g的間距P會縮減，有別於習知的專屬凸塊觸墊。
於另一實施例中，一導電層148會使用PVD、CVD、電解質電鍍、無電極電鍍製程、或是其它合宜的金屬沉積製程被形成在介面層142與載板140的上方，如圖4f中所示。傳導層148可能係由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。傳導層148含有訊號軌道線或引線148a、148b、148c、148d、148e、148f以及接觸觸墊148g、148h、148i、148j、148k以及148l。圖4g所示的係具有訊號軌道線148a至148f以及偏移接觸觸墊148g至148l的介面層142的一部分的俯視圖。接觸觸墊148g至148l分別和訊號軌道線148a至148f為電氣連續。於其中一實施例中，訊號軌道線148a至148f的寬度W為60至90μm，而接觸觸墊148g至148l的寬度或直徑D為150至250μm。訊號軌道線148a至148f以及接觸觸墊148g至148l會被緊密地放置在一起而偏移距離為一細微間距。於其中一實施例中，軌道線148a至148f的間距P為約80至110μm。軌道線148a至148f具有一末端部分或尖端150，其會終止在一被指定為對齊半導體晶粒124之凸塊134的位置處。用於傳導層148的額外接觸觸墊與軌道線可能會被形成在該等橫向方向與垂直方向中。
一非必要的遮罩層151會被形成在訊號軌道線148a至148f的上方，如圖4h中所示。複數個開口153會被形成在軌道線148a至148f之尖端150上方的遮罩層151之中。
在圖4i中，圖3a至3c的半導體晶粒124會利用一拾取與放置操作被放置在介面層142上，被配向成朝向載板140。明確地說，凸塊134會對齊訊號軌道線148a至148f的尖端150。訊號軌道線148a至148f的尖端150會在晶粒鑲嵌期間提供對齊標記。半導體晶粒124的凸塊134會以冶金的方式及電氣方式被連接至訊號軌道線148a至148f的尖端150，成為BOT或BOL。
圖4j所示的係以冶金的方式及電氣方式被連接至訊號軌道線148a至148f之尖端150的半導體晶粒124的凸塊134的俯視圖。凸塊134的直徑大於軌道線148a至148f的寬度。當凸塊134直接被接合至軌道線時，軌道線148a至148f的間距P會縮減，有別於習知的專屬凸塊觸墊。圖4k所示的係經由遮罩層151的開口153以冶金的方式及電氣方式被連接至訊號軌道線148a至148f之尖端150的半導體晶粒124的凸塊134。
圖41所示的係以冶金的方式及電氣方式被連接至訊號軌道線148a至148f的一中間部分的凸塊134。也就是，訊號軌道線148a至148f會在兩個方向中延伸超出凸塊134。圖4m所示的係經由遮罩層151的開口153以冶金的方式及電氣方式被連接至訊號軌道線148a至148f的該中間部分的半導體晶粒124的凸塊134。
接續圖4e或圖4j，一囊封劑或模造化合物152會利用焊膏印刷(paste printing)塗敷機、壓縮模造(compressive molding)塗敷機、轉印模造(transfer molding)塗敷機、液體囊封劑模造塗敷機、真空層疊塗敷機、旋塗塗敷機、或是其它合宜的塗敷機被沉積在半導體晶粒124、載板140、以及傳導層144的上方，如圖4n中所示。囊封劑152可能係聚合物復合材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯、或是具有適當填充劑的聚合物。囊封劑152係非導體並且會為該半導體裝置提供環境保護，避免受到外部元素與污染物破壞。傳導層144可能係可潤濕的材料，例如，助焊材料，以便在囊封期間將半導體晶粒124牢牢地固定在正確的地方並且減少偏移。
在圖4o中，載板140與介面層142會藉由下面方式被移除以便露出半導體晶粒124、傳導層144、以及囊封劑152：化學性蝕刻、機械性剝離、CMP、機械性研磨、熱烘烤、UV光、雷射掃描、或是濕式剝除。
在圖4p中，一焊料遮罩或絕緣層154會被形成在半導體晶粒124、傳導層144、以及囊封劑152的上方。一部分的焊料遮罩154會藉由一蝕刻製程被移除，用以露出傳導層144，以便達到額外電互連的效果。
在圖4q中，一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程、或是網印製程被沉積在傳導層144a與144h的上方。該凸塊材料可能係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及它們的組合，其會有一非必要的助熔溶液。舉例來說，該凸塊材料可能是Sn/Pb共熔合金、高鉛焊料、或是無鉛焊料。該凸塊材料會利用合宜的附著或接合製程被接合至傳導層144。於其中一實施例中，該凸塊材料會藉由將該材料加熱至其熔點以上而被回焊，用以形成球狀的丸體或凸塊156。於某些應用中，凸塊156會被二次回焊，以便改善和傳導層144的電接觸效果。一凸塊下層金屬(Under Bump Metallization，UBM)會被形成在凸塊156的下方。該等凸塊還會被壓縮接合至傳導層144。凸塊156代表能夠被形成在傳導層144上方的其中一種類型的互連結構。該互連結構亦能夠使用接合線、短柱凸塊、微凸塊、或是其它電互連。
於另一實施例中，一增進互連結構158會被形成在半導體晶粒124、傳導層144、以及囊封劑152的上方，如圖4r中所示。該增進互連結構158包含一導電層或重新分配層(ReDistribution Layer，RDL)160，其係利用圖樣化與金屬沉積製程所形成，例如：濺鍍、電解質電鍍、以及無電極電鍍。傳導層160可能係由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。傳導層160的一部分會被電連接至傳導層144。傳導層160的其它部分可能具有共同電性或是為電隔離，端視半導體晶粒124的設計與功能而定。
一絕緣層或鈍化層162會利用下面方法被形成在傳導層160附近以達電隔離的目的：PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化。該絕緣層162含有由下面所製成的一或多層：二氧化矽(SiO2)、氮化矽(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、三氧化二鋁(Al2O3)、或是具有雷同絕緣特性及結構性特性的其它材料。一部分的絕緣層162會藉由一蝕刻製程被移除，用以露出傳導層160，以便達到額外電互連的效果。
在圖4s中，一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程、或是網印製程被沉積在增進互連結構158的上方並且被電連接至傳導層160、144a、以及144g的外露部分。該凸塊材料可能係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及它們的組合，其會有一非必要的助熔溶液。舉例來說，該凸塊材料可能是Sn/Pb共熔合金、高鉛焊料、或是無鉛焊料。該凸塊材料會利用合宜的附著或接合製程被接合至傳導層144與160。於其中一實施例中，該凸塊材料會藉由將該材料加熱至其熔點以上而被回焊，用以形成球狀的丸體或凸塊164。於某些應用中，凸塊164會被二次回焊，以便改善和傳導層144與160的電接觸效果。一UBM會被形成在凸塊164的下方。該等凸塊還會被壓縮接合至傳導層144與160。凸塊164代表能夠被形成在傳導層144與160上方的其中一種類型的互連結構。該互連結構亦能夠使用接合線、短柱凸塊、微凸塊、或是其它電互連。
接續圖4q或4s，半導體晶粒124會利用鋸片或雷射切割工具166被單體化裁切穿過囊封劑152與絕緣層154(或是增進互連結構158)成為個別的FO-WLCSP 168。圖5所示的係單體化裁切之後的圖4q的FO-WLCSP 168。半導體晶粒124會經由接觸觸墊132與凸塊134被電連接至傳導層144與凸塊156。凸塊134會被接合至傳導層144b至144g的尖端146成為BOT或BOL，以達細微互連間距以及高I/O數的目的。
圖6所示的係FO-WLCSP 170的一實施例，雷同於圖5，當其為晶圓形式時會有多根傳導柱172被形成在接觸觸墊132上，參見圖3a至3c。傳導柱172含有不可崩塌或不可熔化的材料，例如，Au、Cu、Ni、高鉛焊料、或是鉛錫合金。一傳導層174(例如，Ni)會被形成在傳導柱172上。多個凸塊176會被形成在傳導層174上。凸塊176含有不可崩塌或不可熔化的材料，例如，Sn；無鉛合金；Sn-Ag合金；Sn-Ag-Cu合金；Sn-Ag-銦(In)合金；共熔合金焊料；含有Ag、Cu、Pb的其它錫合金；或是其它比較低溫的熔融焊料。
具有傳導柱172和凸塊176的半導體晶粒124會藉由施加一回焊溫度與壓力而被接合至傳導層144b至144g。傳導柱172在施加壓力與回焊溫度下並不會變形或熔化並且會保持它們的外形與形狀。據此，傳導柱172的尺寸會經過設計，用以在半導體晶粒124的主動表面130及傳導層144之間提供一均衡距離(standoff distance)。
圖7所示的係FO-WLCSP 180的一實施例，雷同於圖5，在鑲嵌半導體晶粒124之前一絕緣層182會先被形成在傳導層144上。該絕緣層182含有由下面所製成的一或多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是具有雷同絕緣特性及結構性特性的其它材料。絕緣層182可能係一無流動底層填充材料(no-flow underfill material)。
於另一實施例中，接續圖4c，一遮罩層184會被形成在載板140、介面層142、接觸觸墊144a與144h、以及軌道線144b至144g的上方，如圖8a中所示。若凸塊高度15μm，遮罩層184的厚度則約85μm。複數個開口186會被形成在軌道線144b至144g之尖端146上方的遮罩層184之中。圖8b所示的係被形成在載板140上方的遮罩層184的剖視圖，有多個開口186會露出尖端146。半導體晶粒124會藉由受到遮罩層184侷限之凸塊134的回焊而被鑲嵌至軌道線144b至144g，雷同於圖4h。囊封劑152會被沉積在半導體晶粒124與載板140的上方，雷同於圖4k。載板140會被移除而絕緣層154會被形成在半導體晶粒124與囊封劑152的上方，雷同於圖4o至4p。一部分的絕緣層154會被移除而多個凸塊156會被形成在接觸觸墊144a與144g的上方，雷同於圖4p至4q。
圖8c所示的係具有遮罩層184的FO-WLCSP 188。一間隙190會存在於半導體晶粒124與遮罩層184之間，以便對該半導體晶粒進行鑄模底層填充(Mold UnderFill，MUF)。於其中一實施例中，間隙190為約70至100μm。一MUF或囊封劑材料192會被沉積穿過間隙190圍繞半導體晶粒124，其包含該晶粒的上方與下方。MUF 192會從一貯存器處被抽吸至一滴塗針。MUF 192會在壓力作用下從該滴塗針處經由間隙190被注入在半導體晶粒124的下方及凸塊134的附近。真空會幫助吸取MUF 192，有助於達到均勻的分佈。MUF 192可能係聚合物復合材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯、或是具有適當填充劑的聚合物。MUF 192係非導體並且會為該半導體裝置提供環境保護，避免受到外部元素與污染物破壞。
雖然本文已經詳細解釋過本發明的一或多個實施例；不過，熟練的技術人士便會瞭解，可以對該些實施例進行修正與改變，其並不會脫離後面申請專利範圍中所提出的本發明的範疇。
50．．．電子裝置
52．．．印刷電路板(PCB)
54．．．線路
56．．．焊線封裝
58．．．覆晶
60．．．球柵陣列(BGA)
62．．．凸塊晶片載板(BCC)
64．．．雙直列封裝(DIP)
66．．．平台格柵陣列(LGA)
68．．．多晶片模組(MCM)
70．．．方形扁平無引線封裝(QFN)
72．．．方形扁平封裝
74．．．半導體晶粒
76．．．接觸觸墊
78．．．中間載板
80．．．導體引線
82．．．焊線
84．．．囊封劑
88．．．半導體晶粒
90．．．載板
92．．．底層填充材料或環氧樹脂膠黏材料
94．．．焊線
96．．．接觸觸墊
98．．．接觸觸墊
100．．．模造化合物或囊封劑
102．．．接觸觸墊
104．．．凸塊
106．．．中間載板
108．．．主動區
110．．．凸塊
112．．．凸塊
114．．．訊號線
116．．．模造化合物或囊封劑
120．．．半導體晶圓
122．．．基板材料
124．．．半導體晶粒或組件
126．．．切割道
128．．．背表面
130．．．主動表面
132．．．接觸觸墊
134．．．凸塊
136．．．鋸片或雷射切割工具
140．．．基板或載板
142．．．介面層或雙面膠
144a．．．接觸觸墊
144b．．．訊號軌道線或引線
144c．．．訊號軌道線或引線
144d．．．訊號軌道線或引線
144e．．．訊號軌道線或引線
144f．．．訊號軌道線或引線
144g．．．訊號軌道線或引線
144h．．．接觸觸墊
146．．．末端部分或尖端
148a．．．訊號軌道線或引線
148b．．．訊號軌道線或引線
148c．．．訊號軌道線或引線
148d．．．訊號軌道線或引線
148e．．．訊號軌道線或引線
148f．．．訊號軌道線或引線
148g．．．接觸觸墊
148h．．．接觸觸墊
148i．．．接觸觸墊
148j．．．接觸觸墊
148k．．．接觸觸墊
148l．．．接觸觸墊
150．．．末端部分或尖端
151．．．遮罩層
152．．．囊封劑或模造化合物
153．．．開口
154．．．焊料遮罩或絕緣層
156．．．丸體或凸塊
158．．．增進互連結構
160．．．導電層或重新分配層
162．．．絕緣層或鈍化層
164．．．丸體或凸塊
166．．．鋸片或雷射切割工具
168．．．扇出晶圓級晶片規模封裝(FO-WLCSP)
170．．．扇出晶圓級晶片規模封裝(FO-WLCSP)
172．．．傳導柱
174．．．傳導層
176．．．凸塊
180．．．扇出晶圓級晶片規模封裝(FO-WLCSP)
182．．．絕緣層
184．．．遮罩層
186．．．開口
188．．．扇出晶圓級晶片規模封裝(FO-WLCSP)
190．．．間隙
192．．．鑄模底層填充(MUF)或囊封劑材料
圖1所示的係一印刷電路板，在其表面上鑲嵌著不同類型的封裝；
圖2a至2c所示的係被鑲嵌至該印刷電路板的代表性半導體封裝的進一步細節；
圖3a至3c所示的係一半導體晶圓，其具有藉由切割道來分離的複數個半導體晶粒；
圖4a至4s所示的係一用以形成BOL互連以便在FO-WLCSP中鑲嵌半導體晶粒的製程；
圖5所示的係被鑲嵌至該BOL互連的半導體晶粒；
圖6所示的係被形成在該半導體晶粒之該等接觸觸墊上的傳導柱；
圖7所示的係被沉積在該BOL互連上的無流動底層填充材料；以及
圖8a至8c所示的係利用一遮罩層被鑲嵌至該BOL互連的半導體晶粒。
124．．．半導體晶粒或組件
130．．．主動表面
132．．．接觸觸墊
134．．．凸塊
144a．．．接觸觸墊
144b．．．訊號軌道線或引線
144c．．．訊號軌道線或引線
144d．．．訊號軌道線或引線
144e．．．訊號軌道線或引線
144f．．．訊號軌道線或引線
144g．．．訊號軌道線或引線
144h．．．接觸觸墊
152．．．囊封劑或模造化合物
154．．．焊料遮罩或絕緣層
156．．．丸體或凸塊
160．．．導電層或重新分配層
168．．．扇出晶圓級晶片規模封裝(FO-WLCSP)

Claims (10)

  1. 一種製造半導體裝置的方法，其包括：提供一載板；在該載板上形成一包含複數條相鄰的軌道線被放置在一起的傳導層，在該等相鄰的軌道線之間具有80至110μm的間距；提供一半導體晶粒；在該半導體晶粒上形成複數個第一凸塊；將該半導體晶粒鑲嵌至該傳導層，讓該等第一凸塊直接被接合至該等相鄰的軌道線的每一者的一終止端；在該半導體晶粒與傳導層上沉積一囊封劑；移除該載板以露出該等軌道線；以及在該囊封劑與半導體晶粒上形成一互連結構並且電性地連接至該等露出的軌道線。
  2. 如申請專利範圍第1項的方法，其進一步包含利用一鑄模底層填充製程將該囊封劑沉積在該半導體晶粒的下方。
  3. 如申請專利範圍第1項的方法，其中，形成該互連結構包含：在該囊封劑與半導體晶粒的上方形成一絕緣層；以及在該傳導層的上方形成複數個第二凸塊。
  4. 如申請專利範圍第1項的方法，其進一步包含在鑲嵌該半導體晶粒之前先在該傳導層上方形成一絕緣層。
  5. 如申請專利範圍第4項的方法，其中，該絕緣層包含 一無流動底層填充材料。
  6. 如申請專利範圍第1項的方法，其進一步包含：形成複數根傳導柱在該半導體的上方；以及形成該等第一凸塊在該等傳導柱的上方。
  7. 一種製造半導體裝置的方法，其包括：提供一載板；形成包含複數條相鄰的軌道線被一起放置在該載板上的一傳導層；提供一半導體晶粒，其具有被形成在該半導體晶粒之一表面上的複數個第一凸塊；將該半導體晶粒鑲嵌至該傳導層，讓該等第一凸塊直接被接合至該等相鄰的軌道線的每一者；移除該載板以露出該等軌道線；以及形成一互連結構在該半導體晶粒和該等被露出的軌道線的上方。
  8. 如申請專利範圍第7項的方法，其進一步包含將該半導體晶粒鑲嵌至該傳導層，讓該等第一凸塊直接被接合至該等相鄰的軌道線的每一者的一末端部分。
  9. 如申請專利範圍第7項的方法，其中，該等第一凸塊的一直徑大於該等軌道線的一寬度。
  10. 如申請專利範圍第7項的方法，其進一步包含：在該傳導層上方形成一遮罩層；以及在該等軌道線的上方的該遮罩層中形成複數個開口。
TW100130052A 2010-09-13 2011-08-23 半導體裝置以及形成引線上接合互連用於鑲嵌半導體晶粒在扇出晶圓級晶片規模封裝中之方法 TWI581345B (zh)

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Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8216930B2 (en) 2006-12-14 2012-07-10 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
US8129841B2 (en) 2006-12-14 2012-03-06 Stats Chippac, Ltd. Solder joint flip chip interconnection
US9029196B2 (en) 2003-11-10 2015-05-12 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US7659633B2 (en) * 2004-11-10 2010-02-09 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
US8026128B2 (en) 2004-11-10 2011-09-27 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
KR101286379B1 (ko) 2003-11-10 2013-07-15 스태츠 칩팩, 엘티디. 범프-온-리드 플립 칩 인터커넥션
USRE47600E1 (en) 2003-11-10 2019-09-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US8574959B2 (en) 2003-11-10 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
WO2006105015A2 (en) 2005-03-25 2006-10-05 Stats Chippac Ltd. Flip chip interconnection having narrow interconnection sites on the substrate
US8841779B2 (en) 2005-03-25 2014-09-23 Stats Chippac, Ltd. Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate
US8441127B2 (en) * 2011-06-29 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace structures with wide and narrow portions
US8598715B2 (en) * 2011-12-02 2013-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace structures in packaging
JP2013236039A (ja) * 2012-05-11 2013-11-21 Renesas Electronics Corp 半導体装置
TWI471898B (zh) * 2012-06-19 2015-02-01 Chipbond Technology Corp 半導體製程、半導體結構及其封裝構造
KR101965127B1 (ko) 2012-10-29 2019-04-04 삼성전자 주식회사 반도체 패키지 및 그 제조 방법
TWI515808B (zh) * 2013-04-25 2016-01-01 南茂科技股份有限公司 晶片封裝結構的製作方法
US9524958B2 (en) * 2013-06-27 2016-12-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of individual die bonding followed by simultaneous multiple die thermal compression bonding
KR102110332B1 (ko) * 2013-09-27 2020-05-14 르네사스 일렉트로닉스 가부시키가이샤 반도체 장치 및 그 제조 방법
US9721922B2 (en) 2013-12-23 2017-08-01 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of forming fine pitch RDL over semiconductor die in fan-out package
US20150187719A1 (en) 2013-12-30 2015-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Trace Design for Bump-on-Trace (BOT) Assembly
US9230936B2 (en) * 2014-03-04 2016-01-05 Qualcomm Incorporated Integrated device comprising high density interconnects and redistribution layers
US9806046B2 (en) * 2014-03-13 2017-10-31 Taiwan Semiconductor Manufacturing Co., Ltd Semiconductor device structure and manufacturing method
KR102274742B1 (ko) * 2014-10-06 2021-07-07 삼성전자주식회사 패키지 온 패키지와 이를 포함하는 컴퓨팅 장치
JP6019367B2 (ja) * 2015-01-13 2016-11-02 株式会社野田スクリーン 半導体装置
US20160218021A1 (en) * 2015-01-27 2016-07-28 Advanced Semiconductor Engineering, Inc. Semiconductor package and method of manufacturing the same
TWI607327B (zh) * 2015-12-25 2017-12-01 矽創電子股份有限公司 半導體元件
US20180005972A1 (en) * 2016-07-01 2018-01-04 Intel Corporation Interface structures for packaged circuitry and method of providing same
TWI649839B (zh) * 2017-03-15 2019-02-01 矽品精密工業股份有限公司 電子封裝件及其基板構造
US9947634B1 (en) * 2017-06-13 2018-04-17 Northrop Grumman Systems Corporation Robust mezzanine BGA connector
CN109216293A (zh) * 2017-07-03 2019-01-15 葛兰菲安全有限公司 芯片和电子电路的粘接结构和粘接方法
CN111627867A (zh) * 2019-02-28 2020-09-04 富泰华工业（深圳）有限公司 芯片封装结构及其制作方法
KR102631356B1 (ko) 2019-11-14 2024-01-31 삼성전자주식회사 반도체 패키지
US11437526B2 (en) * 2019-12-09 2022-09-06 Amkor Technology Singapore Holding Pte. Ltd. Electronic devices having a sensor and a translucent mold compound and methods of manufacturing electronic devices
CN111048485B (zh) * 2019-12-16 2021-07-27 米尔芯星(深圳)信息科技有限公司 一种半导体芯片器件
GB2603216B (en) 2021-01-29 2024-06-05 Cirrus Logic Int Semiconductor Ltd A chip scale package
CN117203743A (zh) 2021-03-15 2023-12-08 纳欧克斯影像有限公司 用于制造电子发射体阵列芯片的硅管芯叠置体的系统和方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200924137A (en) * 2007-11-19 2009-06-01 Subtron Technology Co Ltd Chip package carrier, chip package and method for fabricating the same
TW201005894A (en) * 2008-07-31 2010-02-01 Powertech Technology Inc Pillar-to-pillar flip-chip assembly
US20100164097A1 (en) * 2008-12-31 2010-07-01 Stats Chippac, Ltd. Semiconductor Device and Method of Confining Conductive Bump Material During Reflow with Solder Mask Patch

Family Cites Families (116)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04355933A (ja) 1991-02-07 1992-12-09 Nitto Denko Corp フリツプチツプの実装構造
US5250843A (en) 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
JP2678958B2 (ja) 1992-03-02 1997-11-19 カシオ計算機株式会社 フィルム配線基板およびその製造方法
US5314651A (en) 1992-05-29 1994-05-24 Texas Instruments Incorporated Fine-grain pyroelectric detector material and method
US5353498A (en) 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5386624A (en) 1993-07-06 1995-02-07 Motorola, Inc. Method for underencapsulating components on circuit supporting substrates
US5508561A (en) 1993-11-15 1996-04-16 Nec Corporation Apparatus for forming a double-bump structure used for flip-chip mounting
EP0751561A4 (en) 1994-03-18 1997-05-07 Hitachi Chemical Co Ltd PROCESS FOR MANUFACTURING SEMICONDUCTOR PACKAGES AND SEMICONDUCTOR PACKAGES
US5519580A (en) 1994-09-09 1996-05-21 Intel Corporation Method of controlling solder ball size of BGA IC components
JP3353508B2 (ja) 1994-12-20 2002-12-03 ソニー株式会社 プリント配線板とこれを用いた電子装置
US5650595A (en) 1995-05-25 1997-07-22 International Business Machines Corporation Electronic module with multiple solder dams in soldermask window
US5710071A (en) 1995-12-04 1998-01-20 Motorola, Inc. Process for underfilling a flip-chip semiconductor device
KR0182073B1 (ko) 1995-12-22 1999-03-20 황인길 반도체 칩 스케일 반도체 패키지 및 그 제조방법
JP3645378B2 (ja) 1996-01-19 2005-05-11 株式会社半導体エネルギー研究所 半導体装置の作製方法
US5889326A (en) 1996-02-27 1999-03-30 Nec Corporation Structure for bonding semiconductor device to substrate
JPH09260552A (ja) 1996-03-22 1997-10-03 Nec Corp 半導体チップの実装構造
KR100216839B1 (ko) 1996-04-01 1999-09-01 김규현 Bga 반도체 패키지의 솔더 볼 랜드 메탈 구조
US5841193A (en) 1996-05-20 1998-11-24 Epic Technologies, Inc. Single chip modules, repairable multichip modules, and methods of fabrication thereof
JP3500032B2 (ja) 1997-03-13 2004-02-23 日本特殊陶業株式会社 配線基板及びその製造方法
JP3346263B2 (ja) 1997-04-11 2002-11-18 イビデン株式会社 プリント配線板及びその製造方法
EP0993039B1 (en) 1997-06-26 2006-08-30 Hitachi Chemical Company, Ltd. Substrate for mounting semiconductor chips
JPH1126919A (ja) 1997-06-30 1999-01-29 Fuji Photo Film Co Ltd プリント配線板
US6335571B1 (en) 1997-07-21 2002-01-01 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
WO1999004430A1 (en) 1997-07-21 1999-01-28 Aguila Technologies, Inc. Semiconductor flip-chip package and method for the fabrication thereof
US5985456A (en) 1997-07-21 1999-11-16 Miguel Albert Capote Carboxyl-containing polyunsaturated fluxing adhesive for attaching integrated circuits
US6448665B1 (en) 1997-10-15 2002-09-10 Kabushiki Kaisha Toshiba Semiconductor package and manufacturing method thereof
JP3819576B2 (ja) 1997-12-25 2006-09-13 沖電気工業株式会社 半導体装置及びその製造方法
US6324754B1 (en) 1998-03-25 2001-12-04 Tessera, Inc. Method for fabricating microelectronic assemblies
US6329605B1 (en) 1998-03-26 2001-12-11 Tessera, Inc. Components with conductive solder mask layers
JP2000031204A (ja) 1998-07-07 2000-01-28 Ricoh Co Ltd 半導体パッケージの製造方法
JP2000133672A (ja) 1998-10-28 2000-05-12 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
JP3346320B2 (ja) 1999-02-03 2002-11-18 カシオ計算機株式会社 半導体装置及びその製造方法
JP2001068836A (ja) 1999-08-27 2001-03-16 Mitsubishi Electric Corp プリント配線基板及び半導体モジュール並びに半導体モジュールの製造方法
TW429492B (en) 1999-10-21 2001-04-11 Siliconware Precision Industries Co Ltd Ball grid array package and its fabricating method
US6774474B1 (en) 1999-11-10 2004-08-10 International Business Machines Corporation Partially captured oriented interconnections for BGA packages and a method of forming the interconnections
TW569424B (en) 2000-03-17 2004-01-01 Matsushita Electric Ind Co Ltd Module with embedded electric elements and the manufacturing method thereof
US6573610B1 (en) 2000-06-02 2003-06-03 Siliconware Precision Industries Co., Ltd. Substrate of semiconductor package for flip chip package
US6787918B1 (en) 2000-06-02 2004-09-07 Siliconware Precision Industries Co., Ltd. Substrate structure of flip chip package
US6201305B1 (en) 2000-06-09 2001-03-13 Amkor Technology, Inc. Making solder ball mounting pads on substrates
JP3554533B2 (ja) 2000-10-13 2004-08-18 シャープ株式会社 チップオンフィルム用テープおよび半導体装置
US7242099B2 (en) 2001-03-05 2007-07-10 Megica Corporation Chip package with multiple chips connected by bumps
US6818545B2 (en) 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US7902679B2 (en) 2001-03-05 2011-03-08 Megica Corporation Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump
US6451626B1 (en) * 2001-07-27 2002-09-17 Charles W.C. Lin Three-dimensional stacked semiconductor package
TW507341B (en) 2001-11-01 2002-10-21 Siliconware Precision Industries Co Ltd Substrate capable of preventing delamination of chip and semiconductor encapsulation having such a substrate
US6870276B1 (en) 2001-12-26 2005-03-22 Micron Technology, Inc. Apparatus for supporting microelectronic substrates
JP2003273145A (ja) 2002-03-12 2003-09-26 Sharp Corp 半導体装置
US6780673B2 (en) 2002-06-12 2004-08-24 Texas Instruments Incorporated Method of forming a semiconductor device package using a plate layer surrounding contact pads
JP2004095923A (ja) 2002-09-02 2004-03-25 Murata Mfg Co Ltd 実装基板およびこの実装基板を用いた電子デバイス
JP2004111676A (ja) 2002-09-19 2004-04-08 Toshiba Corp 半導体装置、半導体パッケージ用部材、半導体装置の製造方法
US7173342B2 (en) 2002-12-17 2007-02-06 Intel Corporation Method and apparatus for reducing electrical interconnection fatigue
JP4114483B2 (ja) 2003-01-10 2008-07-09 セイコーエプソン株式会社 半導体チップの実装方法、半導体実装基板、電子デバイスおよび電子機器
US6774497B1 (en) 2003-03-28 2004-08-10 Freescale Semiconductor, Inc. Flip-chip assembly with thin underfill and thick solder mask
US20040232562A1 (en) 2003-05-23 2004-11-25 Texas Instruments Incorporated System and method for increasing bump pad height
US6849944B2 (en) 2003-05-30 2005-02-01 Texas Instruments Incorporated Using a supporting structure to control collapse of a die towards a die pad during a reflow process for coupling the die to the die pad
US6888255B2 (en) 2003-05-30 2005-05-03 Texas Instruments Incorporated Built-up bump pad structure and method for same
TW572361U (en) 2003-06-03 2004-01-11 Via Tech Inc Flip-chip package carrier
TWI227556B (en) 2003-07-15 2005-02-01 Advanced Semiconductor Eng Chip structure
TWI241702B (en) 2003-07-28 2005-10-11 Siliconware Precision Industries Co Ltd Ground pad structure for preventing solder extrusion and semiconductor package having the ground pad structure
KR100523330B1 (ko) 2003-07-29 2005-10-24 삼성전자주식회사 Ｓｍｄ 및 ｎｓｍｄ 복합형 솔더볼 랜드 구조를 가지는ｂｇａ 반도체 패키지
TWI234258B (en) 2003-08-01 2005-06-11 Advanced Semiconductor Eng Substrate with reinforced structure of contact pad
TWI241675B (en) 2003-08-18 2005-10-11 Siliconware Precision Industries Co Ltd Chip carrier for semiconductor chip
KR100541394B1 (ko) 2003-08-23 2006-01-10 삼성전자주식회사 비한정형 볼 그리드 어레이 패키지용 배선기판 및 그의제조 방법
US7271484B2 (en) 2003-09-25 2007-09-18 Infineon Technologies Ag Substrate for producing a soldering connection
JP3877717B2 (ja) 2003-09-30 2007-02-07 三洋電機株式会社 半導体装置およびその製造方法
JP2005109187A (ja) 2003-09-30 2005-04-21 Tdk Corp フリップチップ実装回路基板およびその製造方法ならびに集積回路装置
US6919224B2 (en) * 2003-09-30 2005-07-19 Intel Corporation Modified chip attach process and apparatus
US8026128B2 (en) * 2004-11-10 2011-09-27 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
KR101286379B1 (ko) 2003-11-10 2013-07-15 스태츠 칩팩, 엘티디. 범프-온-리드 플립 칩 인터커넥션
US7294929B2 (en) 2003-12-30 2007-11-13 Texas Instruments Incorporated Solder ball pad structure
WO2005093817A1 (ja) 2004-03-29 2005-10-06 Nec Corporation 半導体装置及びその製造方法
JP4024773B2 (ja) 2004-03-30 2007-12-19 シャープ株式会社 配線基板、半導体装置およびその製造方法並びに半導体モジュール装置
TWI240389B (en) 2004-05-06 2005-09-21 Advanced Semiconductor Eng High-density layout substrate for flip-chip package
US7224073B2 (en) 2004-05-18 2007-05-29 Ultratera Corporation Substrate for solder joint
US7057284B2 (en) 2004-08-12 2006-06-06 Texas Instruments Incorporated Fine pitch low-cost flip chip substrate
JP2006108313A (ja) 2004-10-04 2006-04-20 Rohm Co Ltd 実装基板および半導体装置
US20060131758A1 (en) 2004-12-22 2006-06-22 Stmicroelectronics, Inc. Anchored non-solder mask defined ball pad
WO2006105015A2 (en) * 2005-03-25 2006-10-05 Stats Chippac Ltd. Flip chip interconnection having narrow interconnection sites on the substrate
US20060255473A1 (en) * 2005-05-16 2006-11-16 Stats Chippac Ltd. Flip chip interconnect solder mask
US7728437B2 (en) 2005-11-23 2010-06-01 Fairchild Korea Semiconductor, Ltd. Semiconductor package form within an encapsulation
JP4971769B2 (ja) 2005-12-22 2012-07-11 新光電気工業株式会社 フリップチップ実装構造及びフリップチップ実装構造の製造方法
TWI286830B (en) 2006-01-16 2007-09-11 Siliconware Precision Industries Co Ltd Electronic carrier board
TWI294682B (en) 2006-02-03 2008-03-11 Siliconware Precision Industries Co Ltd Semiconductor package substrate
US20070200234A1 (en) 2006-02-28 2007-08-30 Texas Instruments Incorporated Flip-Chip Device Having Underfill in Controlled Gap
US7656042B2 (en) * 2006-03-29 2010-02-02 Taiwan Semiconductor Manufacturing Co., Ltd. Stratified underfill in an IC package
US7317245B1 (en) 2006-04-07 2008-01-08 Amkor Technology, Inc. Method for manufacturing a semiconductor device substrate
JP2007305881A (ja) 2006-05-12 2007-11-22 Sharp Corp テープキャリアおよび半導体装置並びに半導体モジュール装置
US7902660B1 (en) 2006-05-24 2011-03-08 Amkor Technology, Inc. Substrate for semiconductor device and manufacturing method thereof
US20080093749A1 (en) 2006-10-20 2008-04-24 Texas Instruments Incorporated Partial Solder Mask Defined Pad Design
TWI331388B (en) 2007-01-25 2010-10-01 Advanced Semiconductor Eng Package substrate, method of fabricating the same and chip package
JP4618260B2 (ja) 2007-02-21 2011-01-26 日本テキサス・インスツルメンツ株式会社 導体パターンの形成方法、半導体装置の製造方法、並びに半導体装置
US7521284B2 (en) 2007-03-05 2009-04-21 Texas Instruments Incorporated System and method for increased stand-off height in stud bumping process
TWI361482B (en) 2007-05-10 2012-04-01 Siliconware Precision Industries Co Ltd Flip-chip semiconductor package structure and package substrate applicable thereto
US8106496B2 (en) 2007-06-04 2012-01-31 Stats Chippac, Inc. Semiconductor packaging system with stacking and method of manufacturing thereof
US7868445B2 (en) 2007-06-25 2011-01-11 Epic Technologies, Inc. Integrated structures and methods of fabrication thereof with fan-out metallization on a chips-first chip layer
TWI357137B (en) 2007-10-19 2012-01-21 Advanced Semiconductor Eng Flip chip package structure and carrier thereof
TWI358113B (en) 2007-10-31 2012-02-11 Advanced Semiconductor Eng Substrate structure and semiconductor package usin
TW200921868A (en) 2007-11-07 2009-05-16 Advanced Semiconductor Eng Substrate structure
US10074553B2 (en) * 2007-12-03 2018-09-11 STATS ChipPAC Pte. Ltd. Wafer level package integration and method
US7847399B2 (en) 2007-12-07 2010-12-07 Texas Instruments Incorporated Semiconductor device having solder-free gold bump contacts for stability in repeated temperature cycles
JP5107012B2 (ja) 2007-12-12 2012-12-26 新光電気工業株式会社 配線基板及び電子部品の実装構造の製造方法
TWI340615B (en) 2008-01-30 2011-04-11 Advanced Semiconductor Eng Surface treatment process for circuit board
US7670939B2 (en) 2008-05-12 2010-03-02 Ati Technologies Ulc Semiconductor chip bump connection apparatus and method
US7772046B2 (en) * 2008-06-04 2010-08-10 Stats Chippac, Ltd. Semiconductor device having electrical devices mounted to IPD structure and method for shielding electromagnetic interference
US7851928B2 (en) 2008-06-10 2010-12-14 Texas Instruments Incorporated Semiconductor device having substrate with differentially plated copper and selective solder
TWI425896B (zh) 2008-06-11 2014-02-01 Advanced Semiconductor Eng 具有內埋式導電線路之電路板及其製造方法
US7932170B1 (en) 2008-06-23 2011-04-26 Amkor Technology, Inc. Flip chip bump structure and fabrication method
US7790509B2 (en) 2008-06-27 2010-09-07 Texas Instruments Incorporated Method for fine-pitch, low stress flip-chip interconnect
TWI384600B (zh) 2008-12-09 2013-02-01 Advanced Semiconductor Eng 內埋線路基板及其製造方法
US7642128B1 (en) * 2008-12-12 2010-01-05 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US7898083B2 (en) 2008-12-17 2011-03-01 Texas Instruments Incorporated Method for low stress flip-chip assembly of fine-pitch semiconductor devices
US20110049703A1 (en) 2009-08-25 2011-03-03 Jun-Chung Hsu Flip-Chip Package Structure
US8368187B2 (en) * 2010-02-03 2013-02-05 Stats Chippac, Ltd. Semiconductor device and method of forming air gap adjacent to stress sensitive region of the die
US8574960B2 (en) * 2010-02-03 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming cavity adjacent to sensitive region of semiconductor die using wafer-level underfill material
US8039384B2 (en) * 2010-03-09 2011-10-18 Stats Chippac, Ltd. Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces
US8357564B2 (en) * 2010-05-17 2013-01-22 Stats Chippac, Ltd. Semiconductor device and method of forming prefabricated multi-die leadframe for electrical interconnect of stacked semiconductor die

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200924137A (en) * 2007-11-19 2009-06-01 Subtron Technology Co Ltd Chip package carrier, chip package and method for fabricating the same
TW201005894A (en) * 2008-07-31 2010-02-01 Powertech Technology Inc Pillar-to-pillar flip-chip assembly
US20100164097A1 (en) * 2008-12-31 2010-07-01 Stats Chippac, Ltd. Semiconductor Device and Method of Confining Conductive Bump Material During Reflow with Solder Mask Patch

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