TW201005894A - Pillar-to-pillar flip-chip assembly - Google Patents
Pillar-to-pillar flip-chip assembly Download PDFInfo
- Publication number
- TW201005894A TW201005894A TW097129134A TW97129134A TW201005894A TW 201005894 A TW201005894 A TW 201005894A TW 097129134 A TW097129134 A TW 097129134A TW 97129134 A TW97129134 A TW 97129134A TW 201005894 A TW201005894 A TW 201005894A
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- Taiwan
- Prior art keywords
- column
- copper pillars
- substrate
- flip
- wafer
- Prior art date
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 121
- 229910052802 copper Inorganic materials 0.000 claims abstract description 121
- 239000010949 copper Substances 0.000 claims abstract description 121
- 239000000758 substrate Substances 0.000 claims abstract description 81
- 229910000679 solder Inorganic materials 0.000 claims abstract description 68
- 239000000463 material Substances 0.000 claims abstract description 44
- 238000005476 soldering Methods 0.000 claims abstract description 5
- 239000002184 metal Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000000565 sealant Substances 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 29
- 230000035882 stress Effects 0.000 description 8
- 229910000831 Steel Inorganic materials 0.000 description 7
- 239000010959 steel Substances 0.000 description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 230000008602 contraction Effects 0.000 description 5
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
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- 239000000084 colloidal system Substances 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- FHKNFXAIEAYRKQ-UHFFFAOYSA-N [Cu].[Ir] Chemical compound [Cu].[Ir] FHKNFXAIEAYRKQ-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000007766 curtain coating Methods 0.000 description 1
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- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- ALKZAGKDWUSJED-UHFFFAOYSA-N dinuclear copper ion Chemical compound [Cu].[Cu] ALKZAGKDWUSJED-UHFFFAOYSA-N 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000003344 environmental pollutant Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 231100000719 pollutant Toxicity 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000007761 roller coating Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
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- 229910052709 silver Inorganic materials 0.000 description 1
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Classifications
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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Abstract
Description
201005894 九、發明說明: 【發明所屬之技術領域】 本發明係有關於一種半導體裝置,特別係有關於一 種柱對柱覆晶結構。 【先前技術】 覆晶接合技術(flip-chip bonding technology)是將晶 片之主動面的銲墊上設置複數個導電凸塊(或稱為突出 ❹ 狀電極)’藉由晶片翻轉方式接合到基板以完成電性連 接。相較於使用打線連接(wire bond)之電性連接方式, 由於覆晶封裝技術提供晶片與基板之間一種較短的電 性連接路徑,可使晶片内更高工作頻率的積體電路具有 良好的高頻訊號的傳輸品質。因此,覆晶接合是先進半 導體裝置的必然發展趨勢,可提供更快的處理速度與更 高的效能。但導電凸塊接合之後晶片與基板結合係為點 對點的局部連接,一旦受到應力而凸塊斷裂,則將造成 • 晶片與基板之間電氣訊號傳遞失敗。目前的凸塊有錫鉛 凸塊與金凸塊兩大類,錫鉛凸塊不符合歐洲環保能源法 規RoHS的無船化要求,金凸塊則成本過高。若直接將 錫錯凸塊置換成無錯凸塊’則會有可靠度降低的問題。 此外,錫鉛凸塊需要加熱回焊成球形,在高溫下不具有 間隙維持的功能。金凸塊是以熱壓合達到凸塊結合,在 高溫壓合下凸塊會變形’亦不具有間隙維持的功能。因 此’在目刖的覆晶接合技術中,無論是锡鉛凸塊或金凸 塊都無法有效控制在覆晶接合時晶片與基板之間的間 5 201005894 隙,且常會隨著製程參數的溫度或壓力的變化而會產生 有控制不一致的覆晶間隙,進而影響封膠品質。 如美國專利第US 6,229,220號所揭示技術,ibm公 司提出一種習知覆晶接合結構以控制一致的覆晶門 隙,第1圖係為該覆晶結構在覆晶前的截面示意圖。兮 覆晶結構主要包含一基板110、一晶片12〇以及複數個 銅柱130。該基板110係作為晶片載體並具有一上表面 111以及對應之一下表面11^該上表面"丨係形成有 複數個連接墊114。該晶片120係覆晶接合方式設於今 基板110之該上表面111,該晶片120之一主動面121 係設有複數個銲墊122。該些銅柱130是配置在該些鲜 塾122上,用以控制覆晶間隙。每一銅柱之頂端預 先形成了一焊接材料150。經由該焊接材料15〇以電性 連接該些銅柱130與該基板11〇之該些連接墊114,再 透過該基板11〇内部之導電跡線(conductivetrace)連接 ❹ 到外部電子裝置。如第2圖所示,該焊接材料15〇在回 焊(reflowing)之後,可接合該些銅柱13〇與該些連接墊 114。該些銅柱130之高度係大於該些連接墊114之高 度’該些連接墊114係直接顯露在該基板11〇之該上表 面111’該焊接材料15〇在該些銅柱13〇與該些連接墊 11 4之間的每一焊接中心點丨5 1係相對偏移該晶片1 2〇 與該基板1 1 0之間間隙Hi的等分分隔面p,而使該焊 接材料1 5 0較為靠近該基板丨i 。 如第3囷所示,在上述習知覆晶結構中,該基板1 1 0 201005894 產生翹曲(warpage)或熱脹冷縮現象時,該些連接塾114 相較於該些銅柱130會承受較大熱應力而容易在焊接 界面產生斷裂或疋脫洛,造成電耽訊號傳遞失敗,進而 影響產品可靠度。 【發明内容】 有鐾於此,本發明之主要目的係在於提供一種柱對 柱覆晶結構,能減緩基板與晶片翹曲度差異或基板熱脹冷 縮現象對焊接材料與基板連接墊的直接應力作用,以避免 ® 焊點斷裂。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明所揭示之一種柱對柱覆晶結 構,主要包含一基板、一晶片、複數個第一銅柱、複數 個第二銅柱以及一焊接材料。該基板係具有一上表面以 及一下表面,該上表面係設置有一防焊層以及複數個連 接墊’該些連接墊係顯露於該防焊層之外。該晶片係設 φ 於該基板之該上表面,該晶片之一主動面係設有複數個 銲墊。該些第一銅柱係設置於該些銲墊上。該些第二銅 柱係設置於該些連接墊上。該焊接材料係連接該些第一 銅柱與該些第二銅柱,其中該些第一銅柱與該些第二銅 柱概約等高’以使該焊接材料的焊接中心點位於該晶片 與該基板之間間隙的等分分隔面。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在則述柱對柱覆晶結構中,該些第二銅柱之高度係可 7 201005894 不小於a亥晶片之厚度之二分之一。 在前述柱對柱覆晶結構中,該些第二銅柱係可為 錐形。 在前述柱對柱覆晶結構中,該些第二銅柱突出於 些連接墊的高度係可不小於該些第二銅柱在對應連 塾上設置區域之一長度或一直徑。 在刖述柱對柱覆晶結構中,該些第二銅柱係可不 該防焊層接觸。 在則述柱對柱覆晶結構中,該晶片係可具有複數 凸塊下金屬層,其係形成於該些第一銅柱與該些銲墊 間。 在前述柱對柱覆晶結構中,可另包含一底部填 膠’係填滿該晶片與該基板之間間隙。 在前述柱對柱覆晶結構中,可另包含一封膠體, 填滿該晶片與該基板之間間隙並密封該晶片。 • 在前述柱對柱覆晶結構中,該基板係可為一印刷 路板。 在前述柱對柱覆晶結構中,該防焊層係可具有複 個開孔,其孔徑係稱小於該些連接塾但大於該些第二 柱之長度或一直徑,以使該防焊層局部顯露該些連 塾不被該些第二銅柱覆蓋之區域。 在前述柱對柱覆晶結構中,該些第二銅柱係可為 柱體。 在前述柱對柱覆晶結構中,該些第二銅柱係可為 平 該 接 與 個 之 充 係 電 數 銅 接 圓 多 8 201005894 角柱體^ 在刚述柱對柱覆晶結構中,該些第二銅柱係可具有 複數個壁面,係朝向該些連接墊之複數個角隅。 由以上技術方案可以看出,本發明之柱對柱覆晶結 構’具有以下優點與功效: 一、藉由基板設有與晶片上第一鋼柱等高之複數個第二 銅柱’以改變焊接材料的焊接中心點位置至位於該 曰曰片與該基板之間間隙的等分分隔面,能減緩基板 與晶片翹曲度差異或基板熱脹冷縮現象對焊接材料 與基板連接塾的直接應力作用,以避免烊點斷裂。 此外,可以取代銲球,更可符合無鉛化、高可靠度 與低製造成本之要求。 一、藉由基板上第二銅柱的高度增加該晶片與該基板之 間間隙直到不小於晶片厚度,以提高銅柱間焊接中 心點的最大可承受應力,並有助於封膠體或底部填 充膠之填入。 三、 藉由防焊層對應於第二銅柱之開孔尺寸,以使防焊 層局部顯露基板上連接墊不被第二銅柱覆蓋之區 域’故能固著多餘焊接材料在第二銅柱之周邊,防 止產生錫珠。 四、 藉由基板上第二銅柱之複數個壁面朝向基板連接墊 之複數個角隅,以增加較佳的多餘焊接材料固著區 域。 五、 利用基板上第二銅柱為平錐形,使焊接材料往位於 9 201005894 該晶片與該基板之間間隙的等分分隔面集中以避 免焊接材料在基板連接墊上的擴散污染。 【實施方式】201005894 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, and more particularly to a column-to-column flip chip structure. [Prior Art] Flip-chip bonding technology is to form a plurality of conductive bumps (or called protruding electrodes) on a pad of an active surface of a wafer to be bonded to a substrate by wafer flipping. Electrical connection. Compared with the electrical connection method using a wire bond, since the flip chip packaging technology provides a short electrical connection path between the wafer and the substrate, the integrated circuit of the higher operating frequency in the wafer can be made good. The transmission quality of high frequency signals. Therefore, flip chip bonding is an inevitable trend in advanced semiconductor devices, providing faster processing speeds and higher performance. However, after the conductive bumps are bonded, the wafer and the substrate are bonded in a point-to-point local connection. Once the bump is broken due to stress, the electrical signal transmission between the wafer and the substrate fails. At present, there are two types of bumps, tin-lead bumps and gold bumps. The tin-lead bumps do not meet the European ship-free requirements of RoHS. The gold bumps are too expensive. If the tin bump is directly replaced by the bump-free bump, there is a problem that the reliability is lowered. In addition, the tin-lead bumps need to be heated and reflowed into a spherical shape, and have no gap maintenance function at high temperatures. The gold bumps are bonded by a thermocompression to the bumps, and the bumps are deformed under high temperature pressing, and the gap is not maintained. Therefore, in the flip-chip bonding technology, neither the tin-lead bump nor the gold bump can effectively control the gap between the wafer and the substrate during the flip-chip bonding, and often along with the temperature of the process parameters. Or the change of pressure will produce a laminating gap with inconsistent control, which will affect the quality of the seal. As disclosed in U.S. Patent No. 6,229,220, the ibm company teaches a conventional flip-chip bonding structure to control a uniform flip-chip gap, and Fig. 1 is a schematic cross-sectional view of the flip-chip structure before flipping.覆 The flip chip structure mainly comprises a substrate 110, a wafer 12 〇 and a plurality of copper pillars 130. The substrate 110 is a wafer carrier and has an upper surface 111 and a corresponding lower surface 11 which is formed with a plurality of connection pads 114. The wafer 120 is formed by flip chip bonding on the upper surface 111 of the substrate 110. One of the active surfaces 121 of the wafer 120 is provided with a plurality of pads 122. The copper pillars 130 are disposed on the fresh crucibles 122 for controlling the flip chip gap. A solder material 150 is pre-formed at the top of each copper post. The connection pads 114 of the copper pillars 130 and the substrate 11 are electrically connected via the solder material 15 and then connected to the external electronic device through conductive traces inside the substrate 11 . As shown in Fig. 2, the solder material 15 is bonded to the copper pads 13 and the connection pads 114 after reflowing. The height of the copper pillars 130 is greater than the height of the connection pads 114. The connection pads 114 are directly exposed on the upper surface 111 of the substrate 11'. The solder material 15 is on the copper pillars 13 and Each of the soldering center points 丨51 between the connecting pads 11 4 is oppositely offset from the bisector separating surface p of the gap Hi between the wafer 1 2 〇 and the substrate 110, and the solder material 1 50 Closer to the substrate 丨i. As shown in FIG. 3, in the above conventional flip chip structure, when the substrate 1 1 0 201005894 generates warpage or thermal expansion and contraction, the connection ports 114 are compared with the copper columns 130. It is easy to bear the large thermal stress and it is easy to break or smash at the welding interface, which causes the failure of the signal transmission, which affects the reliability of the product. SUMMARY OF THE INVENTION In view of this, the main object of the present invention is to provide a column-to-column flip-chip structure, which can slow the difference between the substrate and the wafer warpage or the thermal expansion and contraction of the substrate to the solder material and the substrate connection pad. Stress action to avoid ® solder joint breakage. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a column-to-column flip-chip structure mainly comprises a substrate, a wafer, a plurality of first copper pillars, a plurality of second copper pillars, and a solder material. The substrate has an upper surface and a lower surface, the upper surface being provided with a solder resist layer and a plurality of connecting pads. The connecting pads are exposed outside the solder resist layer. The wafer is φ on the upper surface of the substrate, and one of the active faces of the wafer is provided with a plurality of pads. The first copper pillars are disposed on the pads. The second copper pillars are disposed on the connecting pads. The solder material is connected to the first copper pillars and the second copper pillars, wherein the first copper pillars are approximately equal to the second copper pillars so that the soldering center of the solder material is located on the wafer An equally spaced surface of the gap with the substrate. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the column-to-column flip-chip structure, the height of the second copper pillars may be not less than one-half of the thickness of the a-half wafer. In the above column-column flip-chip structure, the second copper pillars may be tapered. In the column-column flip-chip structure, the heights of the second copper pillars protruding from the connection pads may be not less than a length or a diameter of the regions where the second copper pillars are disposed on the corresponding junctions. In the column-to-column flip-chip structure, the second copper pillars may not be in contact with the solder resist layer. In the column-to-column flip-chip structure, the wafer system may have a plurality of under bump metal layers formed between the first copper pillars and the pads. In the pillar-to-column flip-chip structure, an underfill may be further included to fill the gap between the wafer and the substrate. In the column-column flip-chip structure, a colloid may be further included to fill the gap between the wafer and the substrate and seal the wafer. • In the column-column flip-chip structure described above, the substrate may be a printed circuit board. In the column-column flip-chip structure, the solder resist layer may have a plurality of openings, the apertures of which are smaller than the connection ports but larger than the length or a diameter of the second columns, so that the solder resist layer The areas where the flails are not covered by the second copper pillars are partially exposed. In the column-column flip-chip structure, the second copper pillars may be pillars. In the column-column flip-chip structure, the second copper pillars may be flat and connected to each other, and the number of copper coils is more than 8 201005894 corner cylinders ^ in the column-to-column flip-chip structure The second copper pillars may have a plurality of wall faces facing a plurality of corners of the connecting pads. It can be seen from the above technical solution that the pillar-to-column flip-chip structure of the present invention has the following advantages and effects: 1. The substrate is provided with a plurality of second copper pillars having the same height as the first steel pillar on the wafer. The welding center point of the solder material is located at an equally spaced surface between the die and the substrate, which can slow the difference between the substrate and the wafer warpage or the thermal expansion and contraction of the substrate to the solder material and the substrate. Stress acts to avoid breakage of the defects. In addition, it can replace solder balls and meet the requirements of lead-free, high reliability and low manufacturing cost. 1. Increasing the gap between the wafer and the substrate by the height of the second copper pillar on the substrate until not less than the thickness of the wafer, so as to increase the maximum withstand stress of the soldering center point between the copper pillars, and contribute to the encapsulant or underfill Fill in the glue. 3. By the solder resist layer corresponding to the opening size of the second copper pillar, so that the solder resist layer partially exposes the region on the substrate where the connection pad is not covered by the second copper pillar, so that the excess solder material can be fixed in the second copper The perimeter of the column prevents the formation of tin beads. 4. The plurality of walls of the second copper pillar on the substrate are oriented toward the plurality of corners of the substrate connection pad to increase the preferred excess solder material adhesion area. 5. Using the second copper pillar on the substrate as a flat taper, the solder material is concentrated on the equally spaced surface of the gap between the wafer and the substrate at 9 201005894 to avoid diffusion contamination of the solder material on the substrate connection pad. [Embodiment]
以下將配合所附圖示詳細說明本發明之實施例,然 應注意的是,該些圖示均為簡化之示意圖,僅以示意= 法來說明本發明之基本架構或實施方法,故僅顯示與本 案有關之兀件,且所顯示之元件並非以實際實施之數 目、形狀、尺寸比例緣製,某些尺寸比例與其他相關尺 寸比例已經被修飾放大或是簡化,以提供更清楚的描 述’實際實施之數目、形狀及尺寸比例為一種選置性之 設計,且詳細之元件佈局可能更為複雜。 依據本發明之第一具體實施例,一種柱對柱覆晶結 構舉例說明於第4圖之截面示意圖。該柱對柱覆晶結構 2〇〇主要包含一基板210、一晶片220、複數個第一銅 枉230、複數個第二銅柱240以及一焊接材料250。 該基板210係具有一上表面211以及一下表面212, 其係可為一種高密度雙面導通之多層印刷電路板,内部 形成有導電跡線(conductive trace)與鍍通孔(圖中未繪 出)'。該基板2 1 0係可為一基板條内陣列排列之一單元。 經過裁切之後而形成如本實施例之該基板2 1 0。該上表 面211係設置有一防焊層213以及複數個連接墊214。 該些連接墊214係顯露於該防焊層213之外。該防焊層 213 即是俗稱之「綠漆」(Soldermask or Solderresist) ’ 以環氧樹脂及感光樹脂為主要組成份’主要塗佈於印刷 10 201005894 電路板表面’以形成一遮覆導電跡線免於受外界水氣、 污染物侵害之絕緣保護層。該防焊層2 13係可以網印 (screen printing)、簾幕塗佈(curtain coating)、喷霧塗 佈(spray coating)、滾輪塗佈(roller coating)等方式形 成。具體而言,該防焊層2 1 3係可具有複數個開孔2 1 5 ’ 以顯露該些該些連接墊214。 如第4圖所示,該晶片2 2 0係設於該基板2 1 0之該 上表面211,該晶片220之一主動面221係設有複數個 銲墊222,該些銲墊222係作為該晶片220訊號輸出入 之媒介。該晶片220係為半導體材質,該主動面221上 係設有積體電路元件,選自於微控制器、微處理器、記 憶體、邏輯電路、特殊應用積體電路(如顯示器驅動電 路)等或上述組合。具體而言,如第6圖所示,該晶片 220 係可具有複數個凸塊下金屬層(under bump metallurgy layer,UBM layer)223,其係形成於該些第一 銅柱230與該些銲墊222之間,該些凸塊下金屬層223 係可利用濺鍍方式形成,通常由三層導電金屬層(圖未 繪出)所主要構成,即一黏著層(adhesion)、一渥潤層 (wetting layer)及一抗氧化層(oxidation barrier layer), 用以增進該些第一銅柱230與該些銲墊222之間的連 結。該晶片220之該主動面22 1另可覆蓋一電絕緣性之 保護層(passivation layer)224,該保護層224係大致覆 蓋該主動面221但顯露該些銲墊222,可提供保護該主 動面221上之積體電路元件並使該主動面221較為平 11 201005894 坦。該些凸塊下金屬層223係結合於該些銲墊222 蓋至該保護層224之開孔周邊部分表面。The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The components related to this case, and the components shown are not based on the actual number, shape and size ratio. Some size ratios and other related size ratios have been modified or simplified to provide a clearer description. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated. In accordance with a first embodiment of the present invention, a column-to-column flip-chip structure is illustrated in cross-section of Figure 4. The pillar-to-column structure 2 〇〇 mainly comprises a substrate 210, a wafer 220, a plurality of first copper iridium 230, a plurality of second copper pillars 240, and a solder material 250. The substrate 210 has an upper surface 211 and a lower surface 212, which can be a high-density double-sided conductive multilayer printed circuit board with conductive traces and plated through holes (not shown). )'. The substrate 210 can be a unit arranged in an array within a substrate strip. After the cutting, the substrate 2 10 as in the present embodiment is formed. The upper surface 211 is provided with a solder resist layer 213 and a plurality of connection pads 214. The connection pads 214 are exposed outside the solder resist layer 213. The solder resist layer 213 is commonly known as "Soldermask or Solderresist". The main component of the epoxy resin and the photosensitive resin is mainly applied to the surface of the printed circuit board 10 201005894 to form a covered conductive trace. It is protected from the insulating layer damaged by external moisture and pollutants. The solder resist layer 2 13 can be formed by screen printing, curtain coating, spray coating, roller coating or the like. Specifically, the solder resist layer 2 1 3 may have a plurality of openings 2 1 5 ' to expose the plurality of connection pads 214. As shown in FIG. 4, the wafer 220 is disposed on the upper surface 211 of the substrate 210. One active surface 221 of the wafer 220 is provided with a plurality of pads 222, and the pads 222 are used as The chip 220 signals the medium into which it is output. The wafer 220 is made of a semiconductor material, and the active surface 221 is provided with an integrated circuit component selected from a microcontroller, a microprocessor, a memory, a logic circuit, a special application integrated circuit (such as a display driving circuit), and the like. Or a combination of the above. Specifically, as shown in FIG. 6, the wafer 220 may have a plurality of under bump metallurgy layers (UBM layers) 223 formed on the first copper pillars 230 and the solders. Between the pads 222, the under bump metal layers 223 can be formed by sputtering, and are usually composed of three layers of conductive metal layers (not shown), that is, an adhesive layer and a wet layer. (wetting layer) and an oxidation barrier layer for enhancing the connection between the first copper pillars 230 and the pads 222. The active surface 22 of the wafer 220 may further cover an electrically insulating passivation layer 224. The protective layer 224 substantially covers the active surface 221 but exposes the pads 222 to provide protection to the active surface. The integrated circuit component on 221 and the active surface 221 are relatively flat 11 201005894. The under bump metal layer 223 is bonded to the surface of the peripheral portion of the opening of the protective layer 224.
如第4圖所示,該些第一銅柱23 0係設置於該 墊222上。該些第二銅柱240係設置於該些連接f 上。其中上述的銅柱係指純銅柱、銅合金柱或是硬 於金之高剛性導電柱。如第5圖所示,該些第二 240突出於該些連接墊214的高度H3係可不小於 第二銅柱240在對應連接墊214上設置區域之一長 參 一直徑D’以呈具體柱狀。如第5圖所示,在本實 中’該防焊層213之該些開孔215之孔徑或一長度 小於該些連接墊214但大於該些第二銅柱24〇之一 或一直徑D。如第5圖所示’該些開孔215概呈;$ 而該第二銅柱240係為圓柱體,該些開孔2丨5之一 邊長度係大於該第二銅柱240之直徑D。因此,在 佳的型態中’該些第二銅柱24〇係可不與該防焊層 〇 接觸,以使該防焊層213局部顯露該些連接墊214 該些第二銅柱24 0覆蓋之區域214A。如第5圖所 每一連接墊214之區域214A係不被對應第二銅柱 覆蓋,亦不被該防焊層213所覆蓋,該區域214A 以固著多餘之焊接材料25〇在該些第二銅柱24〇 邊,防止錫珠的產生。 因此°亥日日片220與該基板210皆設置有凸起 柱。並利用該焊接材料250連接該些第一銅柱23〇 些第二鋼柱240,以將其機械性焊接接合。詳細而 並覆 些銲 >214 度大 銅柱 該些 度或 施例 係稍 長度 -形, 較短 一較 213 不被 示, 240 能用 之周 之銅 與該 言 , 12 201005894 如第6及7圖所示,該焊接材料25〇係可預先設置在誃 些第一銅柱230之頂端,在覆晶壓合之後,再經回= (reflowing)以使該焊接材料25〇熔化接合該些第—銅权 230與該些第二銅柱240並形成電性連接與機械結合關 係(如第8圖所示)。通常該焊接材料25〇係可選用無鉛 輝劑為較佳’以錫96.5%_銀3%_銅〇5%之焊接材料^ 例,在到達回焊溫度約攝氏217度以上,最高溫約為攝 氏245度時能產生焊接之濕潤性,而且該些第—鋼柱 230與該些第二銅柱24〇則必須具有高於上述回焊溫度 之熔點。 並且,如第8圖所示,該些第一銅柱23〇與該些第 一銅柱240概約等高,以使該焊接材料25〇的焊接中心 點25 1位於該晶片22〇與該基板2丨〇之間間隙H2的等 分分隔面P。由該等分分隔面p的任意點到該晶片22〇 與到該基板210之最短距離為相同,當該基板21〇有一 φ 相對於該晶片220之翹曲度差異時,該等分分隔面P的 勉曲度則約為該翹曲度差異之二分之一。故該些第—銅 柱.230與該些第二銅柱24〇位置係互相垂直對應,並具 有相等高度,其高度大約為30至9〇 μΓη。由於該些第 一銅柱230與該些第二銅柱24〇具有高剛性與低成本之 特性’該晶片220係疊設在該基板2 1 0之上並能維持一 致的覆晶間隙Η2,約為兩倍的銅柱高度。較佳地,如 第8圖所示,該些第二銅柱24〇之高度Η3係可不小於 該晶片220之厚度τ之二分之一。藉由該基板21〇上該 13 201005894 些第二銅柱24〇的高度增加使該晶片22〇與該基板2i〇 之間間隙H2直至不小於該晶片22〇厚度τ,可提高在 銅柱之間該些焊接中心點251的最大可承受應力。 如第9圖所示,當該基板21〇受到熱應力而翹曲變 形或有熱脹冷縮現象時,該焊接材料25〇的焊接中心點 25 1仍位於該等分分隔面ρ,能減緩該基板2丨〇與該晶As shown in Fig. 4, the first copper posts 230 are disposed on the pad 222. The second copper pillars 240 are disposed on the connections f. The above copper column refers to a pure copper column, a copper alloy column or a highly rigid conductive column harder than gold. As shown in FIG. 5, the heights H3 of the second pads 240 protruding from the connection pads 214 may be not less than a diameter D' of the second copper pillar 240 disposed on the corresponding connection pad 214 to form a specific column. shape. As shown in FIG. 5, in the present embodiment, the aperture or length of the openings 215 of the solder resist layer 213 is smaller than the connection pads 214 but larger than one or a diameter D of the second copper pillars 24 . As shown in FIG. 5, the openings 215 are generally visible; and the second copper pillars 240 are cylindrical, and the length of one of the openings 2丨5 is greater than the diameter D of the second copper pillars 240. Therefore, in a preferred form, the second copper pillars 24 are not in contact with the solder mask layer, so that the solder resist layer 213 partially exposes the connection pads 214 and the second copper pillars 240 are covered. Area 214A. The area 214A of each of the connection pads 214 as shown in FIG. 5 is not covered by the corresponding second copper pillars and is not covered by the solder resist layer 213. The region 214A is fixed with the excess solder material 25 in the first The two copper columns are 24 sides to prevent the generation of tin beads. Therefore, the celestial sheet 220 and the substrate 210 are both provided with raised columns. The first copper posts 23 and the second steel posts 240 are joined by the solder material 250 to mechanically bond them. Detailed and covered with some soldering > 214 degrees large copper column, the degree or the application is slightly length-shaped, shorter one is not shown, 213 is not shown, 240 can be used with the copper and the words, 12 201005894 as the sixth As shown in FIG. 7 , the solder material 25 can be preliminarily disposed at the top end of the first copper pillars 230, and after recrystallization, and then reflowing, the solder material 25 is melted and bonded. The first copper-copper 230 forms an electrical connection and a mechanical bond relationship with the second copper pillars 240 (as shown in FIG. 8). Generally, the solder material 25 can be selected from a lead-free phosphor, preferably a solder material with a tin content of 96.5%_silver 3%_copper 〇, and the highest temperature is about 217 degrees Celsius when the reflow temperature is reached. The wettability of the weld can be produced at 245 degrees Celsius, and the first steel column 230 and the second copper posts 24 must have a melting point higher than the above-mentioned reflow temperature. Moreover, as shown in FIG. 8 , the first copper pillars 23 概 are approximately equal to the first copper pillars 240 such that the soldering center point 25 1 of the solder material 25 位于 is located on the wafer 22 〇 An equally divided surface P of the gap H2 between the substrates 2A. From the arbitrary point of the partitioning surface p to the wafer 22, the shortest distance to the substrate 210 is the same, and when the substrate 21 has a difference in warpage of φ with respect to the wafer 220, the dividing surface The degree of curvature of P is about one-half of the difference in warpage. Therefore, the first copper pillars 230 and the second copper pillars 24 are vertically aligned with each other and have an equal height, and the height is about 30 to 9 〇 μΓη. Because the first copper pillars 230 and the second copper pillars 24A have high rigidity and low cost characteristics, the wafer 220 is stacked on the substrate 210 and can maintain a uniform flip-chip gap Η2, It is about twice the height of the copper column. Preferably, as shown in Fig. 8, the height Η3 of the second copper pillars 24 is not less than one-half of the thickness τ of the wafer 220. By increasing the height of the second copper pillars 24〇 on the substrate 21, the gaps H2 between the wafer 22 and the substrate 2i are not less than the thickness τ of the wafer 22, which can be improved in the copper pillars. The maximum stress that can be withstood between the weld center points 251. As shown in FIG. 9, when the substrate 21 is subjected to thermal stress and warped or has thermal expansion and contraction, the welding center point 25 1 of the bonding material 25 is still located at the aliquot separating surface ρ, which can be slowed down. The substrate 2丨〇 and the crystal
片220翹曲度差異或是該基板21〇熱脹冷縮現象對該些 焊接中心點251與該些連接墊214的直接應力作用,以 避免該焊接材料250在焊接中心點251處斷裂。因此, 本發明係利用等高對應之該些第—銅柱23 〇與該些第 二銅柱240以及該焊接材料25〇取代習知的銲球、錫鉛 凸塊或金凸塊,不會有高溫下使覆晶間隙變化的問題, 更可符合無鉛化、高可靠度與低製造成本之要求。 此外,該些第一銅柱230與該些第二銅柱24〇係可 利用電鍍(electroplating)形成。如第4圖所示,該些第 一銅柱230與該些第二銅柱240係可具有相同尺寸與外 形,例如在本實施例中,該些第一銅柱2 3 0與該些第二 鋼柱240係可為圓柱體(如第5圖所示),但不受限制 地,亦可為各種形狀之多角柱體。如第10A及1〇B圖 所示’該些第二銅柱2 40,係可為八角柱體,其具有複數 個壁面241,該些壁面241係朝向該些連接墊214之複 數個角隅214B,藉由該基板210上該些第二鋼柱24〇, 之複數個壁面241朝向該些連接墊214之該些個角隅 21 4B,以使該些運接墊214具有增多的多餘焊接材料固 14 201005894 著區域。此外,利用該些朝向角隅214B之缺角型壁面 241 ’該些第二銅柱24 0’不會有朝向該些連接墊214之 該些角隅214B的側邊角。當該些第二銅柱240,受到某 一方向的應力時會分散在該些連接墊214,不會直接拉 扯該些連接墊214之該些角隅214B而產生剝離。如第 5圖所示’第一實施例的該些第二銅柱24〇為圓柱體, 亦具有同樣的功效,該些第二銅柱240朝向該些連接墊 214之角隅係為圓弧狀壁面,亦可防止該些連接墊214 •由角隅產生剝離。 再如第4與8圖所示,利用該焊接材料250接合該 些第一銅柱230與該些第二銅柱24〇之後,可以一高流 動性之底部填充膠260填滿該晶片22〇與該基板21〇之 間間隙H2 ’以全面結合該晶片22〇與該基板2丨〇,並保 護該間隙H2免於受到濕氣與灰塵的污染。而本發明之 該基板210上該些第二銅柱24〇的高度增加有助於該底 〇 部填充膠260之填充速度的控制與填滿效果。 此外’本實施例之柱對柱覆晶結構200係為一微小 化半導體封裝構造。如第4圖所示,該柱對柱覆晶結構 200可另包含設置複數個銲球27〇 ’其係設置在該基板 210之該下表面212,以使載設於該柱對柱覆晶結構2〇〇 之該晶片22〇得與外部印刷電路板(printed circuit board,PCB)達成電性連接關係。該柱對柱覆晶結構2〇〇 係為裸as型態之覆晶封裝構造(fiip_chip,並可 具有球格陣列封裝(Bau Grid Array package)之型態。 201005894 依據本發明之第二具體實施例,另一種柱對柱覆晶 結構舉例說明於第u圖之截面示意圖。該柱對柱覆晶 結構300主要包含一基板21〇、一晶片22〇、複數個第 一銅柱230、複數個第二銅柱24〇以及一焊接材料25〇。 P。其中與第一實施例相同的主要元件將以相同符號標 不’故可以理解亦具有相同功能並能達成上述功效,不 再詳予贅述。 在本實施例中,該些第二銅柱240係可為平錐形, ® 例如半圓錐形或半角錐形。每一第二銅柱240係具有一 頂面342與一底面343,該頂面342之直徑係小於該底 面343之直徑,可使該焊接材料250往位於該晶片220 與該基板2 1 0之間間隙H2的該等分分隔面p集中,以 避免該焊接材料250在該基板210之該些連接墊214上 的擴散污染。故可控制該焊接材料250之用量,並藉由 平錐形之該些第一銅柱230與該些二銅柱240讓焊接材 φ 料250集中在該等分分隔面P’使該焊接材料250不會 擴散到該些連接整214上,而污染了該基板210之該上 表面211 。 此外,該柱對柱覆晶結構300可另包含一封膠體 3 80 ’其係填滿該晶片220與該基板210之間間隙H2 並密封該晶片220、該些第一銅柱230與該些第二銅柱 240。由於該晶片220與該基板210之間間隙H2相較於 習知之間隙為大,可提高銅柱間該些焊接中心點25 1的 最大可承受應力,並有助於該封膠體380的無空隙填 16 201005894 充。 以上所述,僅是太路 俚疋尽發明的較佳實施例而已, 本發明作任何形式上的Jjp Μ 所附申往, 本發明技術方案範圍當依 、明專利範圍為準。任何熟悉本專業的技術人員可 利用上述揭*的技術内容作出些冑更動或修飾為等同 變化的等效實施例,但凡是未脫離本發明技術方案的内 容,依據本發明的技術實質斜以上實施例所作的任何簡 ΟThe difference in warpage of the sheet 220 or the thermal expansion and contraction of the substrate 21 affects the direct stress of the soldering center points 251 and the connecting pads 214 to prevent the solder material 250 from breaking at the soldering center point 251. Therefore, the present invention replaces the conventional solder balls, tin-lead bumps or gold bumps with the first copper pillars 23 〇 and the second copper pillars 240 and the solder material 25 等 corresponding to the contours. The problem of changing the flip-chip gap at high temperatures can meet the requirements of lead-free, high reliability and low manufacturing cost. In addition, the first copper pillars 230 and the second copper pillars 24 may be formed by electroplating. As shown in FIG. 4, the first copper pillars 230 and the second copper pillars 240 may have the same size and shape. For example, in the embodiment, the first copper pillars 230 and the first The two steel columns 240 can be cylindrical (as shown in Fig. 5), but can also be a polygonal column of various shapes without limitation. As shown in FIGS. 10A and 1B, the second copper pillars 2 40 may be octagonal cylinders having a plurality of wall surfaces 241 facing a plurality of corners of the connection pads 214. 214B, the plurality of wall surfaces 241 of the second steel column 24b on the substrate 210 face the corners 21 4B of the connection pads 214, so that the transport pads 214 have excessive excess soldering. Material solid 14 201005894 The area. In addition, the second copper posts 240' of the corner-shaped wall faces 241' facing the corners 214B do not have side corners facing the corners 214B of the connecting pads 214. When the second copper pillars 240 are subjected to stress in a certain direction, they are dispersed in the connecting pads 214, and the corners 214B of the connecting pads 214 are not directly pulled to cause peeling. As shown in FIG. 5, the second copper pillars 24 of the first embodiment are cylindrical, and have the same effect. The second copper pillars 240 are curved toward the corners of the connecting pads 214. The wall surface can also prevent the connection pads 214 from being peeled off by the corners. As shown in FIGS. 4 and 8, after the first copper pillars 230 and the second copper pillars 24 are joined by the solder material 250, the wafer 22 can be filled with a high-flow underfill 260. A gap H2' is formed between the substrate and the substrate 21 to fully integrate the wafer 22 and the substrate 2, and protect the gap H2 from moisture and dust. The increase in the height of the second copper pillars 24 on the substrate 210 of the present invention contributes to the control and filling effect of the filling speed of the underfill filler 260. Further, the pillar-to-column flip-chip structure 200 of the present embodiment is a miniaturized semiconductor package structure. As shown in FIG. 4, the pillar-to-column flip-chip structure 200 may further include a plurality of solder balls 27' disposed on the lower surface 212 of the substrate 210 to enable the pillar-on-column loading on the pillars. The structure 22 of the structure 2 is electrically connected to an external printed circuit board (PCB). The pillar-to-column structure 2 is a bare-as-type flip chip package structure (fiip_chip, and may have a type of Bau Grid Array package). 201005894 According to the second embodiment of the present invention For example, another column-to-column flip-chip structure is illustrated in the cross-sectional view of FIG. 5. The column-to-column flip-chip structure 300 mainly includes a substrate 21〇, a wafer 22〇, a plurality of first copper pillars 230, and a plurality of The second copper post 24〇 and a solder material 25〇. P. The same main elements as those of the first embodiment will be labeled with the same symbols, so that they can be understood and have the same functions and can achieve the above-mentioned effects, and will not be described in detail. In this embodiment, the second copper pillars 240 may be flat cones, such as a semi-conical or a pyramidal shape. Each of the second copper pillars 240 has a top surface 342 and a bottom surface 343. The diameter of the top surface 342 is smaller than the diameter of the bottom surface 343, so that the solder material 250 can be concentrated to the aliquot separating surface p of the gap H2 between the wafer 220 and the substrate 210 to prevent the solder material 250 from being The connection pads 214 of the substrate 210 Diffusion contamination, so that the amount of the solder material 250 can be controlled, and the first copper pillar 230 and the two copper pillars 240 of the flat cone are used to concentrate the solder material φ material 250 on the aliquot separating surface P'. The solder material 250 does not diffuse onto the connection 214 and contaminates the upper surface 211 of the substrate 210. In addition, the pillar-to-column structure 300 may further comprise a colloid 3 80 'filled a gap H2 between the wafer 220 and the substrate 210 and sealing the wafer 220, the first copper pillars 230 and the second copper pillars 240. Since the gap H2 between the wafer 220 and the substrate 210 is compared with the conventional one The gap is large, which can increase the maximum withstand stress of the welding center points 25 1 between the copper pillars, and contribute to the void-free filling of the sealant 380. The above is only the invention of the road. The preferred embodiment of the present invention is in addition to the Jjp 任何 in any form, and the technical scope of the present invention is subject to the scope of the patent. Anyone skilled in the art can utilize the technical content of the above-mentioned disclosure. Make changes or modifications to equivalent changes, etc. Example, but all without departing from the technical content of the present invention, based on the technical spirit of the present invention, any of the above swash simplified example embodiment taken Ο
單修改、等同變化與修飾,均仍屬於本發明技術方案的 範圍内。 ' 【圖式簡單說明】 第1圖:習知覆晶結構於覆晶前的截面示意圖。 第2圖:習知覆晶結構於覆晶後的截面示意圖。 第3圖:習知覆晶結構於覆晶後產生基板翹曲的截面示 意圖。 第4圖:為依據本發明第一具體實施例的一種柱對柱覆 晶結構的截面示意圖。 第5圖:依據本發明第一具體實施例的該柱對柱覆晶結 構中連接墊設有第二銅柱的放大立體示意圖。 第6圖:依據本發明第一具體實施例的該柱對柱覆晶結 構中晶片設有第一銅柱的局部放大截面示意 圖0 第7圖:依據本發明第一具體實施例的該柱對柱覆晶結 構在覆晶前的局部戴面示意圖。 第8圖:依據本發明第一具體實施例的該柱對柱覆晶結 17 201005894The single modification, the equivalent change and the modification are all within the scope of the technical solution of the present invention. ' [Simple description of the drawing] Fig. 1 is a schematic cross-sectional view of a conventional flip-chip structure before flipping. Fig. 2 is a schematic cross-sectional view showing a conventional flip-chip structure after flipping. Fig. 3 is a cross-sectional view showing the warpage of the substrate after the flip chip is crystallized. Fig. 4 is a schematic cross-sectional view showing a column-to-column laminated structure according to a first embodiment of the present invention. Fig. 5 is an enlarged perspective view showing the second copper pillar in the pillar-to-column laminated structure according to the first embodiment of the present invention. 6 is a partially enlarged cross-sectional view showing a first copper pillar of a wafer in a column-on-clade structure according to a first embodiment of the present invention. FIG. 7 is a view showing the column pair according to the first embodiment of the present invention. Schematic diagram of the partial wear of the pillared crystal structure before the flip chip. Figure 8: The column-to-column cladding according to the first embodiment of the present invention 17 201005894
構中在覆晶後的局部截面 第9圖:依據本發明第-具體實施 構在覆晶後產生基板翹曲 第1〇Α與10Β圖:為依據本發明 柱對柱覆 晶結構中另 一變 大立體示 意匿 丨與俯視 圖。 第 11圖:為依據 本發明第二 具體 柱覆晶結 構的 f截面示 意圖 【主要元件符號說明 ] Η1 晶片與基板之 間間 隙 Η2 晶片與基板之 間間 隙 Η3 第二鋼柱高度 D 第二鋼柱直徑 Ρ 等分分隔面 Τ 晶片厚 度 110 基板 111 上表面 114 連接墊 120 晶片 121 主動面 130 銅柱 150 焊接材料 151 知接中λ 2點 200 柱對柱覆晶結構 210 基板 211 上表面 213 防焊層 214 連接墊 214Β角隅 215 開孔 220 晶片 221 主動面 柱對;}且 示意圖。 例的該柱對柱覆晶結 的局部截面示意圖。 第一具體實施例的該 ί匕例的第二銅柱的放 實施例的另一種柱對 112下表面 122銲墊 212下表面 214Α區域 222銲墊 18 201005894 223凸塊下金屬層224保護層 230第一銅柱 240第二銅柱 240’第二銅柱 241壁面 250焊接材料 251焊接中心點 260底部填充膠 270銲球 3 0 0柱對柱覆晶結構 342頂面 343底面 380封膠體FIG. 9 is a partial cross-section after lamination in the structure: according to the first embodiment of the present invention, the substrate warpage is generated after the flip-chip. The first and the tenth are: the other one in the column-on-cladding structure according to the present invention. Larger stereoscopic representations and top views. Figure 11 is a cross-sectional view of a f-section of a second specific pillared crystal structure according to the present invention [Description of main components] Η1 gap between wafer and substrate Η2 gap between wafer and substrate Η3 height of second steel column D second steel column Diameter Ρ equally divided surface 晶片 wafer thickness 110 substrate 111 upper surface 114 connection pad 120 wafer 121 active surface 130 copper column 150 solder material 151 λ 2 point 200 column to column flip chip structure 210 substrate 211 upper surface 213 solder mask Layer 214 connection pad 214 corner 隅 215 opening 220 wafer 221 active face column pair; A partial cross-sectional view of the pillar-to-column junction of the column. Another column pair 112 of the second embodiment of the second embodiment of the second embodiment of the first embodiment of the first embodiment of the second embodiment of the second embodiment of the second embodiment of the second embodiment of the second embodiment of the second embodiment of the second embodiment of the present invention First copper column 240 second copper column 240' second copper column 241 wall surface 250 welding material 251 welding center point 260 bottom filling glue 270 solder ball 3 0 0 column to column flip chip structure 342 top surface 343 bottom surface 380 sealant
1919
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TWI451550B (en) * | 2011-01-14 | 2014-09-01 | Unimicron Technology Corp | Package substrate and method of forming same |
CN105720013A (en) * | 2014-12-02 | 2016-06-29 | 力成科技股份有限公司 | Package-on-package method for semiconductor package for preventing bridging of intermediate conductors |
TWI581345B (en) * | 2010-09-13 | 2017-05-01 | 史達晶片有限公司 | Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in fo-wlcsp |
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JP3704402B2 (en) * | 1996-08-20 | 2005-10-12 | 富士通株式会社 | Face-down bonding semiconductor device and manufacturing method thereof |
US5790377A (en) * | 1996-09-12 | 1998-08-04 | Packard Hughes Interconnect Company | Integral copper column with solder bump flip chip |
US6578784B1 (en) * | 2000-08-14 | 2003-06-17 | Highline Mfg. Inc. | Twine cutting assembly for bale processor |
US6800169B2 (en) * | 2001-01-08 | 2004-10-05 | Fujitsu Limited | Method for joining conductive structures and an electrical conductive article |
TWI273667B (en) * | 2005-08-30 | 2007-02-11 | Via Tech Inc | Chip package and bump connecting structure thereof |
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TWI581345B (en) * | 2010-09-13 | 2017-05-01 | 史達晶片有限公司 | Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in fo-wlcsp |
US9679824B2 (en) | 2010-09-13 | 2017-06-13 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in Fo-WLCSP |
TWI451550B (en) * | 2011-01-14 | 2014-09-01 | Unimicron Technology Corp | Package substrate and method of forming same |
CN105720013A (en) * | 2014-12-02 | 2016-06-29 | 力成科技股份有限公司 | Package-on-package method for semiconductor package for preventing bridging of intermediate conductors |
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