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TWI552265B - 形成孔穴於增進互連結構中以縮短晶粒之間訊號路徑之半導體裝置和方法 - Google Patents

形成孔穴於增進互連結構中以縮短晶粒之間訊號路徑之半導體裝置和方法 Download PDF

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Publication number
TWI552265B
TWI552265B TW099123249A TW99123249A TWI552265B TW I552265 B TWI552265 B TW I552265B TW 099123249 A TW099123249 A TW 099123249A TW 99123249 A TW99123249 A TW 99123249A TW I552265 B TWI552265 B TW I552265B
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Taiwan
Prior art keywords
semiconductor die
semiconductor
interconnect structure
over
encapsulant
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TW099123249A
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English (en)
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TW201108356A (en
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瑞莎Ａ 派蓋菈
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史達晶片有限公司
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Publication of TW201108356A publication Critical patent/TW201108356A/zh
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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Description

形成孔穴於增進互連結構中以縮短晶粒之間訊號路徑之半導體裝置和方法
本發明大體上關於半導體裝置，且更明確地說，係關於在增進互連結構中多個部分之間形成孔穴之半導體裝置和方法。一下方半導體晶粒會被鑲嵌在該孔穴中，以便提供一通往一上方半導體晶粒的短訊號路徑。
在現代的電子產品中經常會發現半導體裝置。半導體裝置會有不同數量與密度的電子組件。離散半導體裝置通常含有一種類型的電子組件，舉例來說，發光二極體(Light Emitting Diode，LED)、小訊號電晶體、電阻器、電容器、電感器、以及功率金屬氧化物半導體場效電晶體(Metal Oxide Semiconductor Field Effect Transistor，MOSFET)。整合半導體裝置典型第含有數百個至數百萬個電子組件。整合半導體裝置的範例包含微控制器、微處理器、電荷耦合裝置(Charged-Coupled Device，CCD)、太陽能電池、以及數位微鏡裝置(Digital Micro-mirror Device，DMD)。
半導體裝置會實施廣泛的功能，例如，高速計算、傳送與接收電磁訊號、控制電子裝置、將太陽光轉換成電能以及產生電視顯示器的視覺投影。在娛樂領域、通訊領域、電力轉換領域、網路領域、電腦領域、以及消費性產品領域中皆會發現半導體裝置。在軍事應用、航空、自動車、工業控制器、以及辦公室設備中同樣會發現半導體裝置。
半導體裝置利用半導體材料的電氣特性。半導體材料的原子結構使得可藉由施加電場或基礎電流或是經由摻雜處理來操縱其導電性。摻雜會將雜質引入至該半導體材料之中，以便操縱及控制該半導體裝置的傳導性。
半導體裝置含有主動式電氣結構與被動式電氣結構。主動式結構(其包含雙極電晶體與場效電晶體)控制電流的流動。藉由改變摻雜程度以及施加電場或基礎電流，該電晶體會提高或限制電流的流動。被動式結構(其包含電阻器、電容器、以及電感器)創造用以實施各式各樣電功能所需要的電壓和電流之間的關係。該等被動式結構與主動式結構會被電連接以形成讓該半導體裝置實施高速計算及其它實用功能的電路。
半導體裝置通常會使用兩種複雜的製程來製造，也就是，前端製造以及後端製造，每一者皆可能涉及數百道步驟。前端製造涉及在一半導體晶圓的表面上形成複數個晶粒。每一個晶粒通常相同並且含有藉由電連接主動式組件和被動式組件而形成的電路。後端製造涉及從已完成的晶圓中單體化裁切個別的晶粒並且封裝該晶粒以提供結構性支撐及環境隔離。
半導體製造的其中一個目標便係製造較小的半導體裝置。較小的裝置典型地會消耗較少電力，具有較高效能，並且能夠更有效地生產。此外，較小的半導體裝置還具有較小的覆蓋面積，這係為較小的末端產品所需要的。藉由改善前端製程可以達成較小的晶粒尺寸，從而導致具有較小以及較高密度之主動式組件和被動式組件的晶粒。後端製程可以藉由改善電互連及封裝材料而導致具有較小覆蓋面積的半導體裝置封裝。
在含有被堆疊在多層上之多個半導體裝置的扇出晶圓程度的晶片級封裝(Fan-Out Wafer Level Chip Scale Package，FO-WLCSP)中的電互連能夠利用導體的直通矽晶穿孔(Through Silicon Via，TSV)、直通孔洞穿孔(Through Hole Via，THV)或是鍍銅導體柱來完成。使用雷射鑽鑿或深反應離子蝕刻(Deep Reactive Ion Etching，DRIE)形成多個穿孔於該晶粒附近的矽質材料或有機材料中。該等穿孔會被傳導材料填充(舉例來說，藉由使用電鍍製程的銅沉積法)以形成該等導體直通矽晶穿孔與直通孔洞穿孔。該等直通矽晶穿孔與直通孔洞穿孔會經由被形成跨越每一個半導體晶粒的增進互連結構來進一步連接。
在高速半導體裝置中，例如在通訊應用中所使用者，該堆疊半導體晶粒必須以快速且有效的方式進行通訊。在習知的扇出晶圓程度的晶片級封裝中，堆疊的晶粒之間的訊號必須被繞送經過多個增進互連層以及該等直通矽晶穿孔和直通孔洞穿孔，這會導致冗長的訊號路徑。較長的訊號路徑會降低該扇出晶圓程度的晶片級封裝的操作速度。此外，該等增進互連層係被形成跨越每一個半導體晶粒，即使在不用於訊號繞送的區域中，故其會造成增加製造材料與成本的不必要結果。
在扇出晶圓程度的晶片級封裝中需要一種高速垂直互連結構。據此，於一實施例中，本發明係一種製造半導體裝置的方法，其包括下面步驟：提供一暫時性載體；鑲嵌一第一半導體晶粒，讓其主動表面朝向該暫時性載體；將一囊封劑沉積在該第一半導體晶粒與暫時性載體的上方；移除該暫時性載體，以便露出該囊封劑的第一側以及該第一半導體晶粒的主動表面；在該第一半導體晶粒的該主動表面上方形成一遮罩層；以及在該囊封劑的該第一側上方形成一第一互連結構。該遮罩層會防止該第一互連結構形成於該第一半導體晶粒的該主動表面上方。該方法還進一步包含下面步驟：移除該遮罩層，以便在該第一半導體晶粒的該主動表面上方形成一孔穴；以及將一第二半導體晶粒鑲嵌在該孔穴中。該第二半導體晶粒會被電連接至該第一半導體晶粒的該主動表面。
於另一實施例中，本發明係一種製造半導體裝置的方法，其包括下面步驟：提供一暫時性載體；鑲嵌一第一半導體晶粒，讓其主動表面朝向該暫時性載體；將一囊封劑沉積在該第一半導體晶粒與暫時性載體的上方；移除該暫時性載體，以便露出該囊封劑的第一側；在該囊封劑的該第一側上方形成一第一互連結構而不會覆蓋該第一半導體晶粒的該主動表面；以及在該第一互連結構中多個部分之間將一半導體組件鑲嵌在該第一半導體晶粒的該主動表面的上方。該半導體組件會被電連接至該第一半導體晶粒的該主動表面。
於另一實施例中，本發明係一種製造半導體裝置的方法，其包括下面步驟：提供一第一半導體晶粒；將一囊封劑沉積在該第一半導體晶粒的上方；在該囊封劑的上方形成一第一互連結構而不會覆蓋該第一半導體晶粒的主動表面；以及在該第一互連結構中多個部分之間將一半導體組件鑲嵌在該第一半導體晶粒的該主動表面的上方。該半導體組件會被電連接至該第一半導體晶粒的該主動表面。
於另一實施例中，本發明係一種半導體裝置，其包括一第一半導體晶粒以及被沉積在該第一半導體晶粒上方的囊封劑。一第一互連結構會被形成在該囊封劑的上方而不會覆蓋該第一半導體晶粒的主動表面。一半導體組件會在該第一互連結構中多個部分之間被鑲嵌在該第一半導體晶粒的該主動表面的上方。該半導體組件會被電連接至該第一半導體晶粒的該主動表面。
下面的說明書中會參考圖式於一或多個實施例中來說明本發明，於該等圖式中，相同的符號代表相同或相似的元件。雖然本文會以達成本發明目的的最佳模式來說明本發明；不過，熟習本技術的人士便會明白，本發明希望涵蓋受到下面揭示內容及圖式支持的隨附申請專利範圍及它們的等效物所定義的本發明的精神與範疇內可能併入的替代、修正以及等效物。
半導體裝置通常會使用兩種複雜的製程來製造：前端製造和後端製造。前端製造涉及在一半導體晶圓的表面上形成複數個晶粒。該晶圓上的每一個晶粒皆含有主動式電子組件和被動式電子組件，它們會被電連接而形成功能性電路。主動式電子組件(例如電晶體與二極體)能夠控制電流的流動。被動式電子組件(例如電容器、電感器、電阻器、以及變壓器)會創造用以實施電路功能所需要的電壓和電流之間的關係。
被動式組件和主動式組件會藉由一連串的製程步驟被形成在該半導體晶圓的表面上方，該等製程步驟包含：摻雜、沉積、光微影術、蝕刻、以及平坦化。摻雜會藉由離子植入或是熱擴散將雜質引入至半導體材料之中。摻雜製程會修改主動式裝置中半導體材料的導電性，將該半導體材料轉換成絕緣體、導體，或是響應於電場或基礎電流來動態改變半導體材料傳導性。電晶體含有摻雜的不同類型和程度的範圍，參雜安排為必要的，以在施加一電場或基礎電流時讓該電晶體會提高或限制電流的流動。
主動式組件和被動式組件係由具有不同電氣特性的多層材料構成。該等層能夠藉由各式各樣的沉積技術來形成，其某種程度上取決於要被沉積的材料的類型。舉例來說，薄膜沉積可能包含：化學氣相沉積(Chemical Vapor Deposition，CVD)製程、物理氣相沉積(Physical Vapor Deposition，PVD)製程、電解質電鍍製程、以及無電極電鍍製程。每一層通常都會被圖樣化，以便形成主動式組件、被動式組件、或是組件之間的電連接線的一部分。
該等層能夠利用光微影術來圖樣化，其涉及在要被圖樣化的層的上方沉積光敏材料，舉例來說，光阻。圖樣會利用光從一光罩處被轉印至該光阻。該光阻圖樣中受到光作用的部分會利用溶劑移除，從而露出下方層之中要被圖樣化的部分。該光阻中的剩餘部分會被移除，從而留下一已圖樣化層。或者，某些類型的材料會利用無電極電鍍以及電解質電鍍之類的技術，藉由將該材料直接沉積至先前沉積及/或蝕刻製程所形成的區域或空隙(void)之中而被圖樣化。
在一既有圖樣的上方沉積一薄膜材料可能會擴大下方圖樣並且產生一不均勻平坦的表面。生產較小且更密集封裝的主動式組件和被動式組件需要用到均勻平坦的表面。平坦化作用可用來從晶圓的表面處移除材料，並且產生均勻平坦的表面。平坦化作用涉及利用一研磨墊來研磨晶圓的表面。在研磨期間加入研磨材料以及腐蝕性的化學藥劑到晶圓的表面。結合研磨料的機械作用及化學藥劑的磨蝕作用來移除任何不規律的表面形狀，從而產生均勻平坦的表面。
後端製造係指將已完成的晶圓切割或單體化裁切成個別晶粒，並且接著封裝該晶粒，以達結構性支撐及環境隔離的效果。為單體化裁切晶粒，晶圓會沿著該晶圓中被稱為切割道(saw street)或切割線(scribe)的非功能性區域被刻痕並且折斷。該晶圓會利用雷射切割工具或鋸片來進行單體化裁切。經過單體化裁切之後，個別晶粒便會被鑲嵌至包含接針或接觸觸墊的封裝基板，以便和其它系統組件進行互連。被形成在該半導體晶粒上方的接觸觸墊接著會被連接至該封裝裡面的接觸觸墊。該等電連接線可利用焊料凸塊、短柱凸塊、導電膏、或是焊線來製成。一囊封劑或是其它模造材料會被沉積在該封裝的上方以提供物理性支撐和電隔離。接著，該已完成的封裝便會被插入一電氣系統之中並且讓其它系統組件可取用該半導體裝置的功能。
圖1說明一電子裝置50，其具有一晶片載體基板或是印刷電路板(PCB)52，其表面上鑲嵌複數個半導體封裝。電子裝置50可能係某一類型的半導體封裝或是多種類型的半導體封裝，端視應用而定。為達解釋目的，圖1中顯示不同類型的半導體封裝。
電子裝置50可能係一獨立系統，其會使用該等半導體封裝來實施一或多項電功能。或者，電子裝置50亦可能係一較大型系統中的一子組件。舉例來說，電子裝置50可能係一圖形卡、一網路介面卡、或是能夠被插入在一電腦之中的其它訊號處理卡。該半導體封裝可能包含：微處理器、記憶體、特定應用積體電路(Application Specific Integrated Circuits，ASIC)、邏輯電路、類比電路、射頻電路、離散式裝置、或是其它半導體晶粒或電子組件。
在圖1中，印刷電路板52提供一通用基板，用以結構性支撐及電互連被鑲嵌在該印刷電路板之上的半導體封裝。利用蒸發製程、電解質電鍍製程、無電極電鍍製程、網印製程、或是其它合宜的金屬沉積製程形成導體訊號線路54於印刷電路板52的一表面上方或是多層裡面。訊號線路54在該等半導體封裝、被鑲嵌的組件、以及其它外部系統組件中的每一者之間提供電通訊。線路54還會提供連接至每一個該等半導體封裝的電力連接線及接地連接線。
於某些實施例中，一半導體裝置會有兩個封裝層。第一層封裝係一種以機械方式及電氣方式將該半導體晶粒附接至一中間載體的技術。第二層封裝則涉及以機械方式及電氣方式將該中間載體附接至該印刷電路板。於其它實施例中，一半導體裝置可能僅有該第一層封裝，其中，該晶粒會以機械方式及電氣方式直接被鑲嵌至該印刷電路板。
為達解釋目的，顯示在印刷電路板52上之數種類型的第一層封裝，其包含焊線封裝56以及覆晶58。除此之外，還顯示被鑲嵌在印刷電路板52上之數種類型之第二層封裝，其包含：球柵陣列(Ball Grid Array，BGA)60；凸塊晶片載體(Bump Chip Carrier，BCC)62；雙直列封裝(Dual In-line Package，DIP)64；平台格柵陣列(Land Grid Array，LGA)66；多晶片模組(Multi-Chip Module，MCM)68；方形扁平無導線封裝(Quad Flat Non-leaded package，QFN)70；以及方形扁平封裝72。端視系統需求而定，任何半導體封裝之組合、任何結合第一及第二層封裝形式之組合和其他電子組件皆能夠被連接至印刷電路板52。於某些實施例中，電子裝置50包含單一附接半導體封裝；而其它實施例則要求多個互連封裝。藉由在單一基板上方組合一或多個半導體封裝，製造商便能夠將事先製造的組件併入電子裝置和系統之中。因為該等半導體封裝包含精密的功能，所以電子裝置能夠使用較便宜的組件及有效率的製程來製造。所產生的裝置比較不可能失效而且製造價格較低廉，從而讓消費者的成本會較低。
圖2a至2c所示的係示範性半導體封裝。圖2a所示的係被鑲嵌在印刷電路板52之上的DIP 64的進一步細節。半導體晶粒74包含一含有類比電路或數位電路的主動區，該等類比電路或數位電路會被執行為形成在該晶粒裡面的主動式裝置、被動式裝置、導體層、以及介電層，並且會根據該晶粒的電氣設計來進行電互連。舉例來說，該電路可能包含被形成在半導體晶粒74之主動區裡面的一或多個電晶體、二極體、電感器、電容器、電阻器、以及其它電路元件。接觸觸墊76係一或多層傳導材料(例如鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、或是銀(Ag))製成，並且會被電連接至形成在半導體晶粒74裡面的電路元件。在DIP 64的組裝期間，半導體晶粒74會利用一金-矽共熔合金層或是膠黏材料(例如熱環氧樹脂)被黏著至一中間載體78。封裝主體包含一絕緣封裝材料，例如聚合物或是陶瓷。導體導線80以及焊線82會在半導體晶粒74與印刷電路板52之間提供電互連。囊封劑84會被沉積在該封裝的上方，防止濕氣和粒子進入該封裝並污染晶粒74或焊線82以達環境保護的目的。
圖2b所示的係被鑲嵌在印刷電路板52之上的BCC 62的進一步細節。半導體晶粒88會利用底層填充材料或環氧樹脂膠黏材料92被黏著在載體90的上方。焊線94會在接觸觸墊96與98之間提供第一層封裝互連。模造化合物或囊封劑100會被沉積在半導體晶粒88和焊線94的上方，用以為該裝置提供物理性支撐以及電隔離效果。接觸觸墊102會利用合宜的金屬沉積製程(例如電解質電鍍或無電極電鍍)被形成在印刷電路板52的表面上方以防止氧化。接觸觸墊102會被電連接至印刷電路板52中的一或多條導體訊號線路54。凸塊104會被形成在BCC 62的接觸觸墊98和印刷電路板52的接觸觸墊102之間。
在圖2c中，半導體晶粒58會利用覆晶樣式的第一層封裝以面朝下的方式被鑲嵌至中間載體106。半導體晶粒58的主動區108含有類比電路或數位電路，該等類比電路或數位電路會被執行為根據該晶粒的電氣設計所形成的主動式裝置、被動式裝置、導體層、以及介電層。舉例來說，該電路可能包含在主動區108裡面的一或多個電晶體、二極體、電感器、電容器、電阻器、以及其它電路元件。半導體晶粒58會經由凸塊110以電氣方式及機械方式連接至載體106。
BGA 60會利用凸塊112的BGA樣式第二層封裝以電氣方式及機械方式被連接至印刷電路板52。半導體晶粒58會經由凸塊110、訊號線114、以及凸塊112被電連接至印刷電路板52中的導體訊號線路54。一模造化合物或囊封劑116會被沉積在半導體晶粒58和載體106的上方，以為該裝置提供物理性支撐以及電隔離效果。該覆晶半導體裝置從半導體晶粒58上的主動式裝置至印刷電路板52上的傳導軌提供一條短的電傳導路徑，以便縮短訊號傳導距離、降低電容、並且改善整體電路效能。於另一實施例中，該半導體晶粒58會利用覆晶樣式的第一層封裝以機械方式及電氣方式直接連接至印刷電路板52，而沒有中間載體106。
圖3a至3g所示的係和圖1及2a至2c有關之在扇出晶圓程度的晶片級封裝中為達上下堆疊半導體晶粒之間的短訊號路徑於該增進互連結構的多個部分之間形成一孔穴的製程。在圖3a中，一晶圓形狀的基板或載體120含有暫時性或犧牲性基礎材料，例如，矽、聚合物、聚合復合物、金屬、陶瓷、玻璃、玻璃環氧樹脂、氧化鈹、或是其它合宜的低成本剛性材料或大型半導體材料，用以達到結構性支撐的目的。載體120亦可能為膠帶。於一實施例中，載體120的直徑為20.3公分(cm)。一非必要的介面層122可能會被形成在載體120的上方，成為一暫時性的焊接膜或是蝕刻阻止層。
半導體晶粒或組件124會被鑲嵌至介面層122，主動表面128上的接觸觸墊126向下朝向載體120。主動表面128含有類比電路或數位電路，該等類比電路或數位電路被執行作為被形成在該晶粒裡面的主動式裝置、被動式裝置、導體層、以及介電層，並且會根據該晶粒的電氣設計與功能來進行電互連。舉例來說，該電路可能包含被形成在主動表面128裡面的一或多個電晶體、二極體、以及其它電路元件，用以執行類比電路或數位電路，例如，數位訊號處理器(Digital Signal Processor，DSP)、ASIC、記憶體、或是其它訊號處理電路。半導體晶粒124可能還含有用於射頻訊號處理的整合被動元件(IPD)，例如，電感器、電容器、以及電阻器。一典型的射頻系統在一或多個半導體封裝中需要用到多個整合被動元件，用以實施必要的電功能。
在圖3b中，一囊封劑或模造化合物130會利用焊膏印刷(paste printing)塗敷機、壓縮模造(compressive molding)塗敷機、轉印模造(transfer molding)塗敷機、液體囊封劑模造塗敷機、真空層疊塗敷機、或是其它合宜的塗敷機被沉積在半導體晶粒124的上方。囊封劑130可能係聚合物復合材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯、或是具有適當填充劑的聚合物。囊封劑130係非導體並且會為半導體裝置提供環境保護，避免受到外部元素與污染物破壞。
在圖3c中，載體120與非必要的介面層122會藉由化學性蝕刻、機械性剝離、CMP、機械性研磨、熱烘烤、雷射掃描或是濕式剝除之方式被移除。一遮罩層132會於接觸觸墊126之間被形成在主動表面128的上方。
在圖3d中，一底邊增進互連結構134被形成在半導體晶粒124和囊封劑130的上方。該增進互連結構134包含一絕緣層或鈍化層136，其含有由下面所製成的一或多層：二氧化矽(SiO2)、氮化矽(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、三氧化二鋁(Al2O3)或是具有相似絕緣特性及結構性特性的其它材料。該絕緣層136係利用PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化之方法所形成。
該底邊增進互連結構134還進一步包含一導電層138，其使用圖樣化與金屬沉積製程(例如PVD、CVD、濺鍍、電解質電鍍、以及無電極電鍍)而形成在絕緣層136中。導體層138可能係由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。導體層138中的一部分會被電連接至半導體晶粒124的接觸觸墊126。導體層138中的其它部分可能為共電或被電隔離，端視該半導體裝置的設計及功能而定。
遮罩層132會防止增進互連結構134形成於半導體晶粒124之主動表面128的上方。遮罩層132會在圖3e中從半導體晶粒124的底邊處被移除，留下露出主動表面128的孔穴140。
在圖3f中，半導體晶粒或組件142會在增進互連結構134的多個部分之間被鑲嵌在孔穴140內，用以接觸主動表面128上的觸墊，其中，接觸觸墊144會朝上。凸塊146會在接觸觸墊144及主動表面128之間提供電連接作用。半導體晶粒142包含一含有類比電路或數位電路的主動表面，該等類比電路或數位電路會被執行作為形成在該晶粒裡面的主動式裝置、被動式裝置、導體層、以及介電層，並且會根據該晶粒的電氣設計與功能來進行電互連。舉例來說，該電路可能包含被形成在主動表面裡面的一或多個電晶體、二極體以及其它電路元件，以施行類比電路或數位電路，例如，數位訊號處理器、ASIC、記憶體或是其它訊號處理電路。半導體晶粒142可能還含有用於射頻訊號處理的整合被動元件，例如，電感器、電容器、以及電阻器。一典型的射頻系統在一或多個半導體封裝中需要用到多個整合被動元件，用以實施必要的電功能。
一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程(ball drop)、或是網印製程被沉積在增進互連結構134的上方並且會被電連接至導體層138。該凸塊材料可能係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及它們的組合，具有一非必要的助熔溶劑。舉例來說，該凸塊材料可能是Sn/Pb共熔合金、高鉛焊料、或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程被焊接至導體層138。於一實施例中，該凸塊材料會藉由將該凸塊材料加熱至其熔點以上而被回焊，用以形成球狀的丸體或凸塊148。於某些應用中，凸塊148會被二次回焊，以便改善和導體層138的電接觸效果。該等凸塊也能夠被壓縮焊接至導體層138。凸塊148代表能夠被形成在導體層138上方的其中一種類型的互連結構。該互連結構亦能夠使用焊線、短柱凸塊、微凸塊、或是其它電互連線。
在圖3g中，一底層填充材料150(例如環氧樹脂)會被沉積在半導體晶粒124與142之間。半導體晶粒124會利用鋸片或雷射切割裝置152被單體化裁切成個別的半導體裝置。
圖4所示的係在單體化裁切之後的扇出晶圓程度的晶片級封裝154。半導體晶粒142會利用遮罩層132被鑲嵌在形成於底邊增進互連結構134中多個部分之間的孔穴140之中。半導體晶粒124與142會利用凸塊146進行電互連。藉由將半導體晶粒142放置在孔穴140中，晶粒之間的分隔距離便會縮短，從而會導致短且有效的訊號路徑，用以改善扇出晶圓程度的晶片級封裝154的電氣效能並且提高操作速度。半導體晶粒142的高度(包含凸塊146在內)小於凸塊148的高度。利用上面新穎的製程與結構會降低扇出晶圓程度的晶片級封裝154的總高度。
在圖5中，囊封劑130中的一部分會藉由蝕刻製程被移除，以便露出半導體晶粒124的背表面156。
在圖6中，囊封劑130中的一部分會藉由蝕刻製程被移除，以便露出半導體晶粒124的背表面156。複數個穿孔會利用雷射鑽鑿或蝕刻製程(例如DRIE)被形成貫穿半導體晶粒124。該等穿孔會利用PVD、CVD、電解質電鍍、無電極電鍍製程、或是其它合宜的金屬沉積製程被Al、Cu、Sn、Ni、Au、Ag、鈦(Ti)、W、多晶矽、或是其它合宜的導電材料填充，以便形成導體直通矽晶穿孔158。直通矽晶穿孔158會在圖3a中將半導體晶粒124鑲嵌至介面層122之前被形成在該晶粒中。直通矽晶穿孔158會根據晶粒的設計來進行電互連。
圖7所示的係利用焊膏印刷塗敷機、壓縮模造塗敷機、轉印模造塗敷機、液體囊封劑模造塗敷機、真空層疊塗敷機或是其它合宜的塗敷機而被沉積在半導體晶粒142上方與周圍的囊封劑或模造化合物160。囊封劑160可能係聚合物復合材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯、或是具有適當填充劑的聚合物。囊封劑160係非導體並且會為半導體裝置提供環境保護，避免受到外部元素與污染物破壞。
在圖8中，囊封劑130中的一部分會被移除，以便露出半導體晶粒124的背表面156。一熱介面材料(Thermal Interface Material，TIM)162會被沉積在半導體晶粒124的背表面156上方，在主動表面128的對面。熱介面材料162可能係：氧化鋁、氧化鋅、氮化硼、或是粉銀(pulverized silver)。一散熱片164會被鑲嵌在熱介面材料162及囊封劑130的上方。散熱片164可能係Al、Cu、或是具有高導熱係數的另一材料，以便為半導體晶粒124提供熱消散作用。熱介面材料162有助於分佈與消散半導體晶粒124所產生的熱。
在圖9中，囊封劑130中的一部分會藉由蝕刻製程被移除，以便露出半導體晶粒124的背表面156。複數個穿孔會利用雷射鑽鑿或蝕刻製程(例如DRIE)被形成貫穿半導體晶粒124。該等穿孔會利用PVD、CVD、電解質電鍍、無電極電鍍製程、或是其它合宜的金屬沉積製程被Al、Cu、Sn、Ni、Au、Ag、Ti、W、多晶矽、或是其它合宜的導電材料填充，以便形成導體直通矽晶穿孔170。直通矽晶穿孔170會在將半導體晶粒124鑲嵌至圖3a中之介面層122之前被形成在該晶粒中。直通矽晶穿孔170會根據晶粒的設計來進行電互連。
熱介面材料172會被沉積在半導體晶粒124的背表面156上方，在主動表面128的對面。熱介面材料172可能係：氧化鋁、氧化鋅、氮化硼、或是粉銀。一散熱片174會被鑲嵌在熱介面材料172及囊封劑130的上方。散熱片174可能係Al、Cu、或是具有高導熱係數的另一材料，以便為半導體晶粒124提供熱消散作用。熱介面材料172有助於分佈與消散半導體晶粒124所產生的熱。
圖10所示的係被形成在半導體晶粒142上方的一遮蔽層176。遮蔽層176可能係Cu、Al、鐵氧體或羰基鐵(carbonyl iron)、不鏽鋼、鎳銀合金、低碳鋼、矽鐵鋼(silicon-iron steel)、金屬箔、環氧樹脂、導體樹脂以及能夠阻隔或吸收電磁干擾(ElectroMagnetic Interference，EMI)、射頻干擾(Radio Frequency Interference，RFI)、以及其它裝置間干擾的其它金屬與復合物。遮蔽層176亦可能係非金屬材料，例如，碳黑或鋁質薄片，用以降低電磁干擾與射頻干擾的效應。遮蔽層176會經由導體層178被接地至凸塊148。
圖11所示的係多個被動組件180，它們會被鑲嵌至孔穴140中主動表面128上的接觸觸墊。被動組件180可能係電阻器、電容器、電感器、或是離散主動裝置。
在圖12中，複數個穿孔會利用雷射鑽鑿或蝕刻製程(例如DRIE)被形成貫穿囊封劑130。該等穿孔會利用PVD、CVD、電解質電鍍、無電極電鍍製程、或是其它合宜的金屬沉積製程被Al、Cu、Sn、Ni、Au、Ag、Ti、W、多晶矽、或是其它合宜的導電材料填充，以便形成導體直通孔洞穿孔182。或者，導體柱182會在沉積囊封劑130之前被形成在半導體晶粒124的周圍。直通矽晶穿孔170會根據晶粒的設計來進行電互連。導體柱182係藉由下面的方式構成：沉積一光阻層；在該光阻中蝕刻多個穿孔；利用傳導材料填充該等穿孔；以及移除該光阻層，留下該等導體柱。
一頂邊增進互連結構184會被形成在囊封劑130的上方。該增進互連結構184包含一絕緣層或鈍化層186，其含有由下面所製成的一或多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3或是具有相似絕緣特性及結構性特性的其它材料。該絕緣層186係利用PVD、CVD、印刷、旋塗、噴塗、燒結或是熱氧化之方法形成。
該頂邊增進互連結構184還進一步包含一導電層188，其使用圖樣化與金屬沉積製程(例如PVD、CVD、濺鍍、電解質電鍍、以及無電極電鍍)被形成在絕緣層186中。導體層188可能係由Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料所製成的一或多層。導體層188中的一部分會被電連接至導體穿孔182。導體層188中的其它部分可能為共電或被電隔離，端視該半導體裝置的設計及功能而定。導體穿孔182係介於底邊增進互連結構134和頂邊增進互連結構184之間的z方向互連線。
一半導體晶粒或組件190會利用凸塊192被鑲嵌至增進互連結構184。半導體晶粒190包含一含有類比電路或數位電路的主動表面193，該等類比電路或數位電路會被執行作為形成在該晶粒裡面的主動式裝置、被動式裝置、導體層、以及介電層，並且會根據該晶粒的電氣設計與功能來進行電互連。舉例來說，該電路可能包含被形成在主動表面193裡面的一或多個電晶體、二極體、以及其它電路元件，用以施行類比電路或數位電路，例如，數位訊號處理器、ASIC、記憶體、或是其它訊號處理電路。半導體晶粒190可能還含有用於射頻訊號處理的整合被動元件，例如，電感器、電容器、以及電阻器。一典型的射頻系統在一或多個半導體封裝中需要用到多個整合被動元件，用以實施必要的電功能。一底層填充材料194(例如環氧樹脂)會被沉積在半導體晶粒190的下面。
圖13所示的係位於孔穴140中的熱分散器196，其會利用凸塊198被鑲嵌至半導體晶粒124的主動表面128。熱分散器196會分佈與消散半導體晶粒124所產生的熱。
圖14a至14i所示的係在扇出晶圓程度的晶片級封裝中為達上下堆疊半導體晶粒之間的短訊號路徑於該增進互連結構的多個部分之間形成一孔穴的另一製程。在圖14a中，一晶圓形狀的基板或載體200含有暫時性或犧牲性基礎材料，例如，矽、聚合物、聚合復合物、金屬、陶瓷、玻璃、玻璃環氧樹脂、氧化鈹、或是其它合宜的低成本剛性材料或大型半導體材料，用以達到結構性支撐的目的。載體200亦可能為膠帶。於其中一實施例中，載體200的直徑為20.3cm。一非必要的介面層202可能會被形成在載體200的上方，成為一暫時性的焊接膜或是蝕刻阻止層。複數個非必要的可潤濕觸墊可能會被形成在載體200的上方。複數個屏障壁(dam wall)204會被沉積在介面層202的上方，以便在要放置半導體晶粒208之主動表面的指定區域附近形成一包體。
在圖14b中，多個凸塊206會被形成在介面層202之上。半導體晶粒或組件208會被鑲嵌在凸塊206的上方，主動表面212上的接觸觸墊210會向下朝向載體200。或者，凸塊206亦能夠在將半導體晶粒208鑲嵌至載體200之前被形成在接觸觸墊210之上。主動表面212含有類比電路或數位電路，該等類比電路或數位電路會被執行作為形成在該晶粒裡面的主動式裝置、被動式裝置、導體層、以及介電層，並且會根據該晶粒的電氣設計與功能來進行電互連。舉例來說，該電路可能包含被形成在主動表面212裡面的一或多個電晶體、二極體、以及其它電路元件，用以施行類比電路或數位電路，例如，數位訊號處理器、ASIC、記憶體、或是其它訊號處理電路。半導體晶粒208可能還含有用於射頻訊號處理的整合被動元件，例如，電感器、電容器、以及電阻器。一典型的射頻系統在一或多個半導體封裝中需要用到多個整合被動元件，用以實施必要的電功能。
圖14c所示的係鑲嵌至介面層202上方凸塊206的半導體晶粒208的接觸觸墊210。凸塊206的高度約和屏障壁204的高度相同。屏障壁204會在介面層202與主動表面212之間在指定為主動表面212的區域附近形成一密封包體。
在圖14d中，一囊封劑或模造化合物214會利用焊膏印刷塗敷機、壓縮模造塗敷機、轉印模造塗敷機、液體囊封劑模造塗敷機、真空層疊塗敷機或是其它合宜的塗敷機被沉積在半導體晶粒208的上方。囊封劑214可能係聚合物復合材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯、或是具有適當填充劑的聚合物。囊封劑214係非導體並且會為半導體裝置提供環境保護，避免受到外部元素與污染物破壞。由屏障壁204所形成的包體會提供一密封體，用以防止囊封劑214分散至主動表面212位於接觸觸墊210之間的內部部分。據此，屏障壁204會在半導體晶粒208的主動表面212下方形成孔穴216。
在圖14e中，載體200與非必要的介面層202會藉由化學性蝕刻、機械性剝離、CMP、機械性研磨、熱烘烤、雷射掃描或是濕式剝除之方式被移除。一遮罩層218會於接觸觸墊210之間被形成在主動表面212上方的孔穴216中。
在圖14f中，一底邊增進互連結構220會被形成在半導體晶粒208和囊封劑214的上方。該增進互連結構220包含一絕緣層或鈍化層222，其含有由SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是具有相似絕緣特性及結構性特性的其它材料之一或多層所製成：。該絕緣層222係利用PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化之方法所形成。
該底邊增進互連結構220還進一步包含一導電層224，其使用圖樣化與金屬沉積製程(例如PVD、CVD、濺鍍、電解質電鍍、以及無電極電鍍)被形成在絕緣層222中。導體層224可能係由Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料的一或多層所製成。導體層224中的一部分會經由凸塊206被電連接至半導體晶粒208的接觸觸墊210。導體層224中的其它部分可能為共電或被電隔離，端視該半導體裝置的設計及功能而定。
遮罩層218會防止增進互連結構220形成於半導體晶粒208之主動表面212的上方。遮罩層218會在圖14g中從半導體晶粒208的底邊處被移除，留下露出主動表面212的孔穴226。
在圖14h中，半導體晶粒或組件230會在增進互連結構220的多個部分之間被鑲嵌在孔穴226內，用以接觸主動表面212上的觸墊，其中，接觸觸墊232會朝上。凸塊234會在接觸觸墊232及主動表面212之間提供電連接作用。屏障壁204和遮罩層218的組合會提供一更深的孔穴226，用以容納具有較大厚度的半導體晶粒230。半導體晶粒230包含一含有類比電路或數位電路的主動表面，該等類比電路或數位電路會被執行作為形成在該晶粒裡面的主動式裝置、被動式裝置、導體層、以及介電層，並且會根據該晶粒的電氣設計與功能來進行電互連。舉例來說，該電路可能包含被形成在主動表面裡面的一或多個電晶體、二極體、以及其它電路元件，用以施行類比電路或數位電路，例如，數位訊號處理器、ASIC、記憶體、或是其它訊號處理電路。半導體晶粒230可能還含有用於射頻訊號處理的整合被動元件，例如，電感器、電容器、以及電阻器。一典型的射頻系統在一或多個半導體封裝中需要用到多個整合被動元件，用以實施必要的電功能。
一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程、或是網印製程被沉積在增進互連結構220的上方並且會被電連接至導體層224。該凸塊材料可能係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及它們的組合，具有一非必要的助熔溶劑。舉例來說，該凸塊材料可能是Sn/Pb共熔合金、高鉛焊料、或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程被焊接至導體層224。於一實施例中，該凸塊材料會藉由將該凸塊材料加熱至其熔點以上而被回焊，用以形成球狀的丸體或凸塊236。於某些應用中，凸塊236會被二次回焊，以便改善和導體層224的電接觸效果。該等凸塊也能夠被壓縮焊接至導體層224。凸塊236代表能夠被形成在導體層224上方的其中一種類型的互連結構。該互連結構亦能夠使用焊線、短柱凸塊、微凸塊、或是其它電互連線。
在圖14i中，一底層填充材料238(例如環氧樹脂)會被沉積在半導體晶粒208與230之間。半導體晶粒208與230會利用鋸片或雷射切割裝置240被單體化裁切成個別的半導體裝置。
圖15所示的係在單體化裁切之後的扇出晶圓程度的晶片級封裝242。半導體晶粒230會利用屏障壁204與遮罩層218被鑲嵌在形成於底邊增進互連結構220中多個部分之間的孔穴226之中。半導體晶粒208與230會利用凸塊234進行電互連。藉由將半導體晶粒230放置在孔穴226中，晶粒之間的分隔距離便會縮短，從而會導致短且有效的訊號路徑，用以改善扇出晶圓程度的晶片級封裝242的電氣效能並且提高操作速度。半導體晶粒230的高度(包含凸塊234在內)小於凸塊236的高度。利用上面新穎的製程與結構會降低扇出晶圓程度的晶片級封裝242的總高度。
圖5至13中所示的各個實施例皆可應用至圖15。
雖然本文已經詳細解釋過本發明的一或多個實施例；不過，熟練的技術人士便會瞭解，可以對該些實施例進行修正與改變，其並不會脫離隨後申請專利範圍中所提出的本發明的範疇。
50．．．電子裝置
52．．．印刷電路板(PCB)
54．．．線路
56．．．焊線封裝
58．．．覆晶
60．．．球柵陣列(BGA)
62．．．凸塊晶片載體(BCC)
64．．．雙直列封裝(DIP)
66．．．平台格柵陣列(LGA)
68．．．多晶片模組(MCM)
70．．．方形扁平無導線封裝(QFN)
72．．．方形扁平封裝
74．．．半導體晶粒
76．．．接觸觸墊
78．．．中間載體
80．．．導體導線
82．．．焊線
84．．．囊封劑
88．．．半導體晶粒
90．．．載體
92．．．底層填充材料或環氧樹脂膠黏材料
94．．．焊線
96．．．接觸觸墊
98．．．接觸觸墊
100．．．模造化合物或囊封劑
102．．．接觸觸墊
104．．．凸塊
106．．．載體
108．．．主動區
110．．．凸塊
112．．．凸塊
114．．．訊號線
116．．．模造化合物或囊封劑
120．．．基板或載體
122．．．介面層
124．．．半導體晶粒或組件
126．．．接觸觸墊
128．．．主動表面
130．．．囊封劑或模造化合物
132．．．遮罩層
134．．．互連結構
136．．．絕緣層或鈍化層
138．．．導電層
140．．．孔穴
142．．．半導體晶粒或組件
144．．．接觸觸墊
146．．．凸塊
148．．．球狀的丸體或凸塊
150．．．底層填充材料
152．．．鋸片或雷射切割裝置
154．．．扇出晶圓程度的晶片級封裝(FO-WLCSP)
156．．．背表面
158．．．直通矽晶穿孔
160．．．囊封劑或模造化合物
162．．．熱介面材料(TIM)
164．．．散熱片
170．．．直通矽晶穿孔
172．．．熱介面材料
174．．．散熱片
176．．．遮蔽層
178．．．導體層
180．．．被動組件
182．．．導體直通孔洞穿孔(THV)或導體柱
184．．．互連結構
186．．．鈍化層
188．．．導體層
190．．．半導體晶粒或組件
192．．．凸塊
193．．．主動表面
194．．．底層填充材料
196．．．熱分散器
198．．．凸塊
200．．．基板或載體
202．．．介面層
204．．．屏障壁
206．．．凸塊
208．．．半導體晶粒
210．．．接觸觸墊
212．．．主動表面
214．．．囊封劑或模造化合物
216．．．孔穴
218．．．遮罩層
220．．．互連結構
222．．．絕緣層或鈍化層
224．．．導體層
226．．．孔穴
230．．．半導體晶粒或組件
232．．．接觸觸墊
234．．．凸塊
236．．．球狀的丸體或凸塊
238．．．底層填充材料
240．．．鋸片或雷射切割裝置
242．．．扇出晶圓程度的晶片級封裝
圖1說明一印刷電路板，在其表面上鑲嵌著不同類型的封裝；
圖2a至2c說明被鑲嵌至該印刷電路板的代表性半導體封裝的進一步細節；
圖3a至3g說明為達上下堆疊晶粒之間的短訊號路徑於該增進互連結構的多個部分之間形成一孔穴的製程；
圖4說明在上下堆疊半導體晶粒之間具有短訊號路徑的扇出晶圓程度的晶片級封裝；
圖5說明已露出的上方半導體晶粒的背表面；
圖6說明被形成貫穿該上方半導體晶粒的一直通矽晶穿孔；
圖7說明被形成在該下方半導體晶粒周圍的一囊封劑；
圖8說明被形成在該上方半導體晶粒上方的一熱介面材料與散熱片；
圖9說明直通矽晶穿孔被形成貫穿於形成在該上方半導體晶粒上方之熱介面材料與散熱片；
圖10說明被形成在該下方半導體晶粒周圍的一EMI遮蔽層；
圖11說明一離散半導體組件，其會被鑲嵌在該孔穴中並且被附接至該上方晶粒；
圖12說明位於該上方半導體晶粒上方的一頂邊增進互連結構與額外的半導體晶粒；
圖13說明一熱分散器，其會被鑲嵌在該孔穴中並且被附接至該上方半導體晶粒；
圖14a至14i說明為達上下堆疊半導體晶粒之間的短訊號路徑於該增進互連結構中形成一孔穴的另一製程；以及
圖15說明在上下堆疊半導體晶粒之間具有短訊號路徑的扇出晶圓程度的晶片級封裝。
24．．．半導體晶粒或組件
26．．．接觸觸墊
28．．．主動表面
30．．．囊封劑或模造化合物
34．．．互連結構
36．．．絕緣層或鈍化層
38．．．導電層
42．．．半導體晶粒或組件
44．．．接觸觸墊
46．．．凸塊
48．．．球狀的丸體或凸塊
50．．．底層填充材料
54．．．扇出晶圓程度的晶片級封裝

Claims (14)

  1. 一種製造半導體裝置的方法，其包括：提供一第一半導體晶粒；將一囊封劑沉積在該第一半導體晶粒的上方；在該第一半導體晶粒的一主動表面上方形成一遮罩層；在該囊封劑和該第一半導體晶粒的上方形成一互連結構；移除該遮罩層以形成一孔穴，該孔穴透過該互連結構延伸以露出該第一半導體晶粒的該主動表面；以及將一第二半導體晶粒鑲嵌在該孔穴中。
  2. 如申請專利範圍第1項的方法，其進一步包含形成一導體直通矽晶穿孔貫穿該第一半導體晶粒。
  3. 如申請專利範圍第1項的方法，其進一步包含在該第二半導體晶粒的上方形成一遮蔽層。
  4. 如申請專利範圍第1項的方法，其進一步包含：提供一暫時性載體；將該第一半導體晶粒鑲嵌在該暫時性載體上，其包含該第一半導體晶粒的主動表面朝向該暫時性載體；以及將該暫時性載體移除以露出該囊封劑。
  5. 如申請專利範圍第4項的方法，其進一步包含：形成一屏障壁於該暫時性載體的上方；將該第一半導體晶粒鑲嵌至該暫時性載體，俾使得該第一半導體晶粒的該主動表面的一部分會駐留在該屏障壁裡面； 將該囊封劑沉積在該第一半導體晶粒與暫時性載體的上方，該屏障壁會防止該囊封劑分散至該第一半導體晶粒的該主動表面的該部分；以及在該囊封劑的上方形成該互連結構，該遮罩層會防止該互連結構形成於該第一半導體晶粒的該主動表面的該部分的上方。
  6. 一種製造半導體裝置的方法，其包括：提供一第一半導體晶粒；將一囊封劑沉積在該第一半導體晶粒的上方；在該半導體晶粒的一第一表面上方形成一遮罩層；在該囊封劑和該第一半導體晶粒的上方形成一第一互連結構，該遮罩層會防止該第一互連結構形成於該第一半導體晶粒的該第一表面之一部分的上方。
  7. 如申請專利範圍第6項的方法，其進一步包含移除在該第一互連結構對面的該囊封劑的一部分以露出該第一半導體晶粒之一第二表面。
  8. 如申請專利範圍第6項的方法，其進一步包含鑲嵌一半導體組件於該第一半導體晶粒之該第一表面上方。
  9. 如申請專利範圍第6項的方法，其進一步包含形成一導體直通矽晶穿孔貫穿該第一半導體晶粒。
  10. 如申請專利範圍第6項的方法，其進一步包含：形成一第二互連結構在該第一半導體晶粒的一第二表面上，其在該第一半導體晶粒的該第一表面的對面；以及將一第二半導體晶粒鑲嵌於該第二互連結構上方。
  11. 一種半導體裝置，其包括： 一半導體晶粒；一囊封劑，其被沉積在該半導體晶粒上方，其中該囊封劑的一第一表面與該半導體晶粒的一主動表面共平面；一第一互連結構，其被形成以與該囊封劑的該第一表面以及該半導體晶粒的該主動表面接觸；一半導體組件，其被放置在該半導體晶粒的該主動表面的上方；以及一凸塊，其被形成在該第一互連結構的上方且自該半導體組件橫向的偏移，該半導體組件包含一高度，其低於該凸塊的高度。
  12. 如申請專利範圍第11項的半導體裝置，其進一步包含一熱分散器，其被鑲嵌至該半導體晶粒上方。
  13. 如申請專利範圍第11項的半導體裝置，其進一步包含一被沉積圍繞該半導體晶粒之該主動表面的屏障材料。
  14. 如申請專利範圍第11項的半導體裝置，其中一遮罩層會防止該第一互連結構形成於該半導體晶粒的該主動表面的上方。
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