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JPH09260552A - 半導体チップの実装構造 - Google Patents

半導体チップの実装構造

Info

Publication number
JPH09260552A
JPH09260552A JP8065871A JP6587196A JPH09260552A JP H09260552 A JPH09260552 A JP H09260552A JP 8065871 A JP8065871 A JP 8065871A JP 6587196 A JP6587196 A JP 6587196A JP H09260552 A JPH09260552 A JP H09260552A
Authority
JP
Japan
Prior art keywords
semiconductor chip
substrate
back surface
ground
mounting structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8065871A
Other languages
English (en)
Inventor
Kenichi Tokuno
健市 得能
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP8065871A priority Critical patent/JPH09260552A/ja
Priority to US08/826,750 priority patent/US5869886A/en
Publication of JPH09260552A publication Critical patent/JPH09260552A/ja
Pending legal-status Critical Current

Links

Classifications

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Abstract

(57)【要約】 【課題】 フリップチップ実装した半導体チップのサブ
ストレート部の電位を安定させる。 【解決手段】 基板６の搭載パッド５と半導体チップ１
の電極とをバンプ３で接続し基板６と半導体チップ１と
の間隙を封止樹脂４で封止した半導体チップ１の裏面と
基板６のグランドパターン７とを導電性樹脂８で接続す
る。これにより半導体チップ１のサブストレート部の電
位が安定し半導体チップ１の動作が安定する。

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は半導体チップの実装
構造に関し、特にフリップチップによる半導体チップの
実装構造に関する。
【０００２】
【従来の技術】従来のフリップチップによる半導体チッ
プの実装構造は、図３に示す様に半導体チップ１と基板
６の搭載パッド５とはバンプ３によって電気的に接続さ
れる構造であり、半導体チップ１のサブストレートもバ
ンプ３によって基板６のグランド電位に接続されてい
る。なお、基板６の表面にはパッド５の部分を除きソル
ダーレジスト９が設けられ、半導体チップ１と基板６の
間には封止樹脂４が設けられている。
【０００３】図４は、リードフレームにガラスなど絶縁
材料を用いて接着され、ダイボンディングによりリード
フレームを介して接地されることがない半導体チップ１
６の平面図である。半導体チップ１６の表面に中央部を
囲むようにグランド用アルミ配線１３を形成し、半導体
チップ１６の表面に設けられた酸化膜からなる絶縁膜の
グランド用アルミ配線１３の下部には多数のコンタクト
部１５を成す開口部が設けられている。また、半導体チ
ップ１６の表面にはグランド用アルミ配線１３に沿って
複数の電極パッド１７が設けられ、その一部分のグラン
ド用電極パッド１４をグランド用アルミ配線１３に接続
している。半導体チップ１６の裏面をガラス等でリード
フレームに接着してパッケージに組立てる場合は、図に
は示していないがグランド用電極パッド１４とパッケー
ジの接地用の外部リードとの間をボンディングワイヤで
接続することにより、半導体チップ１６のサブストレー
トを接地する。
【０００４】半導体チップ１６は表面の周辺部にグラン
ド用アルミ配線１３を張り回し、サブストレートとグラ
ンド用アルミ配線１３とを多数のコンタクト部１５で接
続することにより、サブストレートを安定して接地電位
に保つことができる。
【０００５】なお、半導体チップ１６は、ボンディング
ワイヤによる実装のみならず、グランド用電極パッド１
４を含む電極パッド１７を図示しない配線基板上の搭載
パッドにバンプにより接続することによりフリップチッ
プ実装とすることもできる。
【０００６】
【発明が解決しようとする課題】第１の問題点は、半導
体チップのサブストレートがチップ裏面で接地されるこ
とを前提に設計されている半導体チップでは、図３のよ
うにフリップチップ実装する場合バンプのみを介した接
地となるためサブストレートの電位を安定した接地電位
に保つことが困難であることである。
【０００７】その理由は、チップ裏面での接地に比べバ
ンプを介しての接地では、接地抵抗が大きいからであ
る。
【０００８】第２の問題点は、サブストレートをボンデ
ィングワイヤまたはバンプを介した接地のみでサブスト
レートの接地電位を安定に保つために半導体チップを図
４に示すものにすると、半導体チップの面積が大きくな
り、またパッケージ組立コスト，実装コストが高くなる
ことである。
【０００９】その理由は、チップ表面の周辺にグランド
用アルミ配線が必要で、しかもグランド用アルミ配線を
サブストレートに接続する多数のコンタクトが必要だか
らであり、またグランド用電極パッドへのワイヤのボン
ディングやグランド接続用バンプが多数必要となるから
である。
【００１０】本発明の目的は、フリップチップ実装され
た半導体チップの裏面を、基板のグランドパターンに接
続することにより半導体チップの動作を安定させること
である。
【００１１】
【課題を解決するための手段】本発明の半導体チップの
実装構造は、基板にフリップチップ実装した半導体チッ
プの裏面と、前記基板の電源パターンとを導電性樹脂で
電気的に接続したことを特徴とする。
【００１２】本発明の半導体チップの実装構造は、基板
と、この基板にフリップチップ実装した半導体チップ
と、前記基板および前記半導体チップの間ならびに前記
半導体チップの周囲に充填した封止樹脂と、前記半導体
チップの裏面の少くとも一部および基板の電源パターン
の接続部ならびに前記封止樹脂の表面の少くとも一部に
塗布され前記半導体チップの裏面と前記電源パターンと
を電気的に接続する導電性樹脂とを備えている。
【００１３】本発明の半導体チップのは、基板の裏面に
金属膜を形成しておくのが望ましい。
【００１４】フリップチップ実装した半導体チップの裏
面を導電性樹脂で、基板の電源パターンと接続してい
る。このため、半導体チップのサブストレートの電位が
安定することにより半導体チップの動作が安定する。
【００１５】
【発明の実施の形態】次に、本発明の実施の形態につい
て図面を参照して詳細に説明する。
【００１６】図１は、本発明の実施の形態のフリップチ
ップ実装構造の縦断面図であり、図２は本実施の形態の
平面図である。
【００１７】半導体チップ１の電極パッドと、基板６の
搭載パッド５とは、バンプ３で電気的に接続している。
半導体チップ１と基板２との間には、エポキシ系封止樹
脂４があり、半導体チップ１の回路素子面を外部環境か
ら保護するとともに半導体チップ１を基板６に接着する
ことで固定している。
【００１８】半導体チップ１の裏面には、全蒸着膜２が
形成してあり、この半導体チップ１の裏面と基板６のグ
ランドパターン７とが導電性樹脂８で電気的に接続され
ている。基板６には信号線１１およびスルーホール１２
が設けられている。基板６の表面は搭載パッド５の部お
よびグランドパターン７の電導性樹脂８との接続部分で
ある開講部１０を除きソルダーレジスト９で覆われてい
る。
【００１９】本実施の形態の半導体チップ１の実装は、
次のように行なう。半導体チップ１の電極パッドをバン
プ３で基板６の搭載パッド５に接続する。次に半導体チ
ップ１と基板６との間隙に液状のエポキシ系封止樹脂４
を毛細管現象を利用して流し込んだ後、加熱硬化させ
る。
【００２０】次に半導体チップ１の裏面の一部および基
板６に形成されているグランド用配線パターンのソルダ
レジスト開口部１０から露出している部分ならびにこれ
らの間の封止樹脂４の側面上に銀エポキシペーストを塗
布し、加熱硬化することによって導電性樹脂８とし、半
導体チップ１の裏面の全蒸着膜２とグランドパターン７
との間の電気的な導通を得る。
【００２１】半導体チップ１の裏面と基板６のグランド
用パターン７との間を銀エポキシ樹脂８により十分な接
続面積で電気的に接続しているため、半導体チップ１の
サブストレート部の電位を安定させることができる。こ
のことにより半導体チップ１の動作を安定できる。
【００２２】なお、導電性樹脂８として、銀エポキシ樹
脂の代わりに銅エポキシ樹脂、銀パタジュームエポキシ
樹脂、パラジュームエポキシ樹脂の使用も可能である。
【００２３】また、半導体チップの裏面を導電性樹脂上
の一定電位に保たれた電源パターンに接続することによ
り半導体チップのサブストレートを安定に一定電位に保
持することもできる。
【００２４】
【発明の効果】第１の効果は、フリップチップ実装され
た、半導体チップのサブストレートの電位を安定に一定
電位に保持できるということである。これにより、半導
体チップが安定に動作できるようになる。
【００２５】その理由は、半導体チップの裏面と基板の
グランドパターンなどの電源パターンとを導電性樹脂に
よって電気的に接続し、これらの接続面積を十分に大き
くして半導体チップのサブストレートとグランドパター
ンなどとの間の電気的抵抗を小さくできるからである。
【００２６】第２の効果は、上記第１の効果を有しなが
ら面積の小さい半導体チップを得ることができることで
ある。
【００２７】その理由は、半導体チップの裏面と基板の
グランドパターンとを導電性樹脂で電気的に接続するこ
とにより、半導体チップの表面にグランド用アルミ配線
などが不要となるからである。
【図面の簡単な説明】
【図１】本発明の実施の形態の半導体チップの実装構造
の縦断面図である。
【図２】図１の半導体チップの実装構造の平面図であ
る。
【図３】従来の半導体チップの実装構造の縦断面図であ
る。
【図４】従来の他の実装構造に用いる半導体チップの平
面図である。
【符号の説明】
１ 半導体チップ ２ 金蒸着膜 ３ バンプ ４ 封止樹脂 ５ 搭載パッド ６ 基板 ７ グランド用パターン ８ 導電性樹脂 ９ ソルダーレジスト １０ ソルダーレジスト開口部 １１ 信号線 １２ スルーホール １３ グランド用アルミ配線 １４ グランド用電極パッド １５ コンタクト部 １６ 半導体チップ １７ 電極パッド

Claims (3)

    【特許請求の範囲】
  1. 【請求項１】 基板にフリップチップ実装した半導体チ
    ップの裏面と、前記基板の電源パターンとを導電性樹脂
    で電気的に接続したことを特徴とする半導体チップの実
    装構造。
  2. 【請求項２】 基板と、この基板にフリップチップ実装
    した半導体チップと、前記基板および前記半導体チップ
    の間ならびに前記半導体チップの周囲に充填した封止樹
    脂と、前記半導体チップの裏面の少くとも一部および基
    板の電源パターンの接続部ならびに前記封止樹脂の表面
    の少くとも一部に塗布され前記半導体チップの裏面と前
    記電源パターンとを電気的に接続する導電性樹脂とを含
    むことを特徴とする半導体チップの実装構造。
  3. 【請求項３】 半導体チップの裏面に金属膜が形成され
    た請求項１または２記載の半導体チップの実装構造。
JP8065871A 1996-03-22 1996-03-22 半導体チップの実装構造 Pending JPH09260552A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP8065871A JPH09260552A (ja) 1996-03-22 1996-03-22 半導体チップの実装構造
US08/826,750 US5869886A (en) 1996-03-22 1997-03-24 Flip chip semiconductor mounting structure with electrically conductive resin

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8065871A JPH09260552A (ja) 1996-03-22 1996-03-22 半導体チップの実装構造

Publications (1)

Publication Number Publication Date
JPH09260552A true JPH09260552A (ja) 1997-10-03

Family

ID=13299487

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (2)

Country Link
US (1) US5869886A (ja)
JP (1) JPH09260552A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008148720A (ja) * 2006-12-14 2008-07-03 Hitachi Medical Corp 超音波探触子及び超音波診断装置

Families Citing this family (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2758630B1 (fr) * 1997-01-21 1999-04-09 Thomson Tubes Electroniques Procede de scellement etanche d'un detecteur de rayonnement a l'etat solide et detecteur obtenu par ce procede
JPH10335383A (ja) * 1997-05-28 1998-12-18 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US6049122A (en) * 1997-10-16 2000-04-11 Fujitsu Limited Flip chip mounting substrate with resin filled between substrate and semiconductor chip
US6038133A (en) * 1997-11-25 2000-03-14 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module and method for producing the same
US6201301B1 (en) 1998-01-21 2001-03-13 Lsi Logic Corporation Low cost thermally enhanced flip chip BGA
US6191487B1 (en) * 1998-04-23 2001-02-20 Minco Technology Labs, Inc. Semiconductor and flip chip packages and method having a back-side connection
JP3834424B2 (ja) * 1998-05-29 2006-10-18 株式会社東芝 半導体装置
US6246124B1 (en) 1998-09-16 2001-06-12 International Business Machines Corporation Encapsulated chip module and method of making same
WO2000026959A1 (en) * 1998-10-30 2000-05-11 Seiko Epson Corporation Semiconductor device, method of manufacture thereof, circuit board and electronic device
WO2001008220A1 (fr) * 1999-07-28 2001-02-01 Hitachi, Ltd. Dispositif semi-conducteur
KR100817646B1 (ko) 2000-03-10 2008-03-27 스태츠 칩팩, 엘티디. 플립칩 상호연결 구조물
US10388626B2 (en) * 2000-03-10 2019-08-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming flipchip interconnect structure
JP2001326304A (ja) * 2000-05-15 2001-11-22 Toshiba Corp 半導体装置及びその製造方法
JP3945968B2 (ja) * 2000-09-06 2007-07-18 三洋電機株式会社 半導体装置およびその製造方法
US6486561B1 (en) 2000-09-12 2002-11-26 Luminary Logic, Ltd. Semiconductor light emitting element formed on a clear or translucent substrate
JP3660275B2 (ja) * 2001-06-14 2005-06-15 シャープ株式会社 半導体装置およびその製造方法
WO2005048307A2 (en) * 2003-11-08 2005-05-26 Chippac, Inc. Flip chip interconnection pad layout
US8853001B2 (en) * 2003-11-08 2014-10-07 Stats Chippac, Ltd. Semiconductor device and method of forming pad layout for flipchip semiconductor die
US8216930B2 (en) * 2006-12-14 2012-07-10 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
KR101286379B1 (ko) 2003-11-10 2013-07-15 스태츠 칩팩, 엘티디. 범프-온-리드 플립 칩 인터커넥션
USRE44500E1 (en) 2003-11-10 2013-09-17 Stats Chippac, Ltd. Semiconductor device and method of forming composite bump-on-lead interconnection
US8574959B2 (en) 2003-11-10 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
USRE47600E1 (en) 2003-11-10 2019-09-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US9029196B2 (en) 2003-11-10 2015-05-12 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US7659633B2 (en) 2004-11-10 2010-02-09 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
US20070105277A1 (en) 2004-11-10 2007-05-10 Stats Chippac Ltd. Solder joint flip chip interconnection
US8026128B2 (en) 2004-11-10 2011-09-27 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US8129841B2 (en) * 2006-12-14 2012-03-06 Stats Chippac, Ltd. Solder joint flip chip interconnection
US8350384B2 (en) * 2009-11-24 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US8076232B2 (en) 2008-04-03 2011-12-13 Stats Chippac, Ltd. Semiconductor device and method of forming composite bump-on-lead interconnection
US8841779B2 (en) 2005-03-25 2014-09-23 Stats Chippac, Ltd. Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate
WO2006105015A2 (en) 2005-03-25 2006-10-05 Stats Chippac Ltd. Flip chip interconnection having narrow interconnection sites on the substrate
US20060255473A1 (en) 2005-05-16 2006-11-16 Stats Chippac Ltd. Flip chip interconnect solder mask
US9258904B2 (en) * 2005-05-16 2016-02-09 Stats Chippac, Ltd. Semiconductor device and method of forming narrow interconnect sites on substrate with elongated mask openings
US20070152310A1 (en) * 2005-12-29 2007-07-05 Tessera, Inc. Electrical ground method for ball stack package
US20070275504A1 (en) * 2006-05-29 2007-11-29 Henkel Japan, Ltd. Electronic Component Mounting Structure
US9847309B2 (en) 2006-09-22 2017-12-19 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming vertical interconnect structure between semiconductor die and substrate
US7713782B2 (en) * 2006-09-22 2010-05-11 Stats Chippac, Inc. Fusible I/O interconnection systems and methods for flip-chip packaging involving substrate-mounted stud-bumps
US8349721B2 (en) * 2008-03-19 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding
US7759137B2 (en) * 2008-03-25 2010-07-20 Stats Chippac, Ltd. Flip chip interconnection structure with bump on partial pad and method thereof
US9345148B2 (en) 2008-03-25 2016-05-17 Stats Chippac, Ltd. Semiconductor device and method of forming flipchip interconnection structure with bump on partial pad
US20090250814A1 (en) * 2008-04-03 2009-10-08 Stats Chippac, Ltd. Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method Thereof
US7897502B2 (en) 2008-09-10 2011-03-01 Stats Chippac, Ltd. Method of forming vertically offset bond on trace interconnects on recessed and raised bond fingers
US8659172B2 (en) 2008-12-31 2014-02-25 Stats Chippac, Ltd. Semiconductor device and method of confining conductive bump material with solder mask patch
US8198186B2 (en) * 2008-12-31 2012-06-12 Stats Chippac, Ltd. Semiconductor device and method of confining conductive bump material during reflow with solder mask patch
US20100237500A1 (en) * 2009-03-20 2010-09-23 Stats Chippac, Ltd. Semiconductor Substrate and Method of Forming Conformal Solder Wet-Enhancement Layer on Bump-on-Lead Site
US7871860B1 (en) * 2009-11-17 2011-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of semiconductor packaging
US8039384B2 (en) 2010-03-09 2011-10-18 Stats Chippac, Ltd. Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces
US8409978B2 (en) 2010-06-24 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming vertically offset bond on trace interconnect structure on leadframe
US8492197B2 (en) 2010-08-17 2013-07-23 Stats Chippac, Ltd. Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate
US8435834B2 (en) 2010-09-13 2013-05-07 Stats Chippac, Ltd. Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in FO-WLCSP
US11270972B2 (en) * 2019-06-12 2022-03-08 Nxp B.V. Package with conductive underfill ground plane

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07111299A (ja) * 1993-10-14 1995-04-25 Fuji Xerox Co Ltd 混成集積回路

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0815152B2 (ja) * 1986-01-27 1996-02-14 三菱電機株式会社 半導体装置及びその製造方法
EP0536418B1 (en) * 1991-04-26 1999-07-28 Citizen Watch Co. Ltd. Method of manufacturing a semiconductor device terminal structure
US5334857A (en) * 1992-04-06 1994-08-02 Motorola, Inc. Semiconductor device with test-only contacts and method for making the same
US5508561A (en) * 1993-11-15 1996-04-16 Nec Corporation Apparatus for forming a double-bump structure used for flip-chip mounting

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07111299A (ja) * 1993-10-14 1995-04-25 Fuji Xerox Co Ltd 混成集積回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008148720A (ja) * 2006-12-14 2008-07-03 Hitachi Medical Corp 超音波探触子及び超音波診断装置

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