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JPS6437852A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6437852A
JPS6437852A JP19486287A JP19486287A JPS6437852A JP S6437852 A JPS6437852 A JP S6437852A JP 19486287 A JP19486287 A JP 19486287A JP 19486287 A JP19486287 A JP 19486287A JP S6437852 A JPS6437852 A JP S6437852A
Authority
JP
Japan
Prior art keywords
film
inter
layer
films
deposited
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19486287A
Other languages
Japanese (ja)
Inventor
Yoshiki Okumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP19486287A priority Critical patent/JPS6437852A/en
Publication of JPS6437852A publication Critical patent/JPS6437852A/en
Pending legal-status Critical Current

Links

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To manufacture a semiconductor device simultaneously satisfying the film thickness controllability and tapering of an inter-lay er insulating film by depositing a polysilicon material film as a gate uppermost layer and an intermediate layer in inter-multilayer insulating films and changing these films into silicon oxide films through heat treatment. CONSTITUTION:An LDD-structure transistor TR is formed, and an oxide film 7, a thin polysilicon material film 8 and an oxide film 9 as inter-layer insulating films are deposited in succession. A resist 13 is patterned through photoengraving, the film 8 is employ ed as a monitor for detecting an end point as important point of etching, and the oxide film is etched in an isotropic manner. The film 8 is oxidized completely, and changed into an Si oxide film 8a. The film thickness controllability and tapering of the inter-layer insulating film 9, etc., can be satisfied simultaneously through heat treatment. Polysilicon 11 is deposited, a high melting-point metallic silicide 12 is deposited, and a semiconductor substrate 1 and polysilicon 11 and the metallic silicide 12 are connected. An upper layer wiring for a transfer gate having the two layer structure of the metallic silicide 12 and poly-Si is executed through replication and machining.
JP19486287A 1987-08-04 1987-08-04 Manufacture of semiconductor device Pending JPS6437852A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19486287A JPS6437852A (en) 1987-08-04 1987-08-04 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19486287A JPS6437852A (en) 1987-08-04 1987-08-04 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6437852A true JPS6437852A (en) 1989-02-08

Family

ID=16331529

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19486287A Pending JPS6437852A (en) 1987-08-04 1987-08-04 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6437852A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4981810A (en) * 1990-02-16 1991-01-01 Micron Technology, Inc. Process for creating field effect transistors having reduced-slope, staircase-profile sidewall spacers
US5019527A (en) * 1989-08-11 1991-05-28 Kabushiki Kaisha Toshiba Method of manufacturing non-volatile semiconductor memories, in which selective removal of field oxidation film for forming source region and self-adjusted treatment for forming contact portion are simultaneously performed
US5202277A (en) * 1989-12-08 1993-04-13 Matsushita Electric Industrial Co., Ltd. Method of fabricating a semiconductor device
US5221635A (en) * 1991-12-17 1993-06-22 Texas Instruments Incorporated Method of making a field-effect transistor
JPH05160272A (en) * 1991-12-04 1993-06-25 Nec Corp Manufacturing method of semiconductor device
US5679589A (en) * 1989-10-17 1997-10-21 Lucent Technologies Inc. FET with gate spacer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61100936A (en) * 1984-10-23 1986-05-19 Pioneer Electronic Corp Manufacture of semicondcutor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61100936A (en) * 1984-10-23 1986-05-19 Pioneer Electronic Corp Manufacture of semicondcutor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5019527A (en) * 1989-08-11 1991-05-28 Kabushiki Kaisha Toshiba Method of manufacturing non-volatile semiconductor memories, in which selective removal of field oxidation film for forming source region and self-adjusted treatment for forming contact portion are simultaneously performed
US5679589A (en) * 1989-10-17 1997-10-21 Lucent Technologies Inc. FET with gate spacer
US5202277A (en) * 1989-12-08 1993-04-13 Matsushita Electric Industrial Co., Ltd. Method of fabricating a semiconductor device
US4981810A (en) * 1990-02-16 1991-01-01 Micron Technology, Inc. Process for creating field effect transistors having reduced-slope, staircase-profile sidewall spacers
JPH05160272A (en) * 1991-12-04 1993-06-25 Nec Corp Manufacturing method of semiconductor device
US5221635A (en) * 1991-12-17 1993-06-22 Texas Instruments Incorporated Method of making a field-effect transistor

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